DE3279495D1 - Method of manufacturing a semi-conductor device comprising dielectric isolation regions - Google Patents

Method of manufacturing a semi-conductor device comprising dielectric isolation regions

Info

Publication number
DE3279495D1
DE3279495D1 DE8282109009T DE3279495T DE3279495D1 DE 3279495 D1 DE3279495 D1 DE 3279495D1 DE 8282109009 T DE8282109009 T DE 8282109009T DE 3279495 T DE3279495 T DE 3279495T DE 3279495 D1 DE3279495 D1 DE 3279495D1
Authority
DE
Germany
Prior art keywords
semi
manufacturing
isolation regions
dielectric isolation
conductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282109009T
Other languages
English (en)
Inventor
Shuichi Kameyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3279495D1 publication Critical patent/DE3279495D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
DE8282109009T 1982-02-03 1982-09-29 Method of manufacturing a semi-conductor device comprising dielectric isolation regions Expired DE3279495D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57014853A JPS58132946A (ja) 1982-02-03 1982-02-03 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE3279495D1 true DE3279495D1 (en) 1989-04-06

Family

ID=11872585

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282109009T Expired DE3279495D1 (en) 1982-02-03 1982-09-29 Method of manufacturing a semi-conductor device comprising dielectric isolation regions

Country Status (4)

Country Link
US (1) US4445967A (de)
EP (1) EP0091507B1 (de)
JP (1) JPS58132946A (de)
DE (1) DE3279495D1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4564997A (en) * 1981-04-21 1986-01-21 Nippon-Telegraph And Telephone Public Corporation Semiconductor device and manufacturing process thereof
JPS58165341A (ja) * 1982-03-26 1983-09-30 Toshiba Corp 半導体装置の製造方法
JPS59124141A (ja) * 1982-12-28 1984-07-18 Toshiba Corp 半導体装置の製造方法
JPS59139643A (ja) * 1983-01-31 1984-08-10 Hitachi Ltd 半導体装置およびその製造方法
US4771328A (en) * 1983-10-13 1988-09-13 International Business Machine Corporation Semiconductor device and process
FR2554638A1 (fr) * 1983-11-04 1985-05-10 Efcis Procede de fabrication de structures integrees de silicium sur ilots isoles du substrat
US4533430A (en) * 1984-01-04 1985-08-06 Advanced Micro Devices, Inc. Process for forming slots having near vertical sidewalls at their upper extremities
FR2562326B1 (fr) * 1984-03-30 1987-01-23 Bois Daniel Procede de fabrication de zones d'isolation electrique des composants d'un circuit integre
US4495025A (en) * 1984-04-06 1985-01-22 Advanced Micro Devices, Inc. Process for forming grooves having different depths using a single masking step
FR2566179B1 (fr) * 1984-06-14 1986-08-22 Commissariat Energie Atomique Procede d'autopositionnement d'un oxyde de champ localise par rapport a une tranchee d'isolement
US4538343A (en) * 1984-06-15 1985-09-03 Texas Instruments Incorporated Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking
JPS6181653A (ja) * 1984-09-28 1986-04-25 Nec Corp 半導体装置の自己整合誘電体分離方法
US4671970A (en) * 1986-02-05 1987-06-09 Ncr Corporation Trench filling and planarization process
US4837176A (en) * 1987-01-30 1989-06-06 Motorola Inc. Integrated circuit structures having polycrystalline electrode contacts and process
US4740478A (en) * 1987-01-30 1988-04-26 Motorola Inc. Integrated circuit method using double implant doping
US5067002A (en) * 1987-01-30 1991-11-19 Motorola, Inc. Integrated circuit structures having polycrystalline electrode contacts
US5904539A (en) * 1996-03-21 1999-05-18 Advanced Micro Devices, Inc. Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties
WO1997038442A1 (en) * 1996-04-10 1997-10-16 Advanced Micro Devices, Inc. Semiconductor trench isolation with improved planarization methodology
US5926713A (en) * 1996-04-17 1999-07-20 Advanced Micro Devices, Inc. Method for achieving global planarization by forming minimum mesas in large field areas
US5899727A (en) * 1996-05-02 1999-05-04 Advanced Micro Devices, Inc. Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
KR100232522B1 (ko) * 1997-02-11 1999-12-01 김영환 반도체장치의 소자격리막 형성방법
JPH1140797A (ja) * 1997-05-19 1999-02-12 Matsushita Electron Corp 半導体装置及びその製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL170348C (nl) * 1970-07-10 1982-10-18 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult.
US4037306A (en) * 1975-10-02 1977-07-26 Motorola, Inc. Integrated circuit and method
US4238278A (en) * 1979-06-14 1980-12-09 International Business Machines Corporation Polycrystalline silicon oxidation method for making shallow and deep isolation trenches
US4318751A (en) * 1980-03-13 1982-03-09 International Business Machines Corporation Self-aligned process for providing an improved high performance bipolar transistor
US4394196A (en) * 1980-07-16 1983-07-19 Tokyo Shibaura Denki Kabushiki Kaisha Method of etching, refilling and etching dielectric grooves for isolating micron size device regions
FR2498812A1 (fr) * 1981-01-27 1982-07-30 Thomson Csf Structure de transistors dans un circuit integre et son procede de fabrication
US4472240A (en) * 1981-08-21 1984-09-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
EP0091507A2 (de) 1983-10-19
US4445967A (en) 1984-05-01
JPS58132946A (ja) 1983-08-08
EP0091507A3 (en) 1986-04-16
EP0091507B1 (de) 1989-03-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee