DE3277562D1 - Cmos circuitry for dynamic translation of input signals at ttl levels into corresponding output signals at cmos levels - Google Patents

Cmos circuitry for dynamic translation of input signals at ttl levels into corresponding output signals at cmos levels

Info

Publication number
DE3277562D1
DE3277562D1 DE8282401749T DE3277562T DE3277562D1 DE 3277562 D1 DE3277562 D1 DE 3277562D1 DE 8282401749 T DE8282401749 T DE 8282401749T DE 3277562 T DE3277562 T DE 3277562T DE 3277562 D1 DE3277562 D1 DE 3277562D1
Authority
DE
Germany
Prior art keywords
levels
cmos
corresponding output
dynamic translation
output signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282401749T
Other languages
German (de)
English (en)
Inventor
Thomas J Davies
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Application granted granted Critical
Publication of DE3277562D1 publication Critical patent/DE3277562D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
DE8282401749T 1981-10-02 1982-09-28 Cmos circuitry for dynamic translation of input signals at ttl levels into corresponding output signals at cmos levels Expired DE3277562D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/308,073 US4485317A (en) 1981-10-02 1981-10-02 Dynamic TTL input comparator for CMOS devices

Publications (1)

Publication Number Publication Date
DE3277562D1 true DE3277562D1 (en) 1987-12-03

Family

ID=23192431

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282401749T Expired DE3277562D1 (en) 1981-10-02 1982-09-28 Cmos circuitry for dynamic translation of input signals at ttl levels into corresponding output signals at cmos levels

Country Status (5)

Country Link
US (1) US4485317A (enExample)
EP (1) EP0076733B1 (enExample)
JP (1) JPS5871731A (enExample)
CA (1) CA1199686A (enExample)
DE (1) DE3277562D1 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58221521A (ja) * 1982-06-18 1983-12-23 Toshiba Corp 基準電位発生回路およびこれを用いた入力回路
US4496857A (en) * 1982-11-01 1985-01-29 International Business Machines Corporation High speed low power MOS buffer circuit for converting TTL logic signal levels to MOS logic signal levels
EP0111230B1 (en) * 1982-11-26 1987-03-11 Nec Corporation Voltage comparator circuit
JPS6010495A (ja) * 1983-06-30 1985-01-19 Fujitsu Ltd センスアンプ
BE897771A (nl) * 1983-09-19 1984-03-19 Bell Telephone Mfg Elektronische ketens en signaalgenerator die daarvan gebruik maakt
US4561702A (en) * 1984-05-09 1985-12-31 Texas Instruments Incorporated CMOS Address buffer circuit
US4539495A (en) * 1984-05-24 1985-09-03 General Electric Company Voltage comparator
JPS62272722A (ja) * 1986-05-21 1987-11-26 Clarion Co Ltd Ｔｔｌ論理レベルｃｍｏｓ入力バツフア
LU86789A1 (de) * 1986-06-24 1987-07-24 Siemens Ag Abtasttaktgesteuerte schwellwertschaltung in c-mos-technik
IT1201860B (it) * 1986-12-10 1989-02-02 Sgs Microelettronica Spa Circuito logico cmos
US4717845A (en) * 1987-01-02 1988-01-05 Sgs Semiconductor Corporation TTL compatible CMOS input circuit
US4841175A (en) * 1987-01-23 1989-06-20 Siemens Aktiengesellschaft ECL-compatible input/output circuits in CMOS technology
US4970407A (en) * 1988-06-09 1990-11-13 National Semiconductor Corporation Asynchronously loadable D-type flip-flop
JPH0355914A (ja) * 1989-07-25 1991-03-11 Fujitsu Ltd 半導体装置
US5455526A (en) * 1994-08-10 1995-10-03 Cirrus Logic, Inc. Digital voltage shifters and systems using the same
GB2335556B (en) 1998-03-18 2002-10-30 Ericsson Telefon Ab L M Switch circuit
JP2007134901A (ja) * 2005-11-09 2007-05-31 Technology Alliance Group Inc 実装基板の電源制御装置および半導体基板
US7498850B2 (en) * 2007-06-22 2009-03-03 Intel Corporation Compensated comparator for use in lower voltage, higher speed non-volatile memory
US7847576B2 (en) * 2009-02-26 2010-12-07 Advantest Corporation Comparator with latching function
JP5946683B2 (ja) * 2011-04-22 2016-07-06 株式会社半導体エネルギー研究所 半導体装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3555307A (en) * 1967-10-16 1971-01-12 Hitachi Ltd Flip-flop
US3812384A (en) * 1973-05-17 1974-05-21 Rca Corp Set-reset flip-flop
US3959781A (en) * 1974-11-04 1976-05-25 Intel Corporation Semiconductor random access memory
US3938109A (en) * 1975-02-19 1976-02-10 Intel Corporation High speed ECL compatible MOS-Ram
US4096402A (en) * 1975-12-29 1978-06-20 Mostek Corporation MOSFET buffer for TTL logic input and method of operation
US4039862A (en) * 1976-01-19 1977-08-02 Rca Corporation Level shift circuit
US4110639A (en) * 1976-12-09 1978-08-29 Texas Instruments Incorporated Address buffer circuit for high speed semiconductor memory
JPS54116169A (en) * 1978-03-01 1979-09-10 Toshiba Corp Logic signal level conversion circuit
US4216390A (en) * 1978-10-04 1980-08-05 Rca Corporation Level shift circuit
US4380710A (en) * 1981-02-05 1983-04-19 Harris Corporation TTL to CMOS Interface circuit

Also Published As

Publication number Publication date
JPH0245851B2 (enExample) 1990-10-12
EP0076733A2 (en) 1983-04-13
EP0076733B1 (en) 1987-10-28
US4485317A (en) 1984-11-27
JPS5871731A (ja) 1983-04-28
EP0076733A3 (en) 1984-08-01
CA1199686A (en) 1986-01-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition