DE3274923D1 - A method of producing a semiconductor device - Google Patents

A method of producing a semiconductor device

Info

Publication number
DE3274923D1
DE3274923D1 DE8282106245T DE3274923T DE3274923D1 DE 3274923 D1 DE3274923 D1 DE 3274923D1 DE 8282106245 T DE8282106245 T DE 8282106245T DE 3274923 T DE3274923 T DE 3274923T DE 3274923 D1 DE3274923 D1 DE 3274923D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282106245T
Other languages
English (en)
Inventor
Hiroshi Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP11046681A external-priority patent/JPS5943098B2/ja
Priority claimed from JP11186381A external-priority patent/JPS5943099B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3274923D1 publication Critical patent/DE3274923D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Bipolar Transistors (AREA)
DE8282106245T 1981-07-15 1982-07-13 A method of producing a semiconductor device Expired DE3274923D1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11046681A JPS5943098B2 (ja) 1981-07-15 1981-07-15 半導体装置の製造方法
JP11186381A JPS5943099B2 (ja) 1981-07-17 1981-07-17 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE3274923D1 true DE3274923D1 (en) 1987-02-05

Family

ID=26450098

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282106245T Expired DE3274923D1 (en) 1981-07-15 1982-07-13 A method of producing a semiconductor device

Country Status (3)

Country Link
US (1) US4465528A (de)
EP (1) EP0070499B1 (de)
DE (1) DE3274923D1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6057952A (ja) * 1983-09-09 1985-04-03 Toshiba Corp 半導体装置の製造方法
JPH0817180B2 (ja) * 1989-06-27 1996-02-21 株式会社東芝 半導体装置の製造方法
US5629218A (en) * 1989-12-19 1997-05-13 Texas Instruments Incorporated Method for forming a field-effect transistor including a mask body and source/drain contacts
US5279976A (en) * 1991-05-03 1994-01-18 Motorola, Inc. Method for fabricating a semiconductor device having a shallow doped region
US5228808A (en) * 1991-11-27 1993-07-20 Chemical Lime Company Method for preventing the adverse effects of swell in sulfate bearing, expansive clay soils
EP0605946B1 (de) * 1992-11-12 1999-02-24 National Semiconductor Corporation Schmale Basis-Effekte vermeidendes Verfahren für einen Transistor
US5338695A (en) * 1992-11-24 1994-08-16 National Semiconductor Corporation Making walled emitter bipolar transistor with reduced base narrowing
US7247578B2 (en) * 2003-12-30 2007-07-24 Intel Corporation Method of varying etch selectivities of a film

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4074304A (en) * 1974-10-04 1978-02-14 Nippon Electric Company, Ltd. Semiconductor device having a miniature junction area and process for fabricating same
US4063973A (en) * 1975-11-10 1977-12-20 Tokyo Shibaura Electric Co., Ltd. Method of making a semiconductor device
US4115797A (en) * 1976-10-04 1978-09-19 Fairchild Camera And Instrument Corporation Integrated injection logic with heavily doped injector base self-aligned with injector emitter and collector
US4092209A (en) * 1976-12-30 1978-05-30 Rca Corp. Silicon implanted and bombarded with phosphorus ions
US4111726A (en) * 1977-04-01 1978-09-05 Burroughs Corporation Bipolar integrated circuit process by separately forming active and inactive base regions
US4118250A (en) * 1977-12-30 1978-10-03 International Business Machines Corporation Process for producing integrated circuit devices by ion implantation
US4157269A (en) * 1978-06-06 1979-06-05 International Business Machines Corporation Utilizing polysilicon diffusion sources and special masking techniques
CA1129118A (en) * 1978-07-19 1982-08-03 Tetsushi Sakai Semiconductor devices and method of manufacturing the same
US4199380A (en) * 1978-11-13 1980-04-22 Motorola, Inc. Integrated circuit method
JPS5852339B2 (ja) * 1979-03-20 1983-11-22 富士通株式会社 半導体装置の製造方法
US4242791A (en) * 1979-09-21 1981-01-06 International Business Machines Corporation High performance bipolar transistors fabricated by post emitter base implantation process
US4318751A (en) * 1980-03-13 1982-03-09 International Business Machines Corporation Self-aligned process for providing an improved high performance bipolar transistor

Also Published As

Publication number Publication date
US4465528A (en) 1984-08-14
EP0070499A3 (en) 1984-01-11
EP0070499B1 (de) 1986-12-30
EP0070499A2 (de) 1983-01-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee