DE3248566C2 - Method and circuit arrangement for the transmission of data signals - Google Patents

Abstract

In certain cases it is advisable not to transmit a complete multiplex signal (for example the complete multiplex signal of 64 kbit / s according to CCITT recommendation X.51) or a single channel, but rather a single channel group. A channel group is composed of k channels in a homogeneous time division multiplex, each channel having the same envelope structure with a permanently assigned synchronization bit. The channels are arranged in the channel group envelope-nested. The frame synchronization information is given by the fact that k consecutive synchronization bits in a channel group are the same and the synchronization bits of consecutive groups with k envelopes each are alternately binary "0" and binary "1".

Description

characterized in that k successive synchronization bits in a channel group are the same and the synchronization bits are alternately binary "0" and binary "1" in consecutive groups with k envelopes each.

2. The method according to claim 1, characterized in that the synchronization bits are consecutive Envelopes of each individual, non-nested channel alternating binary "0" and binary "1" are.

3. Circuit arrangement for the reception-side detection of frame synchronization and for detection of the number k of channels occurring in a channel group according to claim 1 or 2, with k = 2 ^m (ot = 0.1, 2.3, ...) channels, with a Envelope of a channel consisting of η bit, characterized in that the received bit sequence (a _x ) is compared by means of a first antivalence element (MO) with the same bit sequence (SRI) delayed by η clocks (71,

that the bit sequence (b _x ) present at the output of the anlivalence element (MO) is fed to the first input of a first AND gate (t / 0),
that the output of the first AND gate (i / 0) is connected to the input of a k ■ η-stage shift register (SRI) ,

that the output of the shift register (SRI) is fed back to the second input of the first AND gate (i / 0),

that in the shift register (SRZ) taps after /? · N, mW. ρ = 1,2,4, ..., A :, it is provided that all levels of the shift register (SRI) are set to "1" at the beginning of the synchronization search and channel number determination,
that the input and the taps of the shift register (SRI) are fed to a test circuit (PR) and an output logic (Z.)
and that the output logic (Z.) has k outputs (A 1, A 2, A4) from whose output signals the frame synchronization can be derived and the number of existing channels can be recognized.

4. Circuit arrangement according to claim 3, characterized in that the test circuit (PR) releases the outputs (Al, Al, A4) of the output logic (L) only when a synchronization bit occurs.

5. Circuit arrangement according to claim 4, characterized in that the test circuit (PR) consists of a «-digit counter (Z), a second antivalence element (Ml) and an OR gate (Ol) that the input and the taps of the shift register (SR2) fed to the OR gate (01). The invention relates to a method for transmitting data signals in channel groups using the time division multiplex method according to the preamble of claim 1.

Time division multiplexes for the transmission of data signals can contain several channel groups, which in turn can again be homogeneously divided into one or more channels. Such a multiplexing scheme is for example defined in recommendation X.51 of the CCITT. This contains five channel groups with a bit rate of 12 kbit / s each. Together with a padding bit sequence of 4 kbit / s, this results, among other things, on the receiving end the search for and constant control of the frame synchronism enables a total bit rate to be transmitted of 64 kbit / s. However, details of this frame structure play a role in the method according to the invention not matter.

Each of the channel groups mentioned can be divided homogeneously into one, two, four, eight or sixteen channels The bit rates of these channels are 12, 6, 3.1.5 or 0.75 kbit / s. The homogeneous division into 8 channels at 1.5 kbit / s each is not mentioned in the above recommendation, but is also mentioned applied.

According to Recommendation X.51, the individual channels have a 10-bit envelope structure, as shown in FIG. 1. An envelope consists of the status bil S, which is used to differentiate between the user data transmission and signaling status, the synchronization bit (alignment bit) A and 8 information bits. The individual channels are nested in envelopes in a channel group. The envelopes and bits associated with a particular channel have clearly defined places within the frame of the time division multiplex signal.

In certain cases, for example if a subscriber needs more than one channel, it makes sense or, if necessary, not a complete multiplex signal (for example the complete X.51 multiplex signal mentioned above of 64 kbit / s) or a single channel, but a single channel group. This single channel group can, for. B. be removed from an X.51 multiplex signal or it can have been compiled from individual channels for joint transmission.

About the resolution at the receiving end into the individual channels or the correct classification of the channel group To enable another multiplex signal, this individual channel group must have frame synchronization information contain. This can be done, for example, by adding a Frame sync bit sequence is added, as in the formation of the above-mentioned X.51 multiplex signal the case is. However, this has the disadvantage that the transmission rate is increased.

Another possibility is the envelope synchronization sequence (A-bit sequence) of the successive »channels on the transmit side by means of a frame synchronization bit sequence to replace. This is from DE-OS 3002929 (Claim 2) and for a multiplex signal according to the CCITT recommendation X.50 from the NTG technical reports, Volume 55 (1976), "Datennetze", pages 268 to 269 (section "3. Multiplexer for Envelopes") known. On the sending side, the is marked here Frame phase by overwriting the envelope ίο synchronization bits with the frame synchronization bits. This can mean that the frame length of the multiplex signal is greater than the length of the channel group, especially if a channel group contains a relatively small number of channels, which is on the Receiving side an increased effort in demultiplexing of the received multiplex signal and when assigning the envelopes to the corresponding channels means.

The object of the invention is to provide a method of the type mentioned at the outset in which the frame length of the multiplex signal remains as short as possible, but is in no way larger than a channel group.

The solution to this problem is given in the characterizing part of claim 1.

An advantage of this solution according to the invention is that on the receiving side the Number of channels in a channel group can be determined in a simple manner, since the beginning a channel group and thus the size of a multiplex frame by changing the binary stateeu the synchronization bit sequence is specified.

The method can be used particularly advantageously when the synchronization bit sequence (A bit sequence) is each individual channel always the sequence 101010 ... is, which applies in the cases that have become known so far, because then on the receiving side after the demultiplexing of the channel group signal, the channel-by-channel introduction of new ones Envelope synchronization bits are omitted. In the prior art, the signal must be on both the sending and receiving sides processed while the synchronization bit sequence (A bit sequence) of the individual channels, from which the channel group to be transmitted is composed, not changed at all or at most must be inverted on the transmit side. In any case, there is no need to introduce new channels on the receiving side Envelope sync bits. If an inversion of the synchronization bit is necessary on the transmission side, this can be done by an immediate inversion of the synchronization bit or by delaying the channel signal by the Duration of an envelope. A delay in the channel signal is common when classifying it in a multiplex necessary anyway.

A circuit arrangement and advantageous refinements for the detection of the Frame synchronization and the number of channels occurring in a channel group are in the other subclaims specified.

The following exemplary embodiments of the method according to the invention are illustrated in the drawings and circuit arrangements for this purpose. It shows

1 shows a 10-bit envelope of a channel according to FIG CCITT recommendation X.51,

2 shows the representation of a channel group with four channels,

3A shows the representation of the synchronization bits of a Channel group with two channels,

3B shows the representation of the synchronization bits of a channel group with eight channels,

4 shows a circuit arrangement for carrying out the method in a channel group with four channels, FIG. 5 shows a pulse diagram for FIG. 4,

6 shows a circuit arrangement for the detection of frame synchronization at the receiving end and FIG the channel group subdivision with a maximum of four occurring channels.

In the data signal shown in FIG. 2, a channel group consists, for example, of k = 4 channels. The synchronization bits in the second position of the envelopes are all "1" in the channel group shown in full. In the preceding and following signal group, all synchronization bits are "0". The start of a multiplex frame is thus determined by the change in the binary state of the synchronization bit sequence (A bit sequence).

As can also be seen from FIGS. 3A and 3B, the frame length corresponds to one of these formed multiplex signals each the length of a channel group, corresponding to the number of in one Channel group existing channels. 3A shows this on the basis of the synchronization bit sequence one of two Channels per channel group and FIG. 3B based on the synchronization bit sequence one of eight channels per channel group existing multiplex signal. So if fewer or more channels are combined in the multiplex, this results in shorter or longer distances between the transitions (change in the binary state) in the synchronization bit sequence. This has the advantage that the frame length is as short as possible remain. This also enables the number of channels in the multiplex to be recognized on the receiving side.

The exemplary embodiment of a circuit arrangement shown in FIG. 4 for carrying out the method consists of the assembly G and the channel assemblies Kl, Kl, K3 and K4. A channel assembly is required for each channel of a channel group, each having the same structure, which is why only the channel assembly Kl is shown in detail here. The example shown is designed for four channels. The signals coming from module G are sent to all channel modules Kl. . K4 supplied. According to the number of channels, the multiplexer M of the assembly G contains four inputs El, El, £ 3 and EA.

In addition to the multiplexer M , the assembly G in FIG. 4 (see also the pulse diagrams in FIG. 5) contains the flip-flops a, b, d, e, g, A, m, the NAND gates h, i, the 5: 1 frequency divider c and the 4: 1 frequency divider 1. The basic clock Tg is fed to the clock input of the first flip-flop α. The clock TO with which the multiplex signal DO is read from the multiplexer M with the aid of the flip-flop m is present at the non-inverting output of the second flip-flop b. So it is Tg = 470. The clocks 71, 72, 73, TA are obtained from the clock TO via the 4: 1 frequency divider, with which the data signals Dl, Dl, D3, DA in the channel modules ATI, Kl, K3, KA to be taken over. Since all four channel assemblies have the same structure, only channel assembly K1 will be considered in the following. This consists of the register η with serial input and parallel output, the intermediate register ο with parallel input and parallel output, the register ρ with parallel input and serial output and the AND gate q. The number of storage locations in the registers η, ο, ρ corresponds to the number of bit locations in each case

Envelopes. The data signal Dl of the first channel is thus given with the clock 71 in the register η . With the envelope clock £ 71, which can be derived from the data signal Dl , the data are transferred to the intermediate register ο by envelope. With the control s signal L (L = LOAD) from the flip-flop g and the clock Ti from the NAND circuit ι of the assembly G , the content of the intermediate register ο is transferred to the register ρ . The synchronization bit (alignment bit A ) is replaced by bit ^ 41 contained in the kdsr module G flip-flop. The new synchronization bit is the same for all channels within a channel group, ie here within a frame of the multiplex signal, and changes its polarity from channel group to channel group. This replacement is practically a keeper. or an inversion of the original synchronization bit sequence if the synchronization bits of successive envelopes of each individual, non-interleaved channel are alternately ο and 1.

The content of the registers ρ in the channel assemblies Kl. . . K4 is serially transmitted in turn to the flip-flop m via the 4: 1 multiplexer M of the assembly G and then forms the multiplex signal DO. At the beginning of each cycle of the multiplexer M , the registers ρ of the channel assemblies Kl ... KA are loaded with the status bit and the information bits of the next envelopes by the parallel transfer of the contents of the intermediate register ο. The new synchronization bit is taken from the flip-flop k . The takeover is controlled by the logic consisting of the flip-flop g and the AND gates h, i. This switches the mode of operation of the registers ρ for a 7D half cycle from the shift mode (S = Shift) to the load mode (L = LOAD) and feeds an intermediate clock pulse to the registers ρ via the clock inputs (compare Ti in FIG. 5) with which the parallel data transfer takes place. Thereafter, the circuit g, h, i goes back to the normal state. To prevent a storage process in the intermediate register ο while registerp is being loaded, the AND gate q suppresses any transfer pulse £ 71 during the loading time.

Fig. 6 shows an embodiment of a circuit arrangement which when using the invention Method on the receiving side, the frame synchronization and the number of in a channel group recognizes and checks occurring channels. For a better overview, what is shown here is limited Embodiment to a maximum of four occurring channels, d. H. when applying the procedure to a Channel group according to CCITT recommendation X.51 contains the multiplex signal (the channel group) either one channel at 12 kbit / s or 2 channels at 6 kbit / s each or 4 channels at 3 kbit / s each.

The received bit sequence a _x is fed to a shift register SRI and compared with the same bit sequence delayed by 10 clocks T by means of an exclusive OR element (modulo 2 gate) MQ . The number of stages in the shift register SRI corresponds to the number η of bits in an envelope (according to the X.51 recommendation, η = 10). This comparison results in a bit sequence b _x which is fed to the first input of an AND gate UO. The output of this AND gate I / O is connected to the input of a shift register SRI , which here consists of 40 stages and has taps after 10 and after 20 stages. The output of the shift register SR2 is fed back to the second input of the AND gate {70.

The number of stages S and the number and locations of the taps of the shift register SR2 depend on the number η of the bits of an envelope and on the number k of channels possible in a channel group. The number of steps is S = k ■ η (here S = 40 door η = 10 and k = 4). If the number of possible channels is k — 2 ^m (m = 0,1,2,3 ...), taps are to be provided according to the levels k ■ η, i.e. for η = 10 taps according to the levels 10, 20, 40, 80, ...

The input and the taps of the shift register SRI are fed to an OR gate O \ and, partially inverted, AND circuits Ul, Ul, i / 3. The OR gate 01, a counter Z and an equivalence element Ml are parts of a test circuit PR. The output of the OR gate Ol is connected to the first input of the antivalence element Ml , the output of which is fed to the reset input R of the counter Z. The output of the 10-stage (n = 10) counter Z is connected to the second, inverted input of the antivalence element Ml and to one input each of the AND gates i / l, Ul and i / 3. A "1" is present at this output when the counter Z has reached its maximum level.

At the beginning of the synchronization search and determination of the number of channels, all stages of the shift register SRI are set to "1" (the circuit for this is not shown). As soon as the received bit sequence a _{x has been} received with sufficient length to avoid a simulated synchronization pattern, the shift register SRI only contains a single "ONE", 2 "ONE" s at an interval of 10 clocks T , depending on whether the received channel group contains four, two or one channel. The test circuit PR thus recognizes the point in time when a synchronization bit occurs in the incoming data stream a _x , with which the beginning and end of an envelope can be determined, and at this point in time outputs the data from AND gates i / 1, U1, i / 3 and inverters (some input signals of the AND gates are inverted) existing output logic L free.

The AND gates UX, Ul and i / 3 have the outputs Al, Al and A4. If the synchronization bit sequence in the incoming multiplex signal a _x changes polarity at the input, ie if different values are present at the input of the antivalence element MQ , the value "1" occurs at the output Al (Al = 0, A4 = 0) when the channel group, ie the incoming multiplex signal a “contains only one channel (with, for example, 12 kbit / s). This polarity change of the synchronization bit occurs in this case with every envelope, since the synchronization bit sequence is 1010 ... The frame length is one envelope. The value »1« occurs when the polarity is changed at the output Al (Al = 0 and / 44 = 0) if the channel group contains 2 channels (e.g. with 6 kbit / s each). Then a polarity change occurs after every second envelope, since the synchronization bit sequence is 11001100. . . is, ie the frame length is 2 envelope. If the incoming channel group contains 4 channels (e.g. with 3 kbit / s each), the value »1« occurs when the polarity is changed at output A4 (Al = 0, Al = 0). The synchronization bit sequence in this case is 1111000011110000 ..., ie the frame length is 4 envelopes.

With this relatively simple circuit arrangement it is when using the invention Method thus possible to recognize and to recognize both the frame synchronization on the receiving side check and at the same time, in a simple manner, the number of channels present in the multiplex signal to recognize.

If more than 4 channels can occur in a multiplex signal, the number of AND gates only needs to be increased together with the expansion of the shift register SRI (see above) and the output logic needs to be expanded accordingly. With k = 2 '"(m = 0,1,2,3 ...) channels the number of AND gates is I + m.

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Claims (1)

Patent claims: 1. Method for the transmission of data signals in channel groups using the time division multiplex method, wherein a) a channel group is composed of k channels in a homogeneous time division multiplex, b) each channel has the same envelope structure with at least one permanently assigned synchronization bit (A) , c) envelopes the channels in the channel group are classified d) synchronization bits (A) of the interleaved channels contain the frame synchronization information, that the output of the OR gate (01) is connected to the first input of the antivalence element (Ml), that the output of the counter (Z) is fed back to the second, inverting input of the second antivalence element (Ml) and at the same time to the output logic (L) is performed and that the output of the OR gate (01) is connected to the reset input (R) of the counter (Z).