EP0334193B1 - Method and device for continuously adjusting the phase of a binary data signal at a clock - Google Patents

Method and device for continuously adjusting the phase of a binary data signal at a clock Download PDF

Info

Publication number
EP0334193B1
EP0334193B1 EP89104630A EP89104630A EP0334193B1 EP 0334193 B1 EP0334193 B1 EP 0334193B1 EP 89104630 A EP89104630 A EP 89104630A EP 89104630 A EP89104630 A EP 89104630A EP 0334193 B1 EP0334193 B1 EP 0334193B1
Authority
EP
European Patent Office
Prior art keywords
input
data signal
auxiliary
output
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP89104630A
Other languages
German (de)
French (fr)
Other versions
EP0334193A1 (en
Inventor
Manfred Dipl.-Ing. Kollmeier (Fh)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to AT89104630T priority Critical patent/ATE76706T1/en
Publication of EP0334193A1 publication Critical patent/EP0334193A1/en
Application granted granted Critical
Publication of EP0334193B1 publication Critical patent/EP0334193B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop

Definitions

  • the invention relates to a method for continuously adapting the phase of a first binary data signal to that of a clock whose frequency corresponds to the bit rate of this first data signal.
  • the transmission of binary data signals results in different phase positions compared to the central clock due to their different transit times. So while there is still a fixed phase relationship at the sending location, this is arbitrary at the receiving location.
  • the data signal may have undergone distortion there and may have jitter.
  • phase shift of a data signal with respect to its clock is within certain ranges, it can be recovered in phase by simply sampling it with its clock.
  • phase shift with respect to the clock for all data signals either defined line lengths must be available or the transit time must be adapted by individually interposing delay elements in the signal paths. The limits of this method result from the pulse width distortions of the data signal and the size of the expected jitter and from fluctuations in the transit time due to external influences.
  • An arrangement for synchronizing the phase of a local clock signal with an input signal is known from German published patent application DE 31 02 447 A1.
  • This arrangement contains an oscillator with a downstream delay line, from the taps of which auxiliary clocks are extracted which have the same frequency and form a sequence with the same phase spacing.
  • a coincidence detection circuit can use switches to select the auxiliary clock whose rising edge lies in the middle of the bit of the input signal to be detected.
  • the object of the invention is to provide a method with which the incoming data signal can be continuously adapted in phase to the central clock. This method is said to be feasible with a fully integrated arrangement.
  • Four small circles, which represent auxiliary data signals HD1 to HD4 are arranged on a large circle at a phase distance of 90 °. After a point in time at which they all had a logic state "L” (low), the auxiliary data signal HD2 first went into the logic state "H” (high). It is therefore referred to as the auxiliary data signal HD x . This and the phase-preceding auxiliary data signal HD x-1 or HD1 must not be used as a new second data signal. The hatched small circles show them as parts of an excluded area.
  • the auxiliary data signal HD3 now becomes the new second data signal D2b1.
  • the auxiliary data signal HD1 was the second data signal D2a2
  • the auxiliary data signal HD4 is now selected as the new second data signal D2b2. Accordingly, there is a transition to the next neighboring auxiliary data signal in terms of phase. If, on the other hand, one of the auxiliary data signals HD3 or HD4 was the second data signal, no change is necessary.
  • the auxiliary data signal HD x and thus the two hatched circles can be located at other locations in the large circle.
  • FIG. 2 shows a pulse schedule for the model according to FIG. 1.
  • the data signal D1 is at the top and the four auxiliary clocks HT1 to HT4 can be seen below. If the data signal D1 is clocked with the latter, the auxiliary data signals HD1 to HD4 shown below result. If the data signal D1 is undistorted, the solid lines apply. Two maximum distortion cases x and y are shown in dashed lines, which have an influence on the auxiliary data signals HD1 and HD2. These must therefore not be used as new data signals D2.
  • the incoming data signal D1 has a maximum value for the admissible distortion of the bit length of 3/4 to 5/4 of the nominal length and a value of 0.25 for the jitter UIpp (Unit Interval peak-peak) in the worst case.
  • T when using the auxiliary data signals HD2 or HD3, distortions of a pulse duration of up to T ⁇ T / 4 are eliminated in this case.
  • T ⁇ mT / n applies, where m is the number of bits-n-th maximum distortion and n is the number of auxiliary data signals.
  • the position here serves the positive edge of the data signal D1 in relation to the auxiliary clocks HT1 to HT4 as a selection criterion for the switchover.
  • the decisive factor is from which auxiliary clock HT1 to HT4 the change of state of the data signal D1 was first recognized during the clocking.
  • This auxiliary clock HT1 to HT4 supplies the auxiliary data signal HD x .
  • Under the pulses of the auxiliary clocks HT1 to HT4 five state changes A to E of the data signal D1 are shown after times at which all auxiliary data signals HD1 to HD4 had a logic state "L".
  • auxiliary clocks HT1 to HT4 the status change recognized first and supplies the auxiliary data signal HDx.
  • auxiliary clocks HT2, HT3, HT2, HT1 and HT2 for the cases shown in succession.
  • either the next data phase or the next but one auxiliary data signal is then used as the new second data signal D2, as has already been described with reference to FIG. 1. Which of these two is selected depends on the previous history, ie on whether the auxiliary data signal HD x appears earlier or later in the phase compared to the last adaptation interval.
  • FIG. 3 shows the areas in which the data signal D1 may move without the auxiliary data signals being reselected as data signal D2.
  • cases A, C and E no changeover is required; different in the cases B and D and in each case in a different direction.
  • the shift in the range means that if the data signal D1 jitters by one phase of the auxiliary clock, no further switchovers are triggered.
  • a jitter of the data signal D1 may therefore in the worst case, i.e. if the edge of this data signal D1 oscillates exactly between two auxiliary clock phases, only 0.25 UIpp and in the best case, i.e. if the edge oscillates exactly around an auxiliary clock phase position, be 0.5 UIpp without a switchover taking place.
  • auxiliary data signals HD4 to HD7 and HD x-2 to HD x + 1 now belong to the excluded area. If the last second data signal D2 was in the excluded area, such as D2a3, D2a4, D2a5 or D2a6, then the auxiliary data signal HD3 or HD8 becomes the new second data signal D2b3, D2b4, D2b5 or D2b6.
  • the clocking part I is supplied with the binary data signal D1 via an input 1 and auxiliary clocks HT1 to HTn via inputs 2, 3 and 5.
  • the frequency of the latter is identical to one another and corresponds to the bit rate of the data signal D1.
  • a phase can be found among them which enables error-free sampling of the data signal D1.
  • clock cycle part I data signal D1 is sampled by auxiliary clock signals HT1 to HTn to form auxiliary data signals HD1 to HDn.
  • the control logic II selects a suitable auxiliary data signal via the changeover switch III and feeds it to the adaptation part IV as a second data signal D2. In this the adaptation of the selected second data signal D2 to the phase of the clock T takes place.
  • This is one of the auxiliary clocks HT1 to HTn, for example.
  • FIG. 6 shows an embodiment of the arrangement according to FIG. 5, which contains a clocking part I, a control logic II, a changeover switch III and an adaptation part IV, and FIG. 7 shows an associated pulse schedule.
  • the scanning part I contains four D flip-flops 7 to 10.
  • the control logic II comprises four NAND gates 11 to 14 and two RS flip-flops 15 and 16. The latter consist of NAND gates 17 and 18 or 19 and 20.
  • the switch III consists of NAND gates 21 to 26.
  • the adaptation part IV contains D flip-flops 27, 28 and 30 and a NAND gate 29.
  • the binary data signal D1 at the data signal input 1 is supplied to all D inputs of the D flip-flops 7 to 10.
  • the clock input of the D flip-flop 7 is connected to the auxiliary clock input 2 for the auxiliary clock HT1
  • the clock input of the D flip-flop 8 is connected to the auxiliary clock input 3 for the auxiliary clock HT2
  • the clock input of the D flip-flop 9 is connected to the auxiliary clock input 4 wired for the auxiliary clock HT3
  • the clock input of the D flip-flop 10 is connected to the auxiliary clock input 5 for the auxiliary clock HT4.
  • the reset inputs of all D flip-flops 7 to 10 are connected to the reset signal input 6 for the reset signal R.
  • the data signal D1 is clocked with positive edges of the auxiliary clocks HT1 to HT4.
  • Auxiliary data signals HD1 to HD4 arise at the Q outputs of the D flip-flops 7 to 10 and are supplied to the changeover switch III.
  • the control logic II evaluates the position of the positive edge of the data signal D1 with respect to the four auxiliary clocks HT1 to HT4. With the help of the NAND gate 11 is on S -Input of the RS flip-flop 15 generates a negative pulse when the Q output of the D flip-flop 8 changes from the logic state "L” to the logic state "H” before the Q outputs of the D flip-flops 7, 9 and 10 and thus the positive edge of the data signal D1 lies between the first and second auxiliary clock phases. The same applies to the output signals of the NAND gates 12, 13 and 14.
  • the output signals of the NAND gates 11 to 14 are on the R - and S -Inputs of the RS flip-flops 15 and 16 led. In this case, they are always driven with the phase-after-next output signal of the NAND gates 11 to 14.
  • the output signals of the RS flip-flops 15 and 16 decide which of the auxiliary data signals HD1 to HD4 is selected by the changeover switch III.
  • the auxiliary clock HT1 serves as clock T.
  • the selectable auxiliary data signals HD1 to HD4 are divided into two groups and again sampled with the D flip-flops 27 and 28.
  • the NAND gate 29 there is then a combination of both signals obtained from the clocking to form the data signal D2 and in the D flip-flop 30 an adaptation to the clock T.
  • the adapted and equalized data signal D3 can be seen at the output 31. With the reset signal R, a defined initial state can be forced.
  • FIG. 7 shows the pulse schedule for the arrangement according to FIG. 6.
  • the four auxiliary clock cycles HT1 to HT4 are shown above.
  • the auxiliary clock HT1 serves as clock T.
  • the data signal D1 is shown with distorted pulses. In cases F, H and L there is a nominal delay between the bits. In case G the runtime is longer by T / 4, in cases I and K by T / 4 shorter.
  • the double arrows indicate the assignment of the area according to FIG. 3.
  • the auxiliary data signals HD1 to HD4 are then shown downwards. Then follow pulses from measuring points which are marked with lower case letters in FIG. 6.
  • the reference symbols HD1, HD2 and HD3 along the pulses show which auxiliary data signal is selected in each case.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

In digital data transmission systems with a central clock, incoming binary data signals need to be adjusted to this clock. The new method is intended to enable this adjustment in a fully integrable arrangement. In a clocking element (I) the first data signal (D1) on the input side is pulsed in parallel from a plurality of auxiliary clocks (HT1- HTn) to form a corresponding number of auxiliary data signals (HD1- HDn). The auxiliary clocks have the same frequency as the central clock and have equal phase spaces between one another. One of the auxiliary data signals (HD1 to HD4) is selected by a changeover switch (III) and fed as a second data signal (D2) to an adjustment element (IV) in which it is pulsed by a clock (T) to form a third data signal (D3). A control logic (II) controls the changeover switch (III) so that an auxiliary data signal (HD1 to HD4) is selected as a second data signal (D2) in which, as a result of its phase angle, pulse duration distortions and jitter of the first data signal (D1) have no effect. The new method is suitable for synchronous digital signal processing in cross-connect and cross-connect multiplexer systems. <IMAGE>

Description

Die Erfindung bezieht sich auf ein Verfahren zur fortlaufenden Anpassung der Phase eines ersten binären Datensignals an die eines Taktes, dessen Frequenz der Bitrate dieses ersten Datensignals entspricht.The invention relates to a method for continuously adapting the phase of a first binary data signal to that of a clock whose frequency corresponds to the bit rate of this first data signal.

Innerhalb von Systemen mit einem zentralen Takt ergeben sich bei der Übertragung von binären Datensignalen verschiedene Phasenlagen gegenüber dem zentralen Takt durch deren unterschiedliche Laufzeiten. Während also am Sendeort noch eine feste Phasenbeziehung besteht, ist diese am Empfangsort beliebig. Zusätzlich kann das Datensignal dort eine Verzerrung erfahren haben sowie mit einem Jitter behaftet sein.Within systems with a central clock, the transmission of binary data signals results in different phase positions compared to the central clock due to their different transit times. So while there is still a fixed phase relationship at the sending location, this is arbitrary at the receiving location. In addition, the data signal may have undergone distortion there and may have jitter.

Liegt die Phasenverschiebung eines Datensignals zu seinem Takt innerhalb gewisser Bereiche, so kann dieses durch einfaches Abtasten mit seinem Takt phasenrichtig wiedergewonnen werden. Um für alle Datensignale eine geeignete Phasenverschiebung gegenüber dem Takt zu erreichen, müssen entweder definierte Leitungslängen vorhanden sein oder es muß durch individuelles Zwischenschalten von Laufzeitgliedern in den Signalwegen eine Anpassung der Laufzeit durchgeführt werden. Die Grenzen dieses Verfahrens ergeben sich aus den Impulsbreitenverzerrungen des Datensignals sowie der Größe des zu erwartenden Jitters und aus Schwankungen der Laufzeit durch äußere Einflüsse.If the phase shift of a data signal with respect to its clock is within certain ranges, it can be recovered in phase by simply sampling it with its clock. In order to achieve a suitable phase shift with respect to the clock for all data signals, either defined line lengths must be available or the transit time must be adapted by individually interposing delay elements in the signal paths. The limits of this method result from the pulse width distortions of the data signal and the size of the expected jitter and from fluctuations in the transit time due to external influences.

Aus der deutschen Offenlegungsschrift DE 31 02 447 A1 ist eine Anordnung zum Synchronisieren der Phase eines örtlichen Taktsignals mit einem Eingangssignal bekannt. Diese Anordnung enthält einen Oszillator mit nachgeschalteter Verzögerungsleitung, aus deren Abgriffen Hilfstakte entnommen werden, die dieselbe Frequenz aufweisen und eine Folge mit gleichen Phasenabständen bilden. Über Schalter kann eine Koinzidenzdetektionsschaltung den Hilfstakt auswählen, dessen steigende Flanke mitten in dem zu detektierenden Bit des Eingangssignals liegt.An arrangement for synchronizing the phase of a local clock signal with an input signal is known from German published patent application DE 31 02 447 A1. This arrangement contains an oscillator with a downstream delay line, from the taps of which auxiliary clocks are extracted which have the same frequency and form a sequence with the same phase spacing. A coincidence detection circuit can use switches to select the auxiliary clock whose rising edge lies in the middle of the bit of the input signal to be detected.

Aufgabe der Erfindung ist es, ein Verfahren anzugeben, mit dem das ankommende Datensignal fortlaufend in der Phase an den zentralen Takt angepaßt werden kann. Dieses Verfahren soll weiter mit einer voll integrierten Anordnung durchführbar sein.The object of the invention is to provide a method with which the incoming data signal can be continuously adapted in phase to the central clock. This method is said to be feasible with a fully integrated arrangement.

Diese Aufgabe wird erfindungsgemäß mit den Merkmalen des Patentanspruchs 1 realisiert.This object is achieved with the features of claim 1.

Eine Anordnung zur Durchführung dieses Verfahrens enthält die Merkmale der Patentansprüche 2 bis 6.An arrangement for carrying out this method contains the features of claims 2 to 6.

Anhand von Ausführungsbeispielen wird die Erfindung nachstehend näher erläutert.

  • Fig. 1 zeigt ein erstes Modell zur Erläuterung des Verfahrens,
  • Fig. 2 zeigt einen ersten Pulsplan zum ersten Modell,
  • Fig. 3 zeigt einen zweiten Pulsplan zum ersten Modell,
  • Fig. 4 zeigt ein zweites Modell zur Erläuterung des Verfahrens,
  • Fig. 5 zeigt ein Blockschaltbild einer Anordnung zur Durchführung des Verfahrens,
  • Fig. 6 zeigt ein Anordnungsbeispiel detailliert und
  • Fig. 7 zeigt einen Pulsplan zur Erläuterung der Anordnung nach Fig. 6.
The invention is explained in more detail below on the basis of exemplary embodiments.
  • 1 shows a first model to explain the method,
  • 2 shows a first pulse plan for the first model,
  • 3 shows a second pulse schedule for the first model,
  • 4 shows a second model to explain the method,
  • 5 shows a block diagram of an arrangement for carrying out the method,
  • Fig. 6 shows an arrangement example in detail and
  • FIG. 7 shows a pulse plan to explain the arrangement according to FIG. 6.

Fig. 1 zeigt ein Modell zur Erläuterung des erfindungsgemäßen Verfahrens für den Fall m=1 und n=4. Auf einem großen Kreis sind im Phasenabstand von 90° vier kleine Kreise angeordnet, die Hilfsdatensignale HD1 bis HD4 darstellen. Nach einem Zeitpunkt, an dem diese alle einen logischen Zustand "L" (niedrig) aufwiesen, ging zuerst das Hilfsdatensignal HD2 in den logischen Zustand "H" (hoch) über. Es ist deswegen als Hilfsdatensignal HDx bezeichnet. Dieses und das phasenmäßig vorangehende Hilfsdatensignal HDx-1 bzw. HD1 dürfen nicht als neues zweites Datensignal verwendet werden. Die schraffierten kleinen Kreise weisen diese als Teile eines ausgeschlossenen Bereichs aus. Im Falle, daß das Hilfsdatensignal HD2 zuletzt das zweite Datensignal D2a1 war, wird jetzt das Hilfsdatensignal HD3 das neue zweite Datensignal D2b1. War dagegen das Hilfsdatensignal HD1 das zweite Datensignal D2a2, dann wird jetzt das Hilfsdatensignal HD4 als neues zweites Datensignal D2b2 ausgewählt. Es erfolgt demnach jeweils ein Übergang auf das phasenmäßig nächstbenachbarte Hilfsdatensignal. War dagegen zuletzt eines der Hilfsdatensignale HD3 oder HD4 das zweite Datensignal, dann ist kein Wechsel erforderlich.1 shows a model for explaining the method according to the invention for the case m = 1 and n = 4. Four small circles, which represent auxiliary data signals HD1 to HD4, are arranged on a large circle at a phase distance of 90 °. After a point in time at which they all had a logic state "L" (low), the auxiliary data signal HD2 first went into the logic state "H" (high). It is therefore referred to as the auxiliary data signal HD x . This and the phase-preceding auxiliary data signal HD x-1 or HD1 must not be used as a new second data signal. The hatched small circles show them as parts of an excluded area. In the event that the auxiliary data signal HD2 was last the second data signal D2a1, the auxiliary data signal HD3 now becomes the new second data signal D2b1. In contrast, if the auxiliary data signal HD1 was the second data signal D2a2, then the auxiliary data signal HD4 is now selected as the new second data signal D2b2. Accordingly, there is a transition to the next neighboring auxiliary data signal in terms of phase. If, on the other hand, one of the auxiliary data signals HD3 or HD4 was the second data signal, no change is necessary.

In jedem neuen Anpassungsintervall können das Hilfsdatensignal HDx und damit die zwei schraffierten Kreise an anderen Plätzen des großen Kreises liegen.In each new adaptation interval, the auxiliary data signal HD x and thus the two hatched circles can be located at other locations in the large circle.

Fig. 2 zeigt einen Pulsplan zu dem Modell nach Fig. 1. Oben ist das Datensignal D1 und darunter sind die vier Hilfstakte HT1 bis HT4 zu sehen. Wird das Datensignal D1 mit letzteren abgetaktet, so ergeben sich die unten dargestellten Hilfsdatensignale HD1 bis HD4. Ist das Datensignal D1 unverzerrt, so gelten die ausgezogenen Linien. Gestrichelt sind zwei maximale Verzerrungsfälle x und y dargestellt, die Einfluß auf die Hilfsdatensignale HD1 und HD2 haben. Diese dürfen daher nicht als neue Datensignale D2 eingesetzt werden.FIG. 2 shows a pulse schedule for the model according to FIG. 1. The data signal D1 is at the top and the four auxiliary clocks HT1 to HT4 can be seen below. If the data signal D1 is clocked with the latter, the auxiliary data signals HD1 to HD4 shown below result. If the data signal D1 is undistorted, the solid lines apply. Two maximum distortion cases x and y are shown in dashed lines, which have an influence on the auxiliary data signals HD1 and HD2. These must therefore not be used as new data signals D2.

Bei Verwendung von vier Hilfstakten HT1 bis HT4 mit Phasendifferenzen von je 90° ergeben sich für das ankommende Datensignal D1 ein maximaler Wert für die zulässige Verzerrung der Bitlänge von 3/4 bis 5/4 der Nominallänge und für den Jitter einen Wert von 0,25 UIpp (Unit Interval peak-peak) im ungünstigsten Fall.When using four auxiliary clocks HT1 to HT4 with phase differences of 90 ° each, the incoming data signal D1 has a maximum value for the admissible distortion of the bit length of 3/4 to 5/4 of the nominal length and a value of 0.25 for the jitter UIpp (Unit Interval peak-peak) in the worst case.

Bei einer Taktperiodendauer T werden bei einer Verwendung der Hilfsdatensignale HD2 oder HD3 demnach in diesem Fall Verzerrungen einer Impulsdauer bis zu T ± T/4 eliminiert. Allgemein gilt T ± mT/n, wobei m die Anzahl der Bit-n-tel maximaler Verzerrung und n die Anzahl der Hilfsdatensignale bedeuten.With a clock period T when using the auxiliary data signals HD2 or HD3, distortions of a pulse duration of up to T ± T / 4 are eliminated in this case. In general, T ± mT / n applies, where m is the number of bits-n-th maximum distortion and n is the number of auxiliary data signals.

Wie anhand der Fig. 3 näher erläutert wird, dient die Position hier der positiven Flanke des Datensignals D1 in Bezug auf die Hilfstakte HT1 bis HT4 als Auswahlkriterium für die Umschaltung. Ausschlaggebend ist, von welchem Hilfstakt HT1 bis HT4 der Zustandswechsel des Datensignals D1 bei der Abtaktung zuerst erkannt worden ist. Dieser Hilfstakt HT1 bis HT4 liefert das Hilfsdatensignal HDx. Unter den Pulsen der Hilfstakte HT1 bis HT4 sind fünf Zustandswechsel A bis E des Datensignals D1 nach Zeitpunkten, bei denen alle Hilfsdatensignale HD1 bis HD4 einen logischen Zustand "L" aufwiesen, gezeigt. Die von den Zustandswechseln aus nach oben gerichteten Pfeile zeigen an, welcher der Hilfstakte HT1 bis HT4 den Zustandswechsel zuerst erkannt hat und das Hilfsdatensignal HDx liefert. Dies sind für die nacheinander gezeigten Fälle die Hilfstakte HT2, HT3, HT2, HT1 und HT2. Mit Hilfe dieser Informationen wird anschließend entweder das phasenmäßig nächste oder übernächste Hilfsdatensignal als neues zweites Datensignal D2 verwendet, wie es bereits anhand der Fig. 1 beschrieben wurde. Welches dieser beiden ausgewählt wird, hängt von der Vorgeschichte ab, d.h. davon, ob das Hilfsdatensignal HDx gegenüber dem letzten Anpassungsintervall in der Phase früher oder später erscheint. Dies ist gleichbedeutend mit einer Neuauswahl der Hilfsdatensignale als neues Datensignal D2 aufgrund einer Vergrößerung bzw. Verkleinerung der Datensignallaufzeit des Datensignals D1. Umgeschaltet wird nicht, wenn bereits ein Hilfsdatensignal HD1 bis HD4 außerhalb des ausgeschlossenen Bereichs als Datensignal D2 fungiert.As will be explained in more detail with reference to FIG. 3, the position here serves the positive edge of the data signal D1 in relation to the auxiliary clocks HT1 to HT4 as a selection criterion for the switchover. The decisive factor is from which auxiliary clock HT1 to HT4 the change of state of the data signal D1 was first recognized during the clocking. This auxiliary clock HT1 to HT4 supplies the auxiliary data signal HD x . Under the pulses of the auxiliary clocks HT1 to HT4, five state changes A to E of the data signal D1 are shown after times at which all auxiliary data signals HD1 to HD4 had a logic state "L". The arrows pointing upwards from the status changes indicate which of the auxiliary clocks HT1 to HT4 the status change recognized first and supplies the auxiliary data signal HDx. These are the auxiliary clocks HT2, HT3, HT2, HT1 and HT2 for the cases shown in succession. With the help of this information, either the next data phase or the next but one auxiliary data signal is then used as the new second data signal D2, as has already been described with reference to FIG. 1. Which of these two is selected depends on the previous history, ie on whether the auxiliary data signal HD x appears earlier or later in the phase compared to the last adaptation interval. This is equivalent to a new selection of the auxiliary data signals as the new data signal D2 due to an increase or decrease in the data signal transit time of the data signal D1. Switching does not take place if an auxiliary data signal HD1 to HD4 already functions as a data signal D2 outside the excluded area.

In Fig. 3 sind unten die Bereiche eingezeichnet, in denen sich das Datensignal D1 bewegen darf, ohne das eine Neuauswahl der Hilfsdatensignale als Datensignal D2 erfolgt. In den Fällen A, C und E ist keine Umschaltung erforderlich; anders in den Fällen B und D und zwar jeweils in anderer Richtung. Die Verschiebung des Bereichs führt dazu, daß bei einem Jitter des Datensignals D1 um eine Phasenlage des Hilfstakts keine weiteren Umschaltungen ausgelöst werden. Ein Jitter des Datensignals D1 darf demnach im ungünstigsten Fall, d.h. wenn die Flanke dieses Datensignal D1 genau zwischen zwei Hilfstakt-Phasenlagen pendelt, nur 0,25 UIpp und im günstigsten Fall, d.h. wenn die Flanke genau um eine Hilfstakt-Phasenlage pendelt, 0,5 UIpp betragen ohne daß eine Umschaltung stattfindet.3 shows the areas in which the data signal D1 may move without the auxiliary data signals being reselected as data signal D2. In cases A, C and E no changeover is required; different in the cases B and D and in each case in a different direction. The shift in the range means that if the data signal D1 jitters by one phase of the auxiliary clock, no further switchovers are triggered. A jitter of the data signal D1 may therefore in the worst case, i.e. if the edge of this data signal D1 oscillates exactly between two auxiliary clock phases, only 0.25 UIpp and in the best case, i.e. if the edge oscillates exactly around an auxiliary clock phase position, be 0.5 UIpp without a switchover taking place.

Fig. 4 zeigt einen Fall mit m=2 und n=8. Zum ausgeschlossenen Bereich gehören jetzt die Hilfsdatensignale HD4 bis HD7 bzw. HDx-2 bis HD x+1. War das letzte zweite Datensignal D2 ein im ausgeschlossenen Bereich liegendes wie D2a3, D2a4, D2a5 oder D2a6, dann wird das Hilfsdatensignal HD3 oder HD8 das neue zweite Datensignal D2b3, D2b4, D2b5 oder D2b6.4 shows a case with m = 2 and n = 8. The auxiliary data signals HD4 to HD7 and HD x-2 to HD x + 1 now belong to the excluded area. If the last second data signal D2 was in the excluded area, such as D2a3, D2a4, D2a5 or D2a6, then the auxiliary data signal HD3 or HD8 becomes the new second data signal D2b3, D2b4, D2b5 or D2b6.

Fig. 5 zeigt eine Anordnung zur Durchführung des erfindungsgemäßen Verfahrens. Sie enthält einen Abtaktteil I, eine Steuerlogik II, einen Umschalter III und einen Anpassungsteil IV. Dem Abtaktteil I werden über einen Eingang 1 das binäre Datensignal D1 und über Eingänge 2, 3 und 5 Hilfstakte HT1 bis HTn zugeführt. Die Frequenz letzterer ist untereinander gleich und entspricht der Bitrate des Datensignals D1. Es läßt sich unter ihnen eine Phase finden, die eine fehlerfreie Abtastung des Datensignals D1 ermöglicht.5 shows an arrangement for carrying out the method according to the invention. It contains a clocking part I, a control logic II, a changeover switch III and an adaptation part IV. The clocking part I is supplied with the binary data signal D1 via an input 1 and auxiliary clocks HT1 to HTn via inputs 2, 3 and 5. The frequency of the latter is identical to one another and corresponds to the bit rate of the data signal D1. A phase can be found among them which enables error-free sampling of the data signal D1.

Im Abtaktteil I wird das Datensignal D1 zur Bildung von Hilfsdatensignalen HD1 bis HDn von jedem Hilfstakt HTl bis HTn abgetastet. Die Steuerlogik II wählt über den Umschalter III ein geeignetes Hilfsdatensignal aus und führt es dem Anpassungsteil IV als zweites Datensignal D2 zu. In diesem findet die Anpassung des ausgewählten zweiten Datensignals D2 an die Phase des Taktes T statt. Dieser ist beispielsweise einer der Hilfstakte HT1 bis HTn.In clock cycle part I, data signal D1 is sampled by auxiliary clock signals HT1 to HTn to form auxiliary data signals HD1 to HDn. The control logic II selects a suitable auxiliary data signal via the changeover switch III and feeds it to the adaptation part IV as a second data signal D2. In this the adaptation of the selected second data signal D2 to the phase of the clock T takes place. This is one of the auxiliary clocks HT1 to HTn, for example.

Fig. 6 zeigt ein Ausführungsbeispiel der Anordnung nach Fig. 5, die einen Abtaktteil I, eine Steuerlogik II, einen Umschalter III und einen Anpassungsteil IV enthält, und Fig. 7 einen zugehörigen Pulsplan.FIG. 6 shows an embodiment of the arrangement according to FIG. 5, which contains a clocking part I, a control logic II, a changeover switch III and an adaptation part IV, and FIG. 7 shows an associated pulse schedule.

Der Abtastteil I enthält vier D-Flipflops 7 bis 10. Die Steuerlogik II umfaßt vier NAND-Gatter 11 bis 14 und zwei RS-Flipflops 15 und 16. Letztere bestehen aus NAND-Gattern 17 und 18 bzw. 19 und 20. Der Umschalter III besteht aus NAND-Gatter 21 bis 26. Der Anpassungsteil IV enthält D-Flipflops 27, 28 und 30 sowie ein NAND-Gatter 29.The scanning part I contains four D flip-flops 7 to 10. The control logic II comprises four NAND gates 11 to 14 and two RS flip-flops 15 and 16. The latter consist of NAND gates 17 and 18 or 19 and 20. The switch III consists of NAND gates 21 to 26. The adaptation part IV contains D flip-flops 27, 28 and 30 and a NAND gate 29.

Das binäre Datensignal D1 am Datensignaleingang 1 wird allen D-Eingängen der D-Flipflops 7 bis 10 zugeführt. Der Takteingang des D-Flipflops 7 wird mit dem Hilfstakteingang 2 für den Hilfstakt HT1 verbunden, der Takteingang des D-Flipflops 8 wird an den Hilfstakteingang 3 für den Hilfstakt HT2 angeschlossen, der Takteingang des D-Flipflops 9 ist mit dem Hilfstakteingang 4 für den Hilfstakt HT3 verdrahtet und der Takteingang des D-Flipflops 10 ist mit den Hilfstakteingang 5 für den Hilfstakt HT4 verbunden. Die Rücksetzeingänge aller D-Flipflops 7 bis 10 sind an den Rücksetzsignal-Eingang 6 für das Rücksetzsignal R angeschlossen. In den D-Flipflops 7 bis 10 wird das Datensignal D1 mit positiven Flanken der Hilfstakte HTl bis HT4 abgetaktet. An den Q-Ausgängen der D-Flipflops 7 bis 10 entstehen dabei Hilfsdatensignale HD1 bis HD4, die dem Umschalter III zugeführt werden.The binary data signal D1 at the data signal input 1 is supplied to all D inputs of the D flip-flops 7 to 10. The clock input of the D flip-flop 7 is connected to the auxiliary clock input 2 for the auxiliary clock HT1, the clock input of the D flip-flop 8 is connected to the auxiliary clock input 3 for the auxiliary clock HT2, the clock input of the D flip-flop 9 is connected to the auxiliary clock input 4 wired for the auxiliary clock HT3 and the clock input of the D flip-flop 10 is connected to the auxiliary clock input 5 for the auxiliary clock HT4. The reset inputs of all D flip-flops 7 to 10 are connected to the reset signal input 6 for the reset signal R. In the D flip-flops 7 to 10, the data signal D1 is clocked with positive edges of the auxiliary clocks HT1 to HT4. Auxiliary data signals HD1 to HD4 arise at the Q outputs of the D flip-flops 7 to 10 and are supplied to the changeover switch III.

Die Steuerlogik II wertet die Position der positiven Flanke des Datensignals D1 gegenüber den vier Hilfstakten HT1 bis HT4 aus. Mit Hilfe des NAND-Gatters 11 wird am S-Eingang des RS-Flipflops 15 ein negativer Impuls erzeugt, wenn der Q-Ausgang des D-Flipflops 8 vor den Q-Ausgängen der D-Flipflops 7, 9 und 10 vom logischen Zustand "L" auf den logischen Zustand "H" wechselt und somit die positive Flanke des Datensignals D1 zwischen der ersten und zweiten Hilfstaktphase liegt. Entsprechendes gilt für die Ausgangssignale der NAND-Gatter 12, 13 und 14. Die Ausgangssignale der NAND-Gatter 11 bis 14 werden auf die R- und S-Eingänge der RS-Flipflops 15 und 16 geführt. Dabei werden diese immer mit dem phasenmäßig übernächsten Ausgangssignal der NAND-Gatter 11 bis 14 angesteuert. Die Ausgangssignale der RS-Flipflops 15 und 16 entscheiden, welches der Hilfsdatensignale HD1 bis HD4 vom Umschalter III ausgewählt wird.The control logic II evaluates the position of the positive edge of the data signal D1 with respect to the four auxiliary clocks HT1 to HT4. With the help of the NAND gate 11 is on S -Input of the RS flip-flop 15 generates a negative pulse when the Q output of the D flip-flop 8 changes from the logic state "L" to the logic state "H" before the Q outputs of the D flip-flops 7, 9 and 10 and thus the positive edge of the data signal D1 lies between the first and second auxiliary clock phases. The same applies to the output signals of the NAND gates 12, 13 and 14. The output signals of the NAND gates 11 to 14 are on the R - and S -Inputs of the RS flip-flops 15 and 16 led. In this case, they are always driven with the phase-after-next output signal of the NAND gates 11 to 14. The output signals of the RS flip-flops 15 and 16 decide which of the auxiliary data signals HD1 to HD4 is selected by the changeover switch III.

Als Takt T dient der Hilfstakt HT1. Um auch bei hohen Taktfrequenzen eine geeignete Phasenbeziehung zu diesem Takt T unabhängig von den Gatterlaufzeiten der Steuerlogik II und des Umschalters III zu erreichen, werden die auswählbaren Hilfsdatensignale HD1 bis HD4 in zwei Gruppen aufgeteilt und nochmals mit den D-Flipflops 27 und 28 abgetastet. Im NAND-Gatter 29 erfolgt anschließend eine Zusammenfassung beider aus der Abtaktung gewonnenen Signale zum Datensignal D2 und im D-Flipflop 30 eine Anpassung an den Takt T. Am Ausgang 31 ist das angepaßte und entzerrte Datensignal D3 zu entnehmen. Mit dem Rücksetzsignal R läßt sich ein definierter Anfangszustand erzwingen.The auxiliary clock HT1 serves as clock T. In order to achieve a suitable phase relationship to this clock T even at high clock frequencies regardless of the gate run times of the control logic II and the changeover switch III, the selectable auxiliary data signals HD1 to HD4 are divided into two groups and again sampled with the D flip-flops 27 and 28. In the NAND gate 29 there is then a combination of both signals obtained from the clocking to form the data signal D2 and in the D flip-flop 30 an adaptation to the clock T. The adapted and equalized data signal D3 can be seen at the output 31. With the reset signal R, a defined initial state can be forced.

Fig. 7 zeigt den Pulsplan zur Anordnung nach Fig. 6. Oben sind die vier Hilfstakte HT1 bis HT4 dargestellt. Der Hilfstakt HT1 dient als Takt T. Darunter ist das Datensignal D1 mit verzerrten Impulsen dargestellt. In den Fällen F, H und L liegt eine nominelle Laufzeit zwischen den Bits vor. Im Fall G ist die Laufzeit um T/4 größer, in den Fällen I und K um T/4 kleiner. Die Doppelpfeile zeigen die Zuordnung des Bereichs gemäß Fig. 3 an. Anschließend nach unten sind die Hilfsdatensignale HD1 bis HD4 dargestellt. Weiter folgen Pulse von Meßpunkten, die in Fig. 6 mit Kleinbuchstaben markiert sind. Die Bezugszeichen HD1, HD2 und HD3 längs der Pulse zeigen, welches Hilfsdatensignal jeweils ausgewählt ist.FIG. 7 shows the pulse schedule for the arrangement according to FIG. 6. The four auxiliary clock cycles HT1 to HT4 are shown above. The auxiliary clock HT1 serves as clock T. Below this, the data signal D1 is shown with distorted pulses. In cases F, H and L there is a nominal delay between the bits. In case G the runtime is longer by T / 4, in cases I and K by T / 4 shorter. The double arrows indicate the assignment of the area according to FIG. 3. The auxiliary data signals HD1 to HD4 are then shown downwards. Then follow pulses from measuring points which are marked with lower case letters in FIG. 6. The reference symbols HD1, HD2 and HD3 along the pulses show which auxiliary data signal is selected in each case.

Claims (6)

1. Method for continuously adjusting the phase of a first binary data signal (D1) to that of a clock (T), the frequency of which corresponds to the bit rate of this first data signal (D1),
characterised in that
n auxiliary clocks (HT1 to HTn) are generated which have the same frequency as the clock (T) and form a sequence which has intervals of 360°/n (n > 2),
and in that from the first data signal (D1), n auxiliary data signals (HD1 to HDn), one of which is used as a second data signal (D2a), are derived by sampling with a selected edge of the auxiliary clocks (HT1 to HTn),
and in that each time (t1), at which all auxiliary data signals (HD1 to HDn) have either a logic state "L" or a logic state "H", initiates an adjustment interval, in that it is in each case determined which auxiliary data signal is the second data signal (D2a) at this time (t1), and in that it is in each case determined which auxiliary data signal (HDx) first changes to the logic state "H" after this time (t1),
and in that the last-mentioned auxiliary data signal (HDx), m auxiliary data signals which immediately precede this auxiliary data signal (HDx) in phase and m-1 auxiliary data signals immediately following this auxiliary data signal (HDx) in phase are excluded from the selection of a new second data signal (D2b) (m ≦ n-1 2 )
Figure imgb0002
 ,
and in that an arbitrary non-excluded auxiliary data signal is selected as second data signal (D2b) on initiation of the method,
and in that no new second data signal (D2b) is selected during an adjustment interval if the previous signal (D2a) is one of the non-excluded auxiliary data signals,
and in that during an adjustment interval, a non-excluded auxiliary data signal most closely adjacent to the previous second data signal (D2a) in phase is selected as new second data signal (D2b) if the previous one is one of the excluded auxiliary data signals, and in that the new second data signal (D2b) is adjusted to the clock (T) arbitrarily selected from the auxiliary clocks (HT1 to HT4) for forming a third data signal (D3).
2. Arrangement for continuously adjusting the phase of a first primary data signal (D1) to that of a clock (T) the frequency of which corresponds to the bit rate of this first digital signal (D1), comprising an auxiliary clock generator which generates n auxiliary clocks (HT1 to HTn) which have the same frequency as the clock (T) and form a sequence with phase intervals of 360°/n (n > 2),
characterised in that
a clocking-down section (I) is provided in which auxiliary data signals (HD1 to HD4) are obtained by clocking the first data signal (D1) down with the auxiliary clocks (HT1 to HT4), and in that a change-over switch (III) is provided which switches through one of the auxiliary data signals (HD1 to HD4) as second data signal (D2),
and in that a control logic (II) is provided which selects one of the auxiliary data signals (HD1 to HD4) as second data signal (D2) and appropriately sets the change-over switch (III), and in that an adjustment section (IV) is provided in which from the second data signal (D2), a third phase-adjusted data signal (D3) is obtained by clocking-down with the clock (T).
3. Arrangement according to Claim 2 for m=1 and n=4,
characterised in that
a first (7), second (8), third (9) and fourth (10) D-type flip flop are provided as clocking-down section (I), in which the first data signal (D1) is clocked down by in each case one auxiliary clock (HT1 to HT4) of the same ordinal number,
4. Arrangement according to Claims 2 and 3 for m=1 and n=4,
characterised in that
a first (11), second (12), third (13) and fourth (14) NAND gate, in which in each case a first input is connected to the Q output of the of the D-type flip flop (7) of the same ordinal number, in each case a second inverting input is connected to an auxiliary clock input (2 to 5) of the same ordinal number and in each case a third input is connected to the Q output of the D-type flip flop (7 to 10) of the cyclically next ordinal number, a first RS-type flip flop (15), the S input of which is connected to the output of the first NAND gate (11), the R input of which is connected to the output of the third NAND gate (13) and the reset input of which is connected to a reset signal input (6), and a second RS-type flip flop (16), the S input of which is connected to the output of the second NAND gate (13), the R input of which is connected to the output of the fourth NAND gate (14) and the reset input of which is connected to the resit signal input (6), are provided as control logic (II).
5. Arrangement according to Claims 2 to 4 for m=1 and n=4,
characterised in that
a first gate arrangement consisting of a fifth NAND gate (21), the first input of which is connected to the Q output of the second RS-type flip flop (16), the second input of which is connected to the Q output of the first D-type flip flop (7), and the third input of which is connected to the Q output of the first RS-type flip flop (15), of a sixth NAND gate (22), the first input of which is connected to the Q output of the first RS-type flip flop (15), the second input of which is connected to the Q output of the second D-type flip flop (8), and the third input of which is connected to the Q output of the second RS-type flip flop (16), and of a seventh NAND gate (25), the first input of which is connected to the output of the fifth NAND gate (21) and the second input of which is connected to the output of the sixth NAND gate (22), and a second gate arrangement consisting of an eighth NAND gate (23), the first input of which is connected to the Q output of the second RS-type flip flop (16), the second input of which is connected to the Q output of the third D-type flip flop (9) and the third input of which is connected to the Q output of the first RS-type flip flop (15), of a ninth NAND gate (24), the first input of which is connected to the Q output of the first RS-type flip flop (15), the second input of which is connected to the Q output of the fourth D-type flip flop (10) and the third input of which is connected to the Q output of the second RS-type flip flop (16), and with a tenth NAND gate (26), the first input of which is connected to the output of the eighth NAND gate (23) and the second input of which is connected to the output of the ninth NAND gate (24), are provided as change-over switch (III).
6. Arrangement according to Claims 2 to 5 for m=1 and n=4,
characterised in that
a fifth D-type flip flop (27), the D input of which is connected to the output of the seventh NAND gate (25), the clock input of which is connected to the first auxiliary clock input (2), and the reset input of which is connected to the reset signal input (6), a sixth D-type flip flop (28), the D input of which is connected to the output of the tenth NAND gate (26), the clock input of which is connected to the third auxiliary clock input (4), and the reset input of which is connected to the reset signal input (6), an eleventh NAND gate (29), the first input of which is connected to the Q output of the fifth D-type flip flop (27) and the second input of which is connected to the Q output of the sixth D-type flip flop (28), and a seventh D-type flip flop (30), the D input of which is connected to the output of the eleventh NAND gate (29), the clock input of which is connected to the first auxiliary clock input (2), the reset input of which is connected to the reset signal input (6) and the Q output of which is connected to an output (31) for the third data signal (D3), are provided as adjustment section (IV).
EP89104630A 1988-03-22 1989-03-15 Method and device for continuously adjusting the phase of a binary data signal at a clock Expired - Lifetime EP0334193B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT89104630T ATE76706T1 (en) 1988-03-22 1989-03-15 METHOD AND ARRANGEMENT FOR CONTINUOUSLY ADAPTING THE PHASE OF A BINARY DATA SIGNAL TO A CLOCK.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3809606U 1988-03-22
DE3809606 1988-03-22

Publications (2)

Publication Number Publication Date
EP0334193A1 EP0334193A1 (en) 1989-09-27
EP0334193B1 true EP0334193B1 (en) 1992-05-27

Family

ID=6350374

Family Applications (1)

Application Number Title Priority Date Filing Date
EP89104630A Expired - Lifetime EP0334193B1 (en) 1988-03-22 1989-03-15 Method and device for continuously adjusting the phase of a binary data signal at a clock

Country Status (5)

Country Link
EP (1) EP0334193B1 (en)
AT (1) ATE76706T1 (en)
DE (1) DE58901519D1 (en)
ES (1) ES2031295T3 (en)
GR (1) GR3005402T3 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0369047A1 (en) * 1988-11-15 1990-05-23 Siemens Aktiengesellschaft Arrangement for commuting a clock on a clock with the same frequency but lagging in phase
DE19740255C2 (en) * 1997-09-12 2000-02-10 Siemens Ag Sampling circuit for digital signals with high data rates

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL183214C (en) * 1980-01-31 1988-08-16 Philips Nv Apparatus for synchronizing the phase of a locally generated clock signal with the phase of an input signal.
JPS59225640A (en) * 1983-06-06 1984-12-18 Nitsuko Ltd Clock phase synchronization system

Also Published As

Publication number Publication date
DE58901519D1 (en) 1992-07-02
EP0334193A1 (en) 1989-09-27
ATE76706T1 (en) 1992-06-15
ES2031295T3 (en) 1992-12-01
GR3005402T3 (en) 1993-05-24

Similar Documents

Publication Publication Date Title
DE3604277C2 (en) Device for adjusting the phase position of data signals
DE69734954T2 (en) Method and apparatus for phasing digital time signals, e.g. a clock signal and a data stream
CH623692A5 (en)
EP0345564B1 (en) Method and device for the recuperation of a bit clock from a digital telecommunication signal
DE3442613C2 (en)
DE69733108T2 (en) Synchronous multiplexing delay circuit
EP0363513A1 (en) Method and apparatus for receiving a binary digital signal
DE3131897C2 (en) Control signal multiplexing circuit
EP0334193B1 (en) Method and device for continuously adjusting the phase of a binary data signal at a clock
DE2714219C2 (en)
DE2753999A1 (en) DIGITAL TRANSMISSION SYSTEM WITH TIME DISTRIBUTION
EP0204376B1 (en) Ternary signal scanning device
DE1616356B1 (en) Circuit arrangement for synchronization in a time division multiplex system
EP0400398B1 (en) Method for receiving binary digital signals
EP0339515B1 (en) Method and device for the clock recovery from a data signal by consecutive adjustments of a local clock with a data signal
DE2242639B2 (en) TIME MULTIPLEX TELEGRAPHY SYSTEM FOR NESTING BY CHARACTER
DE69224452T2 (en) Phase shifter
DE4434803C1 (en) Serial bit stream sampling method for high speed data transmission equipment
DE3248566C2 (en) Method and circuit arrangement for the transmission of data signals
DE3835259C2 (en) Circuit arrangement for receiving serial transmitted digital data
DE2517097A1 (en) Time multiplex signal transmission network - has branches to which individual subscriber stations are connected
DE1219066B (en) Transmission method for electrical data
DE2434869A1 (en) DIGITAL DATA MULTIPLEXER IN PLUG TECHNOLOGY
DE10003532C1 (en) Clock generator
DE2430760A1 (en) Coding device with transmitter coder and receiver decoder - has two shift registers, one with five and other with four d-flip-flops

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH DE ES FR GB GR IT LI NL SE

17P Request for examination filed

Effective date: 19891026

17Q First examination report despatched

Effective date: 19910913

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE CH DE ES FR GB GR IT LI NL SE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 19920527

REF Corresponds to:

Ref document number: 76706

Country of ref document: AT

Date of ref document: 19920615

Kind code of ref document: T

REF Corresponds to:

Ref document number: 58901519

Country of ref document: DE

Date of ref document: 19920702

ET Fr: translation filed
ITF It: translation for a ep patent filed
GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)
REG Reference to a national code

Ref country code: ES

Ref legal event code: FG2A

Ref document number: 2031295

Country of ref document: ES

Kind code of ref document: T3

REG Reference to a national code

Ref country code: GR

Ref legal event code: FG4A

Free format text: 3005402

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19930315

Ref country code: AT

Effective date: 19930315

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Effective date: 19930316

Ref country code: ES

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19930316

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Effective date: 19930331

Ref country code: CH

Effective date: 19930331

Ref country code: BE

Effective date: 19930331

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
BERE Be: lapsed

Owner name: SIEMENS A.G.

Effective date: 19930331

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Effective date: 19931001

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19930315

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19931130

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19931201

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

REG Reference to a national code

Ref country code: GR

Ref legal event code: MM2A

Free format text: 3005402

EUG Se: european patent has lapsed

Ref document number: 89104630.2

Effective date: 19931008

REG Reference to a national code

Ref country code: ES

Ref legal event code: FD2A

Effective date: 19990405

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20050315