DE3205026C2 - - Google Patents

Info

Publication number
DE3205026C2
DE3205026C2 DE3205026A DE3205026A DE3205026C2 DE 3205026 C2 DE3205026 C2 DE 3205026C2 DE 3205026 A DE3205026 A DE 3205026A DE 3205026 A DE3205026 A DE 3205026A DE 3205026 C2 DE3205026 C2 DE 3205026C2
Authority
DE
Germany
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3205026A
Other versions
DE3205026A1 (de
Inventor
Satoshi Yokohama Jp Shinozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3205026A1 publication Critical patent/DE3205026A1/de
Application granted granted Critical
Publication of DE3205026C2 publication Critical patent/DE3205026C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Read Only Memory (AREA)
DE19823205026 1981-02-13 1982-02-12 Halbleiterspeicher und verfahren zu dessen herstellung Granted DE3205026A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1992681A JPS57134962A (en) 1981-02-13 1981-02-13 Semiconductor memory and manufacture of the same

Publications (2)

Publication Number Publication Date
DE3205026A1 DE3205026A1 (de) 1982-08-26
DE3205026C2 true DE3205026C2 (de) 1987-04-23

Family

ID=12012824

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19823205026 Granted DE3205026A1 (de) 1981-02-13 1982-02-12 Halbleiterspeicher und verfahren zu dessen herstellung

Country Status (3)

Country Link
US (1) US4453233A (de)
JP (1) JPS57134962A (de)
DE (1) DE3205026A1 (de)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3653005A (en) * 1969-08-25 1972-03-28 North Electric Co Mechanical storage means for repertory dialer
BE794202A (fr) * 1972-01-19 1973-05-16 Intel Corp Liaison fusible pour circuit integre sur substrat semi-conducteur pour memoires
US3835457A (en) * 1972-12-07 1974-09-10 Motorola Inc Dynamic mos ttl compatible
JPS5154789A (de) * 1974-11-09 1976-05-14 Nippon Electric Co
NL176415C (nl) * 1976-07-05 1985-04-01 Hitachi Ltd Halfgeleidergeheugeninrichting omvattende een matrix van halfgeleidergeheugencellen, die bestaan uit een veldeffekttransistor en een opslagcapaciteit.

Also Published As

Publication number Publication date
US4453233A (en) 1984-06-05
JPS57134962A (en) 1982-08-20
DE3205026A1 (de) 1982-08-26

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8128 New person/name/address of the agent

Representative=s name: HENKEL, G., DR.PHIL. FEILER, L., DR.RER.NAT. HAENZ

8127 New person/name/address of the applicant

Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee