DE3175640D1 - A semiconductor device with a v-groove insulating isolation structure and a method of manufacturing such a device - Google Patents

A semiconductor device with a v-groove insulating isolation structure and a method of manufacturing such a device

Info

Publication number
DE3175640D1
DE3175640D1 DE8181301189T DE3175640T DE3175640D1 DE 3175640 D1 DE3175640 D1 DE 3175640D1 DE 8181301189 T DE8181301189 T DE 8181301189T DE 3175640 T DE3175640 T DE 3175640T DE 3175640 D1 DE3175640 D1 DE 3175640D1
Authority
DE
Germany
Prior art keywords
manufacturing
isolation structure
insulating isolation
semiconductor device
groove insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181301189T
Other languages
German (de)
English (en)
Inventor
Takeshi Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3175640D1 publication Critical patent/DE3175640D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H10W20/065—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by making at least a portion of the conductive part non-conductive, e.g. by oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
DE8181301189T 1980-03-25 1981-03-19 A semiconductor device with a v-groove insulating isolation structure and a method of manufacturing such a device Expired DE3175640D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3807080A JPS56146247A (en) 1980-03-25 1980-03-25 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
DE3175640D1 true DE3175640D1 (en) 1987-01-08

Family

ID=12515223

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181301189T Expired DE3175640D1 (en) 1980-03-25 1981-03-19 A semiconductor device with a v-groove insulating isolation structure and a method of manufacturing such a device

Country Status (5)

Country Link
US (1) US4497665A (https=)
EP (1) EP0036764B1 (https=)
JP (1) JPS56146247A (https=)
DE (1) DE3175640D1 (https=)
IE (1) IE52351B1 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58105551A (ja) * 1981-11-20 1983-06-23 Fujitsu Ltd 半導体装置
JPS59155944A (ja) * 1983-02-25 1984-09-05 Mitsubishi Electric Corp 半導体装置の製造方法
US4610730A (en) * 1984-12-20 1986-09-09 Trw Inc. Fabrication process for bipolar devices
US4849371A (en) * 1986-12-22 1989-07-18 Motorola Inc. Monocrystalline semiconductor buried layers for electrical contacts to semiconductor devices
JPS6467945A (en) * 1987-09-08 1989-03-14 Mitsubishi Electric Corp Wiring layer formed on buried dielectric and manufacture thereof
CN1034228C (zh) * 1993-08-04 1997-03-12 株洲冶炼厂 一种自萃除有色金属的富铁有机相中除铁的方法
DE19538005A1 (de) * 1995-10-12 1997-04-17 Fraunhofer Ges Forschung Verfahren zum Erzeugen einer Grabenisolation in einem Substrat
US20110241185A1 (en) * 2010-04-05 2011-10-06 International Business Machines Corporation Signal shielding through-substrate vias for 3d integration

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3956033A (en) * 1974-01-03 1976-05-11 Motorola, Inc. Method of fabricating an integrated semiconductor transistor structure with epitaxial contact to the buried sub-collector
US4037306A (en) * 1975-10-02 1977-07-26 Motorola, Inc. Integrated circuit and method
US4048649A (en) * 1976-02-06 1977-09-13 Transitron Electronic Corporation Superintegrated v-groove isolated bipolar and vmos transistors
DE2837800A1 (de) * 1978-08-30 1980-03-13 Philips Patentverwaltung Verfahren zum herstellen von halbleiterbauelementen
JPS5534442A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
US4214918A (en) * 1978-10-12 1980-07-29 Stanford University Method of forming polycrystalline semiconductor interconnections, resistors and contacts by applying radiation beam
US4269636A (en) * 1978-12-29 1981-05-26 Harris Corporation Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking
JPS6043024B2 (ja) * 1978-12-30 1985-09-26 富士通株式会社 半導体装置の製造方法
EP0030286B1 (de) * 1979-11-23 1987-09-09 Alcatel N.V. Dielektrisch isoliertes Halbleiterbauelement und Verfahren zur Herstellung
US4295924A (en) * 1979-12-17 1981-10-20 International Business Machines Corporation Method for providing self-aligned conductor in a V-groove device
US4260436A (en) * 1980-02-19 1981-04-07 Harris Corporation Fabrication of moat resistor ram cell utilizing polycrystalline deposition and etching

Also Published As

Publication number Publication date
IE52351B1 (en) 1987-09-30
IE810631L (en) 1981-09-25
EP0036764A2 (en) 1981-09-30
EP0036764B1 (en) 1986-11-20
EP0036764A3 (en) 1984-01-18
JPS6227744B2 (https=) 1987-06-16
JPS56146247A (en) 1981-11-13
US4497665A (en) 1985-02-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee