DE3171328D1 - Two-level threshold circuitry for large scale integrated circuit memories - Google Patents

Two-level threshold circuitry for large scale integrated circuit memories

Info

Publication number
DE3171328D1
DE3171328D1 DE8181304890T DE3171328T DE3171328D1 DE 3171328 D1 DE3171328 D1 DE 3171328D1 DE 8181304890 T DE8181304890 T DE 8181304890T DE 3171328 T DE3171328 T DE 3171328T DE 3171328 D1 DE3171328 D1 DE 3171328D1
Authority
DE
Germany
Prior art keywords
integrated circuit
large scale
level threshold
scale integrated
circuit memories
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181304890T
Other languages
English (en)
Inventor
Ta-Ming Wu
Lance Ray Murray
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Application granted granted Critical
Publication of DE3171328D1 publication Critical patent/DE3171328D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/067—Single-ended amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Read Only Memory (AREA)
  • Manipulation Of Pulses (AREA)
  • Measurement Of Current Or Voltage (AREA)
DE8181304890T 1981-02-17 1981-10-20 Two-level threshold circuitry for large scale integrated circuit memories Expired DE3171328D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/235,040 US4435658A (en) 1981-02-17 1981-02-17 Two-level threshold circuitry for large scale integrated circuit memories

Publications (1)

Publication Number Publication Date
DE3171328D1 true DE3171328D1 (en) 1985-08-14

Family

ID=22883836

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181304890T Expired DE3171328D1 (en) 1981-02-17 1981-10-20 Two-level threshold circuitry for large scale integrated circuit memories

Country Status (5)

Country Link
US (1) US4435658A (de)
EP (1) EP0058273B1 (de)
JP (1) JPS57151869A (de)
CA (1) CA1192271A (de)
DE (1) DE3171328D1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5975721A (ja) * 1982-10-25 1984-04-28 Toshiba Corp 信号入力回路およびその制御方法
US4512030A (en) * 1983-01-28 1985-04-16 Motorola, Inc. High speed presettable counter
JPS621191A (ja) * 1985-03-11 1987-01-07 Nec Ic Microcomput Syst Ltd 信号出力回路
US4808854A (en) * 1987-03-05 1989-02-28 Ltv Aerospace & Defense Co. Trinary inverter
US4743842A (en) * 1987-03-11 1988-05-10 Grumman Aerospace Corporation Tri-state circuit tester
US5121004A (en) * 1991-08-09 1992-06-09 Delco Electronics Corporation Input buffer with temperature compensated hysteresis and thresholds, including negative input voltage protection
US5486774A (en) * 1991-11-26 1996-01-23 Nippon Telegraph And Telephone Corporation CMOS logic circuits having low and high-threshold voltage transistors
US5544175A (en) * 1994-03-15 1996-08-06 Hewlett-Packard Company Method and apparatus for the capturing and characterization of high-speed digital information
JPH103796A (ja) * 1996-06-14 1998-01-06 Nec Corp センスアンプ回路
JP3451579B2 (ja) * 1997-03-03 2003-09-29 日本電信電話株式会社 自己同期型パイプラインデータパス回路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3851189A (en) * 1973-06-25 1974-11-26 Hughes Aircraft Co Bisitable digital circuitry
JPS547372A (en) * 1977-06-17 1979-01-20 Seiko Epson Corp Electronic watch
JPS5467476A (en) * 1977-11-09 1979-05-30 Fuji Electric Co Ltd Level detecting switch circuit
JPS553210A (en) * 1978-06-21 1980-01-11 Toshiba Corp Waveform shaping circuit
US4224539A (en) * 1978-09-05 1980-09-23 Motorola, Inc. FET Voltage level detecting circuit
JPS5856198B2 (ja) * 1980-09-25 1983-12-13 株式会社東芝 半導体記憶装置

Also Published As

Publication number Publication date
EP0058273A3 (en) 1982-12-29
EP0058273B1 (de) 1985-07-10
US4435658A (en) 1984-03-06
EP0058273A2 (de) 1982-08-25
CA1192271A (en) 1985-08-20
JPS57151869A (en) 1982-09-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: EISENFUEHR, G., DIPL.-ING. SPEISER, D., DIPL.-ING., PAT.-ANW., 2800 BREMEN

8339 Ceased/non-payment of the annual fee