DE3143216C2 - Semiconductor wafer with dicing sections and process for their manufacture - Google Patents

Abstract

The semiconductor device according to the invention comprises a semiconductor wafer which has a groove (406) covered with a thin glass layer (410) for dividing the semiconductor device into a plurality of semiconductor components. An elevation (407) is formed at the bottom of the groove (406). The semiconductor device can easily be divided along this elevation (407) without the glass layer (410) cracking or peeling off. In the production method according to the invention, the elevation (407) is produced on the bottom of the groove (406) by forming a zone on the surface of the intended dicing section of the semiconductor wafer, with the exception of the central area of the dicing section, the etching speed of which is greater than the etching speed of the remaining surface area is, whereupon the semiconductor wafer is subjected to an etching treatment.

Description

a) on a main surface of the semiconductor washer with Except for a dividing section arranged between adjacent semiconductor components an etch-resistant thin layer (605, 508) is applied,

b) the dicing section is etched to form a groove (612), and

c) on the groove (612) a thin glass layer (6161 is applied, which in the middle area of the The bottom of the groove (612) has a smaller thickness than in the area of the edge of the groove (612),

characterized in that

d) before the etching of the groove (612) (step b)) in the surface area of the division spacing with the exception of the center of the surface area zones (610, 504) with opposite the Center of the surface area of higher etching speed are formed, and

bl) the dividing section with the formation of an elevation (614) at the bottom of the groove (612) is etched.

6. The method according to claim 5, characterized in that in process step d) the zones (610) with the higher etching speed compared to the center of the surface area Doping can be formed with a dopant whose conductivity type corresponds to the conductivity type of the center of the surface area is opposite.

7. The method according to claim 5, characterized in that in process step d) the zones (504) with the higher etching speed compared to the center of the surface area Increasing the doping concentration of these zones compared to the doping concentration of the Center of the surface area are formed.

8. The method according to any one of claims 5 to 7, characterized in that in step b) the groove (612) is formed so deep that its bottom is deeper than the pn junction is located

9. The method according to any one of claims ί to 8, characterized in that in process step c) a glass powder-containing solution is applied in the groove (612) and then the applied glass powder is sintered.

10. The method according to any one of claims 5 to 9, characterized in that in process step c) the thin glass layer (616) in the area is formed above the pn junction in a thickness of at least 15 μπι.

The invention relates to a semiconductor wafer according to the preamble of claim 1 and a method for dividing a semiconductor wafer according to the preamble of claim 5.

When manufacturing semiconductor components, a plurality of the desired semiconductor components is usually used formed in a common semiconductor wafer which is then cube-shaped Pieces or tablets are divided according to the semiconductor components. It is extraordinary important, on the whole of the distribution section To apply an insulating layer to the surface of the semiconductor substrate and the surface of the semiconductor substrate to be passivated in order to increase the reliability of the semiconductor device.

For this purpose, semiconductor devices are usually in a mesa structure to achieve a high dielectric strength. This procedure should be based on a: n FIG. 1 shown Thyristor structure are briefly explained. In the thyristor according to FIG. 1 are on both major surfaces an n-silicon semiconductor wafer, a p-zone 602 or a p-zone 603 attached in the p-zone 602, an η + -zone 608 is formed selectively The individual semiconductor components are separated from one another by a mesa structure creating grooves 612 which are deeper than the pn junctions are sufficient for passivation of the pn junctions with a thin glass layer each 616 are covered. After the grooves 612 have been covered with the thin glass layers 616, a calhode electrode is formed 618 and control electrodes 618,620 are formed. The structure made in this way will be on the points indicated by dashed lines from the top of the thin glass layers on the bottom of the respective grooves 612 divided into pieces in order to separate the individual semiconductor components from one another Form available.

The conventional cutting methods for semiconductor components include scribing the semiconductor disk a laser beam, cutting by means of a saw blade, sawing by means of a Saw wire, as well as the scribing and breaking of the semiconductor wafer with a diamond graver. Because of Comparative tests carried out with regard to the breaking or flaking of the thin glass layers when dividing or with regard to the requirements and

The most common operating characteristics of the cutting devices has been to use a diamond Proven method which makes the semiconductor tablets available at the lowest cost The diamond scribing method as the best division method so far developed is, however, deficient in this respect afflicted than the ability of a semiconductor wafer to be diced to a large extent from that during dicing The thickness of the GlEUschichtschicht taken depends on If, for example the glass layer thickness is more than 20 Jim, the ability to split suddenly decreases, what to break and peel off the glass layer, reducing the yield and deterioration of the properties leads With a lower glass layer thickness, the ability to split is improved the semiconductor wafer, but the thickness of the glass layer at the pn junction is also reduced. This affects in turn, the dielectric strength disadvantageously and deteriorates the reliability of semiconductor components. If the glass layer thickness is less than ίΰμπι, form in the glass layer Blowholes, whereby the dielectric strength decreases. For these reasons, the glass layer strength not be reduced beyond this value. The optimal glass layer thickness is around 15 μm. It is however, it is difficult to adjust the casting layer to this optimum thickness, since it is difficult to achieve a uniform one Produce a glass layer by means of electrophoresis and a uniform, mesa-shaped groove.

In order to improve these shortcomings, as shown in FIG. 2 from Japanese Patent Publication 51-49 395 known, on each main surface between respectively adjacent semiconductor components a pair of grooves 612 in the same manner as in FIG. 1 to produce and the semiconductor wafer at the between to divide the two grooves 6i2 existing section. Since none of the glass layers 616 are broken in this way, the cracking and peeling can be prevented prevent the gaseous layer. The glass layer 616 can therefore be formed with a relatively large thickness However, by forming a pair of grooves 612 between adjacent semiconductor devices the usable area of the semiconductor wafer and thus the yield is smaller than in the case of Fig. 1

Another known, based on FIG. 3 as illustrated in Japanese Patent Publication 50-4 541 is described. consists in applying the thin glass layer 616 in the groove 612, which the pn junction in the same way as in the case of FIG. 1 exposed. On the thin glass layer 616 a thin metal layer 301 is applied, whereupon the semiconductor wafer is cut up at this point. With this one However, there is a risk of the method that when the semiconductor wafer is scribed by means of the diamond stylus the resulting metal chips stick to the blade of the cut-off saw. This leads to business interruptions and for the saw blade to slide out during the scribing process, the saw blade does not interfere with the semiconductor wafer can split and ultimately the yield is reduced.

From DE-OS 23 06 842 one is provided for dividing Semiconductor wafer similar to that of FIG. 1 or 2 known, but at least on the one side of the semiconductor wafer on both sides of the groove provided for the division one further, Groove, likewise covered with a thin layer of gass, is arranged in parallel. Take over these side grooves the isolation of the PN junctions, so that flaking This does not cause any damage to the glass layer when dividing the groove provided for the dividing However, it is bought at the cost of a considerable loss of practically usable surface area of the semiconductor wafer

A semiconductor wafer according to the preamble of claim 1 and a method for producing a Semiconductor wafer according to the preamble of claim 5 are known from GB-PS 12 93 807 In In this prior art, grooves are similar to those above in connection with FIG. 1 described, trained, however, the thickness of the glass layer is smallest in the middle of the bottom of the groove and towards both edges of the groove towards pie semiconductor wafer can then be divided at points where the glass layer is proportionate is thin so that the division is simplified and unwanted damage to the glass layer is prevented. To achieve the minimum thickness in the middle of the groove base, one over the edge the groove overhanging oxide layer * made use

The object of the invention is to provide an easily split semiconductor wafer and a method for its production indicate with a sufficient glass layer thickness in the places where a high dielectric strength required is guaranteed, there is no risk that this glass layer during the cutting process breaks or flakes off and no overhanging oxide layer is used in their manufacture must become.

According to the invention, this object is achieved by a semiconductor wafer having the features of claim 1 or solved by a method having the features of claim 5.

The invention is explained in more detail with reference to the drawings

F i g. 1 to 3 cuts through the known manufacturing processes dicing areas of a semiconductor wafer provided by mesa thyristors;

4 shows a section through a dividing area a semiconductor wafer according to the invention;

F i g. 5a to 5f, sections through the successive manufacturing steps of a first embodiment semiconductor structures produced by the method according to the invention;

F i g. 6a and 6f sections through the successive manufacturing steps of a further embodiment semiconductor structures produced by the method according to the invention, and

Fi g. 7 shows a plan view of the semiconductor structure according to FIG F i g. 6c.

In the arrangement according to FIG. 4 is at the bottom of a groove 6? "Of the semiconductor wafer, along which this later is to be divided, an elevation 614 is formed. The semiconductor wafer supports a plurality of semiconductors components, such as diodes, each of which consists of a p-doped zone 506, an n-doped Zone 501 and an η + -doped zone 504 consists. With 404 and 405 insulating oxide layers are designated.

The elevation 614 is covered with an insulating thin layer which, for. B. by electrophoresis or is formed by stripping off a solution containing glass powder with subsequent sintering. The glass layer 616 can be applied substantially parallel with respect to the bottom surface 408 of the groove 612, as by the dashed line 409 is indicated, provided that the groove bottom surface 408 is flat in the usual way. But when on the groove bottom surface 408 according to the teaching of

According to the invention, the elevation 614 is formed, a glass layer is applied to the top of the elevation 614 411 thinner than the glass layer 616 in the remaining area. Furthermore, the internal structure of the glass layer is inclined 411 on top of the bump 614 for non-uniformity. This allows the semiconductor wafer easily split without the glass layer cracking and / or flaking off. After all, due to the The surface tension of the solution containing glass powder on the elevation 614 is the strength of the pn junction formed glass layer larger than in conventional semiconductor wafers, in which the groove 612 without Elevation 614 is formed.

In an advantageous manner, a thin glass layer is therefore more sufficient in the semiconductor wafer according to the invention Strength (15 μm or more) formed there, where high dielectric strength is required, namely at the pn junction. On the bump where the riäiblciierscheibe Zcficni wcrdcü solos, bcsitii against it the thin glass layer has a thickness of 15 μm or less, which allows easy division of the semiconductor wafer without the glass layer cracking and / or flakes off.

The elevation 614 on the bottom surface of the groove 612 preferably has a relatively flat top. The height of the elevation 614 should be significantly smaller than the depth of the groove 612, in general a height of the elevation 614 between 4 and ΙΟμπι is sufficient.

The division of the semiconductor wafer according to the invention is in no way due to the scribing by means of a Diamond graver, but can also be done using any other conventional cutting method take place. Furthermore, the claimed manufacturing method is not limited to the exemplary embodiments described below limited, but can just as well be used on semiconductor wafers with other semiconductor elements, such as transistors, AC triode switches, etc. can be used.

In the following, using an exemplary embodiment relating to the manufacture of diodes the claimed method will be explained.

As shown in FIG. 5a, a semiconductor wafer 500, for example an n-silicon wafer with a thickness of about 250 μπι and a doping concentration between 1 to 5 · 10 ¹⁴ cm ^-3 , a steam oxidation at a temperature of about 1000 ⁰ C for a Subjected a period of 8 hours to thin oxide layers 502 and 503 in a thickness of about 2 μπι on both main surfaces of the semiconductor disk 500 to form.

In the next, as shown in 5b shows process step, the thin oxide layer 502 is selectively etched by a photoetching process Subsequently, an n-type dopant, such as phosphorus, on one main surface of the semiconductor wafer 500 in a concentration of for example 1 - 10 ²¹ cm ^-3 is diffused to form an η ⁺ -doped region 504.

Then, as shown in Fi g. 5c, the thin oxide layer 503 is removed and a p-type dopant, such as boron, ^{diffuses in at a concentration of 1 · ΙΟ 21} cm ^-3 to form a ρ + -doped zone 506.

In the subsequent method step illustrated in FIG. 5d, the thin oxide layer 502 is removed and a photoresist 508 is selectively applied by means of a photo-etching process. The photoresist 508 is used as a mask in the subsequent mesa etching, in which a groove 612 with a depth of approximately 80 μm is produced will. Mesa etching is a chemical process that uses a mixture of acids. Since the etching speeds of the n-silicon ^{zone 501 and the n +} -doped zone 504 are different due to the different dopant concentrations, an elevation 614 is formed on the bottom of the groove 612, which on its top has a width of about 2 μm and a height of about 4 has μπι.

ίο In the next method step illustrated in Fig. 5e becomes a thin glass layer 616 by means of electrophoresis or by means of a stripping process selectively formed in the groove 612. When using electrophoresis, the semiconductor wafer is dissolved in a solution made of alcohol and glass powder briefly immersed so that the glass powder adheres to the semiconductor wafer remain. The semiconductor wafer with the glass powder adhering to it is then placed in an oven sintered about 1000 "C for a period of one hour.

As a result, a thin, relatively flat glass layer 616 is formed within the groove 612. The glass layer 616 has a thickness of about 20 μm where it is connected to the pn junction and on the Elevation 514 has a thickness of about 15 μm.

The photoresist 508 is then removed and electrodes 518 and 520, for example made of aluminum, applied to the exposed areas. The semiconductor disk is then inserted into the individual semiconductor components divided by means of a diamond graver from above the elevation 614 to the Pieces made together into individual diodes Separate diodes (Fig. 5f).

In the following, a further exemplary embodiment will now be based on the production of thyristors. be tert.

First, as shown in FIG. 6a is shown, a p-Dotigrctrtff un £ for example gallium, in a semiconductor wafer, for example an n-silicon wafer with a thickness of about 240 μm, in the two main surfaces of which it diffuses thermally ^{at a concentration of 2 · 10 19 cm- 'or more,} to form p-doped zones 602 and 603 and an η-doped zone 601. The thermal diffusion takes place at a temperature of 1200 ° C for a period of 10 hours. The semiconductor wafer is then subjected to a steam oxidation at about 1000 ⁰ C for a period of 8 hours, to form a thin oxide layer 604th In the next method step illustrated in FIG. 6b, a contact hole 606 is produced in the p-doped zone 602 on a main surface of the semiconductor wafer with the aid of a photo-etching process in order to form an η-conductive zone as a cathode at this point. Simultaneously with this, a further contact hole 607 is formed at the dicing section of the semiconductor wafer where the groove is formed. Subsequently, as illustrated in FIGS a concentration of 7-10 · 10 ¹⁸ cm ^-3 at a temperature of 1200 ° C for a period of 8 hours thermally diffused F i g. 7 shows a schematic plan view of the FIG. 6c illustrated semiconductor wafer. After the dopant has diffused through the contact holes 606 and 607, an n-conductive zone 608 as a cathode and an n-conductive zone 610 are formed on the semiconductor wafer with the exception of the central region of the groove

100O ⁰ C for a period of 2 * 1 hours in order to form a thin oxide layer 605.

In the next method step illustrated in FIG. 6d the oxide layer 605 is removed in the region of the groove by means of a photo-etching process. Afterward the semiconductor wafer undergoes a chemical treatment, with an acid mixture of hydrofluoric acid, salt and acidic acid Acetic acid subjected to make a groove 612 with a depth of about 50 μm. It forms depends on the dopant concentration of the p- and η-conductive zones at the dividing section in the center of the groove 612 during its manufacture an approximately 7 μm high elevation 614. The width of the Elevation 614 fluctuates as a function of the size of the η-conductive zone converted into the groove and the etching rate achieved with the acid mixture.

In the subsequent, in F i g. 6e illustrated After the semiconductor wafer has been previously washed, a method step is a thin glass layer 616 in the groove 612 electroplated and sintered. For this purpose, the semiconductor wafer can again be immersed in a solution of alcohol and glass powder are briefly immersed, so that the glass powder on the semiconductor wafer due to the The electrophoresis effect remains adhering. The adhering glass layer is then kept at a temperature of Sintered 1000 ° C. for a period of 1 hour. The resulting glass layer 616 is relatively covered the inner surface of the groove 612 is flat. The glass layer 516 has a thickness of at the pn junction about 20 μm and on the elevation 614 a thickness of about 13 μm.

In the final, in FIG. 6f illustrated method step, the oxide layer is at a predetermined Remove the spot using a photo-etching process. After applying metal electrodes 618, 619 and 620, for example made of aluminum, the semiconductor wafer is cut into the individual semiconductor components.

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In addition 5 sheets of drawings

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Claims (5)

Patent claims: 1. Semiconductor disk on which a large number of semiconductor components, each with at least one PN junction is formed and in the adjacent semiconductor components by a Dividing section forming groove (612) are separated, which are covered with a thin glass layer (616) is which in the middle area of the bottom of the groove (612) has a smaller thickness than in the area of the edge of the groove adjoining the pn junction, characterized in that at the bottom the groove (612) has an elevation (614) whose height is less than the depth of the groove (612) and that the glass layer (411) on the top of the elevation (614) is thinner than in the rest Divide the bottom of the groove (612). 2. Semiconductor wafer according to claim 1, characterized gekennzeichncudaß the top of the bump (614) is fish. 3. A semiconductor wafer according to claim 1 or 2, characterized in that the height of the elevation (614) 4 to 10 μίτ. amounts to 4. Semiconductor wafer according to one of the preceding claims, characterized in that the thin glass layer (411, 616) in the area of the elevation (614) a thickness of not more than 15 μιτι and in the area of the groove area adjoining the pn junction, a thickness of not less than 15 μm owns 5. A method for producing a semiconductor wafer according to any one of claims 1 to 4 »in which