DE3110123A1 - FIELD EFFECT SEMICONDUCTOR DEVICES - Google Patents

Description

Patent Attorneys · European Patent Attorneys

Munich

G7 P55 D

GTE Laboratories Inc. Wilmington, Delaware, USA

Field effect semiconductor devices

Priority: March 17, 1980 -USA- Ser.No. 130 896

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description Field effect semiconductor devices

The invention relates to gate structures for static induction transistors, especially those that improve the performance of the transistors and simplify their manufacture.

It is a static induction transistor a field effect semiconductor device capable of operating at very high power and at high frequencies. These devices are characterized by relatively short, high resistance channels and they operate by depletion of the channel. the The current-voltage characteristics of a static induction transistor are similar to those of an unsaturated triode. Static induction transistors are described, for example, in U.S. Patent 3,828,230.

A vertical geometry is commonly used in a static induction transistor. The source and drain contacts are on opposite sides of a thin layer of a certain conductivity type with high Resistance arranged. Gate areas' from the opposite Conductivity types are diffused into the high resistance layer on opposite sides of the source. If a bias voltage is applied to the gate junctions in the opposite direction, the associated one expands Depletion region under the source, the channel being constricted between the source and the drain.

If good control of the drain current is to be achieved, relatively deep gate diffusions are required. However, this results in

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various disadvantages. First, has a deeply diffused Gate area has significant series resistance, which affects operation at high frequencies and secondly, it will require great depth diffusions to cover the entire device during the To keep the diffusion process at a high temperature for a relatively long time. During this taking place at high temperature During the process, impurities are caused as a result of diffusion from the substrate on which the layer of high resistance is bred to migrate into this layer, thereby increasing the effective thickness of the layer of high resistance. Because of this redistribution of charges, the initial thickness of the layer must be high Increase resistance by increasing the precipitation time allotted for the high resistance layer.

The invention is based on the object of providing improved Gat e. constructions for static induction transistors, especially those of little Specify resistance for static induction transistors and continue those that enable the manufacture of static induction transistors to be simplified.

According to the invention, these objects are achieved by providing a Field effect semiconductor device solved, which has ohmic source and drain contacts, further a layer of high Resistance made from a semiconductor material of a certain conductivity type and first and second rectifying gate junctions. The high resistance layer includes a first surface having a source contact formed thereon and a second surface with the drain contact formed on it, the arrangement being such that the high resistance layer between the source and drain a channel for conducting a current between the contacts

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forms. The high resistance layer also includes first and second grooves that connect the first surface of the high resistance layer on opposite sides of the source contact is provided. The first and second gate junctions are in areas near the surfaces of the first and second grooves arranged. Depletion zones are assigned to the gat e transitions, which extend into the High resistance layer extending into it and under the influence of a reverse bias applied to the gate junctions regulate the current by expanding into the canal and an associated threshold drain voltage set the size of which increases as the reverse bias applied to the gat e junctions increases. The current is interrupted as soon as a voltage that is lower than the threshold voltage is applied to the drain contact is created. The current increases without saturation occurring if one exceeds the threshold voltage increasing voltage is applied to the drain contact. The grooves that hold the layer of high resistance can have a V-shaped cross-section. The first and second gate junctions can each have one Gate area made of a semiconductor material from the opposite Have conductivity type. Alternatively, the first and second gate transitions each include a metal, which adheres firmly to the surfaces of the grooves, so that metal-semiconductor rectifier contacts are present in the grooves are.

Embodiments of the invention are explained in more detail below with reference to schematic drawings. It shows:

Fig. 1 is a partial section of a static induction transistor of known type;

Fig. 2 is a graph showing the relationship between drain current and drain voltage in a

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static induction transistor;

3 shows a partial section of a semiconductor crystal after the production of V-shaped grooves;

Fig. 4 is a partial section of a static induction transistor in which the gate areas as diffusion zones of are formed in V-shaped grooves with a shallow depth,

FIG. 5 is an oblique view of the static induction transistor according to FIG. 4;

6 shows a partial section of a static induction transistor with planar Schottky gate contacts; and

Fig. 7 is a partial section of a static induction transistor in which Schottky Gat e contacts in V-shaped grooves are trained.

In the figures, the various elements are not shown to scale. Certain dimensions are in comparison exaggerated to others in order to give a clearer picture of the invention.

In Fig. 1, a static induction transistor of known type with vertical geometry is shown. To its manufacture becomes an.epitaxial layer 10 of high resistance on a heavily doped substrate 12 of the one Conductivity type. An ohmic drain contact 14 is applied to the underside of the substrate 3 2. In the surface of the high resistance layer 10, a source diffusion of one conductivity type of little resistance

generated. V / pus gate diffusions. 18 of minor

Resistance made from a material of the opposite conductivity type are in the surface of the layer 10 of

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y-β

high resistance is generated on opposite sides of the source diffusion 16. An ohmic source contact 20 is connected to the source diffusion χ 6. Ohmic Gat e contacts 22 are made to the Gat e diffusions. The high resistance layer 10 forms a channel 24 through which current can flow between the source _and drain. If a high performance device is required, the structure of FIG. 1 is made in multiple forms on a single die, so that numerous channels are available for a current flowing between the source and the drain.

For operation in the frequency range of ί GHz, the layer .10 of high resistance typically less than 15 microns thick and a resistance of at least 30 ohmcm. During normal operation, a counter bias voltage is applied to the gate contacts 22. To those in the opposite direction biased gate junctions each include a depletion layer that diffused into the channel 24 under the Source 16 extends in and constricts channel 24. Static induction transistors like the one in Fig. due to their short channels of high resistance and due to the operation with depleted channel characteristics, which are similar to those of unsaturated triodes as shown in FIG. In Fig. 2 is the drain current is plotted along the vertical axis as a function of the drain voltage, the latter for various Values of the gate voltage is plotted on the horizontal axis. Curve 30 represents one low value of the reverse gate bias, while the Curves 32 and 34 successively represent higher values of this voltage. It can be seen that an increase in Value of the counter bias gate e. voltage generally has the effect that you have to increase the drain voltage, the

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must be applied to the device in order to make it conductive. Further details regarding the structure and the mode of operation of static induction transistors can be found in the following references: Nishizawa et al. in U.S. Patent 3,828,230; Nishizawa et al in "Field Effect Transistor Versus Analog Transistor (Static Induction Transistor)", IEEE Transactions on Electron Devices, Vol. ED 22, No. 4, April 1975; Nishizawa et al in "High Frequency High Power Static Induction Transistor, "IEEE Transactions on Electron Devices", Vol. ED 25, No. 3, March 1978.

As mentioned, in the case of the known static induction transistors Gat e diffusion of a relatively great depth be present (usually about 4 microns), and this results in a relatively high gate series resistance. Further during the deep diffusion process, impurities migrate from the substrate 12 to the layer 10 of high resistance, which reduces the effective thickness of this layer.

To manufacture a field effect semiconductor device or of a static induction transistor according to the invention is a plate or a substrate in the form of a single crystal made of a semiconductor material of a certain conductivity type used as a supporting base. The following Description relates to the use of silicon as a semiconductor material, but the invention is natural also applicable to other semiconductor materials. For example, the substrate is of the N conductivity type, it has a 250 microns thick and its resistance is 0.01 ohmcm.

In Fig. 3, a portion of a semiconductor die is shown during the manufacture of a static induction transistor of the invention shown. A thin, high resistance, N-conductivity type epitaxial layer 40 is formed on top of the

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Grown on top of a highly doped substrate 42 of the same conductivity type. For operation in the 1 gigahertz range, the high resistance layer 40 should have a thickness of less than 15 micrometers, and preferably about 12 micrometers. The resistance of layer 40 should be at least 30 ohm cm and preferably about 40 ohm cm. The surface of the layer 40 is provided with grooves or grooves 44 where the gates are to be created. Although the object of the invention can be achieved with the aid of grooves of any shape, grooves with a V-shaped cross section are usually used. DB Lee has shown in "Anisotropy Etching of Silicon", Journal of Applied Physics, Vol. 40 No. 11, 1969, pp. 4569-4574, that V-shaped grooves can be etched through a silicon dioxide layer 48 in silicon single crystals without difficulty if the plate has the surface orientation (100). The mask is oriented with respect to the platelet plane (110), which indicates the (HO) crystal direction. If an equimolar mixture of N ₉ H ^ and HgO is used, the etching process leads, with self-interruption, to the creation of grooves at an angle of 54.7 to the surface. The depth of the grooves depends only on the dimensions of the etching window. The depth of the V-shaped grooves 44 in the static induction transistor according to the invention is usually in the range of 20 to 40% of the thickness of the layer 40 of high resistance. For 1 GHz operation, the grooves 44 are typically spaced about 5 micrometers from the source.

In Fig. 4, a finished static induction transistor according to the invention is shown in a partial section. After the V-shaped grooves 44 have been produced, gate β junctions 50 are produced by a diffusion of shallow depth (in the present case of the P conductivity type). This diffusion leads to the creation of an area with graduated resistance

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stood in layer 40 of high resistance. Typically, the gate diffusions 50 are about 1 micrometer thick and are limited to the areas near the inwardly offset surfaces of the V-shaped grooves 44. A shallow source diffusion 52 of the N conductivity type is created in the area between the V-shaped grooves 54 on top of the layer 40 of high resistance. The presence of the source diffusion 52 facilitates the establishment of a low-resistance contact with the layer 40. As an alternative to the gate and source diffusions, known methods of ion implantation could also be used to produce these zones. Gate metallizations 54 are applied to the surface of the gate diffusions 50 in order to form ohmic gate contacts. A source metallization 56 is applied to the surface of the source diffusion region 52, so that an ohmic source contact is produced. A drain metallization 58 is applied to the underside of the substrate 42 to create an ohmic drain contact. The high resistance layer forms a channel 60 for a current flowing between the so'urce 56 and the drain 58 *

In FIG. 5, the static induction transistor according to the invention according to FIG. 4 is shown in a sectional oblique view. In the part of the semiconductor die shown in FIG. 5, the gate metallization 54 and the associated Ga te.diffusion 50 partially enclose the source metallization ^{56 and the} source diffusion 52. This arrangement offers good control of the current flowing between the source and the drain through the Gate. To enable higher power operation, multiple perpendicular channels, each controlled by gates located on opposite sides, can be made using known patterns of interdigitated source and gate zones.

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The operation of the static induction transistor of Figure 4 is generally the same as that described above of Fig. 1 described. The gat e transitions that at the interface between the gat e diffusions 50 and of high resistance layer 40 are associated with depletion zones that extend into layer 40 of extend into high resistance. If a counter bias is applied to the gat e junctions, they expand Depletion regions into channel 60 and control the current between source 56 and drain 58 as in FIG As shown in FIG. 2, the bias voltage applied to the gate junctions determines an associated threshold drain voltage. A drain current flows when the applied drain voltage is higher than the threshold value. On the other hand, is that If the drain voltage is lower than the threshold value, no current flows. The magnitude of the threshold drain voltage increases with the size of the applied gate voltage. The drain flow increases without any Saturation occurs when the Dra-in contact increases Drain voltage is applied, which is higher than the Schwel lendrain voltage.

To the static induction transistor shown in FIG includes a gate construction that allows good current regulation, but avoids the problems of which diffusion at gate e. of great depth. The Gat ο diffusions 50, their shallow depth ordinarily is 1 micrometer, have very small series resistances, which reduces the RF frequency response of the front of the device is improved. Furthermore, the gate diffusions 50, which have a small thickness, only require a short one

Treatment duration, which prevents that during the -Gate- / Diffusion process impurities from the substrate 42 in FIG

migrate into the high resistance layer 40.

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In Fig. 6 is a further inventive static induction transistor with an improved gate e structure which includes the following parts: a high resistance layer 62, a substrate 64, a source diffusion 66, a source metallization 68, a drain metallization 70 and a silicon dioxide layer 72, which of the layer 40 of high resistance or the substrate 42 or the source diffusion 52 or the source metallization 56 or the drain metallization 58 or the silicon dioxide layer 48 of the static induction transistor correspond to Fig. 4 and are produced in the manner described above. On opposite Sides of the source metallization 68 are in the silicon dioxide layer with the help of known cover or Masking process made openings, and metal-semiconductor rectifier contacts are generated in these openings in that Gat e metallizations 74 directly can be applied to the high resistance layer 62. The gate metallizations 74 can, for example, be made of aluminum, Chromium, nickel or tungsten exist. At the transition between the gate metallizations 74 and the layer 62 of high Resistance is created by metal-semiconductor rectifier contacts ♦ or Schottky contacts. The rectifier contacts practically form gate junctions, as is the case with gate diffusions of the P-type. The layer 62 of high Resistance forms a channel 76 for one between the sauce

68 and the drain 70 current flowing. Is applied to the Gatemetallisierungen 74 © e ⁱⁿ reverse bias, the depletion zones extend 78 in the layer 62 in high resistor. If the counter bias reaches a sufficient size, the depletion zones 78 expand into the channel 76 below the source diffusion 66, and regulate the drain current between the source 68 and the drain 70.

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The Schottky gate contact has a very low series resistance, so that the static induction transistor works with a good HP frequency response.

Furthermore, avoiding the use of diffusions of great depth results in the diffusion process during the gate no contaminants migrate from substrate 64 into high resistance layer 62. However the arrangement of the gate junctions on top of the high resistance layer 62 results in a reduction the controllability of the drain current.

Fig. 7 shows in section a preferred embodiment of the invention in the form of a static induction transistor with a gate e arrangement in which metal-semiconductor rectifier contacts are formed in grooves. To the transistor of FIG. 7 includes a layer 80 of high resistance, a substrate 82, a source diffusion region 84, a Sourcemetallisie ^r ung 86, a drain metallization 88 and a silicon dioxide layer 90, which layer 40 of high resistance or the substrate 42 or the source diffusion 52 or the source metallization 55 or the drain metallization zone 58 or the silicon dioxide layer 48 of the transistor described with reference to FIG. V-shaped grooves 92 are produced on both sides of the source diffusion 84 where the gate e are to arise, as has already been described with reference to FIG. 4. In the grooves 92 Gat e. metallization zones 94 generated in order to produce metal-semiconductor rectifier gate contacts or Schottky contacts. The high resistance layer 80 forms a channel 96 for the current flowing between the source 86 and the drain 88.

Associated with the gate junctions is a depletion region 98 which extends into the layer 80 of high resistance. If there is sufficient counter-

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When applied bias, the depletion zones 98 expand into the channel 96 under the source diffusion 84, and they regulate the drain current flowing between the source 86 and the drain 88 in the manner described. The drain current-drain voltage characteristics of the transistor 7 are similar to those shown in FIG.

When operating at 1 GHz, the high resistance layer 80 is typically less than 15 micrometers thick and preferably about 12 micrometers while their resistance is greater than 30 ohmcm, preferably about 40 ohmcm. The grooves 92 have a depth that is in the range of 20 to 40 percent of the thickness of the layer 80 of high resistance. the Gate arrangement according to FIG. 7 extends to a sufficient depth into the layer 80 of high resistance, to allow a good regulation of the drain current. The Schottky-Gat e contacts have an extremely low level Series resistance increases, which increases the RF frequency response

of the transistor improved. Since no gate diffusion is used, the problems that arise during the gate diffusion process can also be avoided result in contaminants migrating from substrate 82 into layer 80 of high resistance.

The above-described static induction transistors with high resistance layers, whose thickness is approximately 12 micrometers and whose resistance is approximately 40 Ohmcm, can be determined using a supply voltage of 100 V at a frequency of 1 GHz. With these transistors, the cutoff frequency is in the range from 2 to 3 GHz. It should be noted that high resistance layers of greater thickness can also be used can, so that suitable devices for higher voltages

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receives. However, the maximum operating frequency is lower when the high resistance layer has a larger one Thickness has. Correspondingly, in the case of layers of smaller thickness, devices are obtained which are suitable for a lower voltage, however, are suitable for a higher frequency. Resistance values in the range of 30 to 40 Ohmcm are preferred, but it is also possible to use layers with high resistance in static induction transistors, where the resistance is in the range of 1.5 to 100 Ohmcm.

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Claims (16)

Expectations Field effect half-parental device, characterized by an ohmic drain contact (58; 70; 88) of low resistance, an ohmic source contact of low resistance, a high resistance layer (40; 62; 80) of a semiconductor material of a certain conductivity type, to the one belongs to the first area, which is provided with the source contact, and a second area, which is provided with the drain contact. is provided so that this layer between the source contact and the drain contact forms a channel (60; 76; 96) through which a current is passed between the contacts, the layer of high resistance further comprising first and second grooves (44) , with which the first surface of the layer is provided on both sides of the source contact, v / obei the grooves have recessed areas in the layer of high resistance, and first and second rectifying gate junctions (54, 56) in the areas adjacent to the first and second grooves, the gate junctions being associated with depletion zones which extend into the layer of high resistance and, when a reverse bias is applied to the gate junctions, regulate said current by expanding into the channel and determining an associated threshold drain voltage which increases in magnitude when the reverse bias applied to the gate junctions is increased so that the current is interrupted when a voltage which is lower than the threshold voltage to which the drain contact is applied, and wherein the current increases without saturation occurring when an increasing voltage which is higher than the threshold voltage is applied to the drain contact. 130067/0818 2. Semiconductor device according to claim 1, characterized in that the first and second gate areas each includes a semiconductor material of the opposite conductivity type with ohmic contacts. 3. Semiconductor device according to claim 2, characterized in that to the drain contact von.geringem resistance a substrate made of a semiconductor material of one conductivity type, which is attached to the second surface of the Adjacent layer of high resistance, and that the thickness of the substrate is sufficient to provide mechanical support to form for the device. 4. A semiconductor device according to claim 3, characterized in that the grooves have a V-shaped cross section. 5. The semiconductor device according to claim 4, characterized in that the high resistance layer has a certain Has thickness and that the V-shaped grooves have a depth which is 20 to 40% of the thickness of the layer. 6. Semiconductor device according to claim 5, characterized in that the gate regions are graded as regions Resistance are formed. 7. A semiconductor device according to claim 6, characterized in that the high resistance layer is an epitaxial one Shift is. 8. The semiconductor device according to claim 7, characterized in that that the high resistance layer has a resistance of at least 30 ohmcm. 9. A semiconductor device according to claim 8, characterized in that the layer of high resistance is a Less than 15 microns thick. 130067/0618 10. The semiconductor device according to claim 1, characterized in that the first and second gate junctions
each include metal on the surfaces of the grooves
adheres to form metal-semiconductor rectifier contacts in the grooves. 11. The semiconductor device according to claim 10, characterized in that that to the drain contact of low resistance a substrate made of a semiconductor material of the aforesaid belongs to a conductivity type adjacent to the second surface of the high resistance layer, and that the thickness of the substrate is sufficient to provide mechanical support for the device. 12. The semiconductor device according to claim 11, characterized in that that the grooves have a V-shaped cross section. 13. Semiconductor device according to claim 12, characterized in that that the layer of high resistance has a certain thickness and that the V-shaped grooves have a depth which is 20 to 40% of the thickness of the layer. 14. The semiconductor device according to claim 13, characterized in that that the layer of high resistance is an epitaxial layer. 15. A semiconductor device according to claim 3 4, characterized in that the layer of high resistance is a
Has a resistance of at least 30 Ohmcm. 16. The semiconductor device according to claim 15, characterized in that that the thickness of the high resistance layer is less than 15 micrometers. 130067/0618