CA1149083A - Static induction transistors with improved gate structures - Google Patents
Static induction transistors with improved gate structuresInfo
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- CA1149083A CA1149083A CA000373040A CA373040A CA1149083A CA 1149083 A CA1149083 A CA 1149083A CA 000373040 A CA000373040 A CA 000373040A CA 373040 A CA373040 A CA 373040A CA 1149083 A CA1149083 A CA 1149083A
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- 230000003068 static effect Effects 0.000 title abstract description 18
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- 239000000463 material Substances 0.000 claims abstract description 10
- 230000005669 field effect Effects 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 17
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- 239000000377 silicon dioxide Substances 0.000 description 5
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
STATIC INDUCTION TRANSISTORS
WITH IMPROVED GATE STRUCTURES
Abstract of the Disclosure Vertical geometry static induction transistors have gate structures which improve high frequency performance and which simplify device fabrication. Ohmic source and drain contacts are formed on opposite sides of a layer of high resistivity semiconductor material of one conductivity type. Grooves, typically V-shaped, are formed in the sur-face of the high resistivity layer on opposite sides of the source. According to one embodiment, the gate junctions are formed by diffusing semiconductor material of the oppo-site conductivity type into the surfaces of the V-shaped grooves. According to another embodiment, the gate junc-tions are Schottky contacts formed by applying a metalliza-tion directly to the surfaces of the V-shaped grooves.
WITH IMPROVED GATE STRUCTURES
Abstract of the Disclosure Vertical geometry static induction transistors have gate structures which improve high frequency performance and which simplify device fabrication. Ohmic source and drain contacts are formed on opposite sides of a layer of high resistivity semiconductor material of one conductivity type. Grooves, typically V-shaped, are formed in the sur-face of the high resistivity layer on opposite sides of the source. According to one embodiment, the gate junctions are formed by diffusing semiconductor material of the oppo-site conductivity type into the surfaces of the V-shaped grooves. According to another embodiment, the gate junc-tions are Schottky contacts formed by applying a metalliza-tion directly to the surfaces of the V-shaped grooves.
Description
~7 ~ 83 S'L'ATIC INDUCTIO~.I T~~SISTORS
WITH IMPROVF~ GATE STRUCTUR~S
This invention relates to gate structures for static induction transistors, and, more particularl~, to yate structures which improve device pe.rformance and which simplify device fa~rication.
The static induction transistor is a field effect semiconductor device which e~hibit.s excellent high power :.
and high frequency capabilities. These devices are char~
acterized by relatively sAort, high resistivity chanrlels and operate with the channel depleted of carri~rs. The current-voltage characteristics of the stati.c induction transistor are similar to those of an unsaturated triode.
15 Static induc.tion transistors are disclosed by ~is'nizawa et al in U. S. ~atent No. 3,828,230 issued August.6, 1974r The static induction transistor (SIT~ typiccllly utilizes a vertical geometry. Source and drain contacts are placed on opposite sides of a thi.n, high resistivit.y layer of one conductivi.ty t~pe~ Gate regi.ons of the oppo~
site conductivity type are diffused into the hiyh resis-tivity layer on opposite sides of the source~ l~hen a reverse bias is applied to the gate junctions, the deple-tion region associated therewith extellds underneath the ~5 source and pinches off the channel between the source and drain.
In order to achie~e good control of the drai.n current, relativel~ deep gate diffusions are recsui.red~ ~lowever, the deep gate diffusi.ons have various disadvantages~ Firstt the deepl~ diffusecl gate reyion has an appreciable series resistarlce which adversely affects high freque~c~ opera--~ion Second, the deep ga-te cdiffusions require the entire ~ 7 ~ Q ~ 3 device -to be m~in.ta.-ned during the diffus.ion process at a high temperatUre for a relatively long period. During this high temperature process, impurities migrate by diffusion from the substrate on which the high resistivity layer is grown into the high resistivity layer, thus reducing the effective thickness of the high,resistivity layer. Due to this redistribution of charges, the initial thickness of the high resistivity layer must be increased by increasing the deposition time of the high resistivity layer.
Accordi-ngly, the present invention provides a field effect s~rniconductor device comprising: a low resistivity ohmic drain contact; a low resistivity ohmic source contact; a high resistivity layer of semiconductor rnaterial of one conductivity type, said high resistivity layer .includiny a first surface with said source con-tact formed '.
thereon and a second surface with said draîn contact forrned thereon such that said high resistivity layer ~-etween said source and drain contacts defines a channel ZO for conducting a cu~rent therebetween and said high resistivity layer further including f.irst and second grooves formed in the first surface of said high resistivity layer on opposite sides of said source contact, said grooves including recessed .surfaces in said high resistivity layer; and first and second rectifying gate junctions in regions approximate the surfaces of sa.id first and second grooves, respectively, whereby said gate junctions have associated depletion ,~,,3~7 ~ 3 I
regions which e~tend into said high resisti.vlt.y la~er 1.
and which, in response to a reve~se ~ias vol-age ..
appli.ed to said gate j~mctions, control said cur--ent by expandint~ into sai.d channel and estaL~lishing an associate~ threshold drairl voltage which increases in magnitl~de as said revers~ bias voltage app:Lied to said gate junctions increases iJI magnitude~ ~herc~by said ~urrent is Cllt off when a voltaye, lower in magnitude than said thxeshold voltage, is applied to said drain contact and wherehy said current increases wit~.out sa-,urating when an increasing voltage, greater .in magnitude than said thrt-~shold ~oltage, is applied to said drain contact~
~ome e.~bodiment of ihe inv~!lti.orl wll.l norr/ be descr:ibed, ~y way of exam.p1e, ~lth ~eference to -the accompanying drawlngs in which:
FIG. 1 is a cr(,sx-sectional view of a static 20 induction tr~nsi.stor acco:rding to the prior art, FIG. 2 is a graph illus~rating the drain current versus dra-~n ~701tage charactel-istics ~f a sta'ic inducti.on transistor;
FIG 3 is a cxoss-set.~tiorla.l view of a semiconductor ~r~,7stal after formation of V-shaped groov~s~
FIG. 4 is a cross--secti.~nal view t~ a s atic induction transistor wherPin t-he gate regions are fo~med a.s shallow , ' ' ' J ~ Z'~
diffusions in V-shaped grooves;
F~G. 5 is a perspective view of the static induction transistor shown in FIG. 4;
FIG. 6 is a cross-sectional view of a static induction transistor utilizing planar Schottky gate contacts; and FIG. 7 is a cross-sectional view of a stat.ic induction transistor wherein Schottky gate contacts are formed in V-shaped grooves.
~ n the figures, the various elements are not drawn to scale. Certain dimensions are exaggerated in relation to ot~er dimensions in order tG present a clearer underst2nd-ing of the invention.
For a better understanding of the present invention, together with other and further objects, ad~Tantages, and capabilities thereof, reference is made to the follo~7ing disclosure and appended claims in connection with che above-described drawings.
A static induction transistor with vertical geomecry according to the prior art is shown in FIG~ 1. A high resistivity epitaxial layer 10 is grown on a highly doped substrate 12 of one conductivity type. An ohmic drain con-tact 14 is applied to the l-~wer surface of the substrate 12.
A low resistivity source diffusion 16 of the one conductiv-ity type is formed in the upper surface of the high resis--tivity layer 10. Low resistivity gate diffusions 18 of the opposite con~uctivity type are formed in the upper surface of the high resistivi-ty layer 10 on opposite sides of the source diffusion 16. ~n ohmic source contact 20 is made to the source diffusion 16. Ohmic gate contacts 22 are made to the gate diffusions 1~. The high res.isti~Tity layer 10 provides a channel 24 for current flGw between t~e source .~7 ~ ~ ~g ~8 3 and the drain. ~hen a high power device is desired, t~le structure shown in FIG. 1 is repeated many times on a single wafer o~ semiconductor material, thus providing multiple channels for current flow between the source ana drain.
For operation in the one gigahertz frequency range, the high resistivity layer 10 is typically less than 15 microns in thickness and has a resistivity of at least ~0 ohm centimeters. In normal operation, a reverse bias voltage is applied to the gate contacts 22. The reverse biased gate junctions have an associated depletion layer which extends into the channel 24 underneath the source diffusion i6 and pinches off the channel 24. Static induc~
tion transistors such as the one shown in FIG. 1, because of their high resistivity short channels and operation with the channel depleted, exhibit non-saturating triode-liXe characteristics such as those shown in FIG. 2. Drain cur-rent is plotted on the vertical axis in FIG. 2 as a func-tion of drain voltage on the horizontal axis for various values of gate voltage. Cur~e 30 represents a low value of reverse bias gate voltage while curves 32 and 34 represent successively higher values of reverse bias gate voltage.
It can be seen that increasing the value of the reverse bias gate voltage has the general effect of increasing the drain voltage which must be applied to the device in order to cause it ~o conduct. Further details regarding ths con-struction and operation of static induction transistors are disclosed by Nishizawa et al in U. S. Patent No. 3,82~,230;
by Nishizawa et al in "Field Effect Transistor Versus 3Q Analog Transistor (Static Induction Transistor) llr IEEE
r~lransactions on E3ectron Devices~ Vol. ED-22, No. 4, April 1~7~; and by Nishizawa et al in "High Frequency High Power ~ 7 ~ 83 Static Induction l'ransistor", ~E~E Transactions on Electron - Devices, Vo:L. ED-25, ~o. 3, March 1978.
As noted hereinabove, prior art statlc induction tran-sistors required relatively deep gate diffusions (typically S about 4 microns in depth) which had relatively high series gate resistance. Furthermore, during the deep gate diffu-sions, impurities migrated from the substrate 12 in-to the high resistivity layer 10, thus reducing the effective thickness of the high resistivity layer 10.
In fabricating a field effect semiconductor device or static induction transistor (SIT) according to the present invention, a slice, or substrate, of single crystal semi- ' ' conductor material of one conductivity type is provided as a supporting structure. In t'ne follGwing description, silicon is emp]oyed as the semiconductor material, although the teachings are obviously applicable to other semiconduc-tor materials. Also, by ~Tay of eY~ample, the substrate is of ~-type conductivity, has a thickness or 250 micron~, and has a resist:ivity of .01 ohm centimeters.
~ eferring now to E`IG. 3, there is sho~n a fragment of a semiconductor wafer during processing of a stcatic induc-tion transistor according to a preferred embodiment of the present invention. A thin,high resistlvity epitaxial layer 40 of ~-type conductivity is grown on the upper surface of a highly doped substrate 42 of the same conductivity type~
For operation in the one gigahertz range, the high resis-tivity layer 40 should be less ~han 15 microns in thicXness, preferably, about l2 microns. ~he high resistivity layer 40 S'hOU d have a r~sistivity of at least 30 ohrr, centimeters~
preferably, about 40 ohm centimeters. Grooves 44 are formed in the upper surface of the high resistivlty layer40 ., ~ . .
~- " ~7 at the gate locations. While the objects of the invention can be achieved with grooves of any shape, V-shaped ~rooves are typically utilized. As shown by D. B. Lee in "Aniso-tropic Etching of Silicon", Journal of Applied Physics, Vol. 40, No. 11, 19~9, pp. 4569-4574, V~shaped grooves can be conveniently etched in silicon monocrystals through a silicon dioxide layer 48 when the wafer has a surface ori-entation of (100). The mask is oriented in referenc~ to the (110) wafer flat which is indicative of the (llOj crystal direction. When an equimolar mixture of N2H4 and H20 is used, the etching process will produce self-stopping grooves with an angle of 54.7 from the surface. The depth of the groove depends only on the etching window dimension.
The depth of the V-shaped grooves 44 in the SIT of the present invention is typically in the range of 20 to 40 percent of the thickness of the high resistivity layer ~0.
For one gigahertz operation, the grooves 44 are typically spaced abo~t 5 microns from the sourceO
A cross-sectional view of a completed SIT according to the present invention is shown in FIG~ 4~ ~fter the forma-tion of -the V-shaped grooves 44, gate junctions are formed by a shallow gate di~fusion 50 (P-type conductivity in the presen-t e~ample). The diffusion produces a region of graded resistivity in the hi~h resistivity layer 40.
Typically, the gate diffusions 50 are appro~imately one micron thickness and are confined to the regions near the rece.ssed sur~aces of the V-grooves 44. A shallow ~-t.ype ' ~i~7 ~ 3 source di~J~uc.ion 52 is formed in the region be-t~een the V-shaped grooves 54 on the upper surface o the high resistivity layer 40. The soùrce diffusion 52 facili-tates the making of a low resistance contact to layer 40.
As an alternative to gate and source diffusions, known techniques of ion implantation can be used to form gate and source regions. Gate metallizations 54 are applied to the surface o~ the gate diffusions 50 to form ohmic gate con-tacts. Source metalli~ation 56 is applied to the surface of source diffusion 52 to form an ohmic source contact.
Drain metalliza-tion 58 is applied to the lower surface of the substrate 42 to form an ohmic drain contact. The high resistivity layer 40 provides a channel 60 for curren-t flow between the source 56 and the drain 58.
- 15 A three dimensional view, partly in section, of the SIT of FIG. 4 is shown in FIG. 5. In the portion G~ the semiconductor wafer shown in FIG. 5, the gate metallization 54 and the associated gate diffusion 50 par-tially surround the source metallization 56 and the source dif~usion 52.
This configuration provides good control by -the gate of tne current flowing between the source and drain. To obtain higher power capability, multiple vertical channels, each controlled by gates located on opposite sides of the chan-nel, can be formed by utilizing known patterns of ~nter--locking source and gate re~ions.
The operation o~ -the SiT shown in FIG. 4 is generally the same as that described hereinabove in connection with the SIT shown in FIG. 1. The gate junctions which are formed at the interface between the gate diffusions 50 and the high resis-tivity layer 40 have an associated dep7etion region which exterlds into the high resistivity layer 40.
When a reverse bias voltage is applied -to the gate ' . . . .
..
, ~7 f~,L~ 3 junction-;, the d.-:pl2tion regions expand into the channol 60 and control the current hetween the source 56 ana the drain 58. As illustrated in FIG. 2,-the bias voltage applied to the gate junctions establishes an associated threshold drain voltage. When the applied drain voltage is ~reater than the threshold value, drain current flows. Conversely, when the applied drain voltaye is less than the threshold value, current does not flow. The magnitude of the thresh-old drain voltage increases as the magnitude of the applied gate voltage increases~ The drain current .increases with-out saturating when an increasing drain voltage, greater in magnitude than the threshold drain voltage, is applied to the drain contact.
The SIT shown in FIG. ~ has a gate struct~re which achieves good curren~ control ~7hile avoiding the problems associated with deep gate diffusionsr The shall.ow o,a-te diffusions 50, typically one micron i.n thickness, have very s~all series resistances, thus improving the high frequency response of ~he device. Also, the shallow gate diffusions 50 require a relatively short processing time, thus avoid-in~ migration of impurities from the substrate 42 into the high resis-tivity layer 40 during the gate diffusion process Anoth0r SIT having an improved gate structure is shown in FIG. 6. The SIT of FIG. 6 includes a high xesistivi~y layer 62, a sub.strate 64, a source diffusion 66, a source metal.lization 6~, a drain metallization 70, and a silicon dioxide layer 72 which correspond to the hign resistivi.ty la-~er 40, the substra-te 42, the source diffusion 52, the source metalli~ation 56, the drain metallization 58, and the silicon dioxi.de l~yer 48, respectively, of the .SIT
sho~7n in ~IG~ 4 and are fabricated in -the manner descri~ed hereina~ove. OE~enin~s are made in the silicon dioxide - s,~7 ~ 3 layer on oppos te sides of the source metallization 5~ by known masking techniques and metal-to-semiconductor recti-fying contacts are formed in the openings by applying gate metallizations 7~ directly to the higl~ resistivity layer 62. By way of example, the gate metallizations 74 can be aluminum, chromium, nickel, or tungsten. Ai the interface between the gate metallizations 74 and the high resistivity layer 62, metal-to-semiconductor rectifying contacts or Schottky cont~cts are formed. The rectifying contacts, in effect, form gate junctions as in the case Oc P-type gate diffusions. The high resistivity layer 62 provides a chan-nel 76 ~or current flow between the source 68 and the drain 70. When a reverse bias voltage is applied to gate metal-liæatio~s 74, depletion regions 78 extend into the high resistivity layer 62. When the reverse bias voltage has sufficient magnitude, the depletiQn regions 7~3 extend into the channel 76 underneath the source diffusion 66 and con-trol the drain current between the source 6~ and the drain 70~
The Scho-ttky gate contact has a very low series resis-tance, thus resulting in an SIT with good high frequency responseO Furthermore, the eli~ination of the deep gate diffusion eliminates the impurity migration from the sub-strate 64 into the high resistivity la~er 62 durlng tne gate diffusion process. However~ the location of the gate ~unctions on the upper surface of the high resistivity Layer 62 results in a reduced degree of drain current control~
A cross-sectional view of a preferred e~bodiment of the present invention is illustraLed in FIG. 7. An SIT has a gate structure wherein metal-to-semiconductor rectifying gate contacts are formed in groov~s. The SIT of FIG. 7 ~.~J~ 3 includes a hish resistivity layer 80, a substrate ~2, a source diffusion 84, a source metallization 86, a drain metallization 88, and a silicon dioxide layer 90 which correspond to the high resistivity layer 40, the substrate 5 42, the source diffusion 52, the source metallization 56, the drain metallization 58, and the silicon dioxide layer 48, respectively, of the SII~ illustrated in FIG. 4 and described hereinabove. V-shaped grooves 92 are formed in gate locations on opposite sides of the source diffus-on 8~r 10 as described hereinabove in connection with the SIT shown in FIG. 4. Gate metall.izations 94 are formed in grooves 92 SG as to form metal-to-semiconductor rectifying gate con-tacts or Schottky contacts. The high resist.ivity layer 80 provides a channel 96 for current flow between the source 15 86 and the drain 88.
The gate junctions have an associated depletion region 98 which extends into the high resistivity layer 80. When a reverse bias voltage of sufficient maynitude is appl..ied to th~ gate ~unctions, the depletion regions 98 e~pand into the channel 96 underneath the source diffusion a4 and con trol the drain current passing between the source 86 and the drain 88 as described hereinabove. The SIT shown in FIG. 7 has drain current-drain voltage characteristi.cs similar to those shown in FIG. 2.
For one gigahertz operation, the high resistivity layer 80 has a thickness of less than 15 microns, typically, about 12 microns, and has a resistivity greai:er -than 30 ohm centimeters, typically, about 40 ohm centimeters. r~ne yrooves 92 have a depth which i.s in the range o~ 20 to 40 percent of the thic~ness of the high resist.ivity layer 80.
rrhe yate structure shown in FIG. 7 has sufficient deptn into the high resistivity layer 80 to provide good control ,3~ 3 of the d~ain cuL-rent. The Schottky gate contacts have extremely low series resistance, thus improviny the high frequency response of the SIT. Also, since no gate diffu-sions are utilized, the problem of impurity migration from the substrate 82 into the high resistivity layer 80 during the gate diffusion process is eliminated.
The static induction transistors described hereir.~
above, with high resistivity layers having a thickness of ahout 12 microns and a resistivity of about 40 ohm centi-meters, are capable of operation at one gigahertz with asupply voltage of 100 volts. These SIT's have a cutoff frequency in the range of 2 to 3 gigahertz. It is to be understood that thicker high resistivity layers can be used and produce devices having higher voltage capability.
Eowever, the maximum operating frequency is lower when the high resistivity layer is thicker. Similarly, thinner high resistivity layers produce devices having lower voltage but higher frequency capabilities. Furthermore, while resis-tivities in the range of 30 to 40 ohm centimeters are pre-ferred, high resistivity layers having resistivities in therange of 15 to 100 ohm centimeters can be used in sta-tic induction transistors.
While there has been shown and-described what is at present considered the preferred embodiments of the inven-tion, it will be obvious to those skilled in the art thatvarious changes and modifications may be made therein with-out departing from the scope of the invention as dafined by the appended claims.
.. . ..
:
WITH IMPROVF~ GATE STRUCTUR~S
This invention relates to gate structures for static induction transistors, and, more particularl~, to yate structures which improve device pe.rformance and which simplify device fa~rication.
The static induction transistor is a field effect semiconductor device which e~hibit.s excellent high power :.
and high frequency capabilities. These devices are char~
acterized by relatively sAort, high resistivity chanrlels and operate with the channel depleted of carri~rs. The current-voltage characteristics of the stati.c induction transistor are similar to those of an unsaturated triode.
15 Static induc.tion transistors are disclosed by ~is'nizawa et al in U. S. ~atent No. 3,828,230 issued August.6, 1974r The static induction transistor (SIT~ typiccllly utilizes a vertical geometry. Source and drain contacts are placed on opposite sides of a thi.n, high resistivit.y layer of one conductivi.ty t~pe~ Gate regi.ons of the oppo~
site conductivity type are diffused into the hiyh resis-tivity layer on opposite sides of the source~ l~hen a reverse bias is applied to the gate junctions, the deple-tion region associated therewith extellds underneath the ~5 source and pinches off the channel between the source and drain.
In order to achie~e good control of the drai.n current, relativel~ deep gate diffusions are recsui.red~ ~lowever, the deep gate diffusi.ons have various disadvantages~ Firstt the deepl~ diffusecl gate reyion has an appreciable series resistarlce which adversely affects high freque~c~ opera--~ion Second, the deep ga-te cdiffusions require the entire ~ 7 ~ Q ~ 3 device -to be m~in.ta.-ned during the diffus.ion process at a high temperatUre for a relatively long period. During this high temperature process, impurities migrate by diffusion from the substrate on which the high resistivity layer is grown into the high resistivity layer, thus reducing the effective thickness of the high,resistivity layer. Due to this redistribution of charges, the initial thickness of the high resistivity layer must be increased by increasing the deposition time of the high resistivity layer.
Accordi-ngly, the present invention provides a field effect s~rniconductor device comprising: a low resistivity ohmic drain contact; a low resistivity ohmic source contact; a high resistivity layer of semiconductor rnaterial of one conductivity type, said high resistivity layer .includiny a first surface with said source con-tact formed '.
thereon and a second surface with said draîn contact forrned thereon such that said high resistivity layer ~-etween said source and drain contacts defines a channel ZO for conducting a cu~rent therebetween and said high resistivity layer further including f.irst and second grooves formed in the first surface of said high resistivity layer on opposite sides of said source contact, said grooves including recessed .surfaces in said high resistivity layer; and first and second rectifying gate junctions in regions approximate the surfaces of sa.id first and second grooves, respectively, whereby said gate junctions have associated depletion ,~,,3~7 ~ 3 I
regions which e~tend into said high resisti.vlt.y la~er 1.
and which, in response to a reve~se ~ias vol-age ..
appli.ed to said gate j~mctions, control said cur--ent by expandint~ into sai.d channel and estaL~lishing an associate~ threshold drairl voltage which increases in magnitl~de as said revers~ bias voltage app:Lied to said gate junctions increases iJI magnitude~ ~herc~by said ~urrent is Cllt off when a voltaye, lower in magnitude than said thxeshold voltage, is applied to said drain contact and wherehy said current increases wit~.out sa-,urating when an increasing voltage, greater .in magnitude than said thrt-~shold ~oltage, is applied to said drain contact~
~ome e.~bodiment of ihe inv~!lti.orl wll.l norr/ be descr:ibed, ~y way of exam.p1e, ~lth ~eference to -the accompanying drawlngs in which:
FIG. 1 is a cr(,sx-sectional view of a static 20 induction tr~nsi.stor acco:rding to the prior art, FIG. 2 is a graph illus~rating the drain current versus dra-~n ~701tage charactel-istics ~f a sta'ic inducti.on transistor;
FIG 3 is a cxoss-set.~tiorla.l view of a semiconductor ~r~,7stal after formation of V-shaped groov~s~
FIG. 4 is a cross--secti.~nal view t~ a s atic induction transistor wherPin t-he gate regions are fo~med a.s shallow , ' ' ' J ~ Z'~
diffusions in V-shaped grooves;
F~G. 5 is a perspective view of the static induction transistor shown in FIG. 4;
FIG. 6 is a cross-sectional view of a static induction transistor utilizing planar Schottky gate contacts; and FIG. 7 is a cross-sectional view of a stat.ic induction transistor wherein Schottky gate contacts are formed in V-shaped grooves.
~ n the figures, the various elements are not drawn to scale. Certain dimensions are exaggerated in relation to ot~er dimensions in order tG present a clearer underst2nd-ing of the invention.
For a better understanding of the present invention, together with other and further objects, ad~Tantages, and capabilities thereof, reference is made to the follo~7ing disclosure and appended claims in connection with che above-described drawings.
A static induction transistor with vertical geomecry according to the prior art is shown in FIG~ 1. A high resistivity epitaxial layer 10 is grown on a highly doped substrate 12 of one conductivity type. An ohmic drain con-tact 14 is applied to the l-~wer surface of the substrate 12.
A low resistivity source diffusion 16 of the one conductiv-ity type is formed in the upper surface of the high resis--tivity layer 10. Low resistivity gate diffusions 18 of the opposite con~uctivity type are formed in the upper surface of the high resistivi-ty layer 10 on opposite sides of the source diffusion 16. ~n ohmic source contact 20 is made to the source diffusion 16. Ohmic gate contacts 22 are made to the gate diffusions 1~. The high res.isti~Tity layer 10 provides a channel 24 for current flGw between t~e source .~7 ~ ~ ~g ~8 3 and the drain. ~hen a high power device is desired, t~le structure shown in FIG. 1 is repeated many times on a single wafer o~ semiconductor material, thus providing multiple channels for current flow between the source ana drain.
For operation in the one gigahertz frequency range, the high resistivity layer 10 is typically less than 15 microns in thickness and has a resistivity of at least ~0 ohm centimeters. In normal operation, a reverse bias voltage is applied to the gate contacts 22. The reverse biased gate junctions have an associated depletion layer which extends into the channel 24 underneath the source diffusion i6 and pinches off the channel 24. Static induc~
tion transistors such as the one shown in FIG. 1, because of their high resistivity short channels and operation with the channel depleted, exhibit non-saturating triode-liXe characteristics such as those shown in FIG. 2. Drain cur-rent is plotted on the vertical axis in FIG. 2 as a func-tion of drain voltage on the horizontal axis for various values of gate voltage. Cur~e 30 represents a low value of reverse bias gate voltage while curves 32 and 34 represent successively higher values of reverse bias gate voltage.
It can be seen that increasing the value of the reverse bias gate voltage has the general effect of increasing the drain voltage which must be applied to the device in order to cause it ~o conduct. Further details regarding ths con-struction and operation of static induction transistors are disclosed by Nishizawa et al in U. S. Patent No. 3,82~,230;
by Nishizawa et al in "Field Effect Transistor Versus 3Q Analog Transistor (Static Induction Transistor) llr IEEE
r~lransactions on E3ectron Devices~ Vol. ED-22, No. 4, April 1~7~; and by Nishizawa et al in "High Frequency High Power ~ 7 ~ 83 Static Induction l'ransistor", ~E~E Transactions on Electron - Devices, Vo:L. ED-25, ~o. 3, March 1978.
As noted hereinabove, prior art statlc induction tran-sistors required relatively deep gate diffusions (typically S about 4 microns in depth) which had relatively high series gate resistance. Furthermore, during the deep gate diffu-sions, impurities migrated from the substrate 12 in-to the high resistivity layer 10, thus reducing the effective thickness of the high resistivity layer 10.
In fabricating a field effect semiconductor device or static induction transistor (SIT) according to the present invention, a slice, or substrate, of single crystal semi- ' ' conductor material of one conductivity type is provided as a supporting structure. In t'ne follGwing description, silicon is emp]oyed as the semiconductor material, although the teachings are obviously applicable to other semiconduc-tor materials. Also, by ~Tay of eY~ample, the substrate is of ~-type conductivity, has a thickness or 250 micron~, and has a resist:ivity of .01 ohm centimeters.
~ eferring now to E`IG. 3, there is sho~n a fragment of a semiconductor wafer during processing of a stcatic induc-tion transistor according to a preferred embodiment of the present invention. A thin,high resistlvity epitaxial layer 40 of ~-type conductivity is grown on the upper surface of a highly doped substrate 42 of the same conductivity type~
For operation in the one gigahertz range, the high resis-tivity layer 40 should be less ~han 15 microns in thicXness, preferably, about l2 microns. ~he high resistivity layer 40 S'hOU d have a r~sistivity of at least 30 ohrr, centimeters~
preferably, about 40 ohm centimeters. Grooves 44 are formed in the upper surface of the high resistivlty layer40 ., ~ . .
~- " ~7 at the gate locations. While the objects of the invention can be achieved with grooves of any shape, V-shaped ~rooves are typically utilized. As shown by D. B. Lee in "Aniso-tropic Etching of Silicon", Journal of Applied Physics, Vol. 40, No. 11, 19~9, pp. 4569-4574, V~shaped grooves can be conveniently etched in silicon monocrystals through a silicon dioxide layer 48 when the wafer has a surface ori-entation of (100). The mask is oriented in referenc~ to the (110) wafer flat which is indicative of the (llOj crystal direction. When an equimolar mixture of N2H4 and H20 is used, the etching process will produce self-stopping grooves with an angle of 54.7 from the surface. The depth of the groove depends only on the etching window dimension.
The depth of the V-shaped grooves 44 in the SIT of the present invention is typically in the range of 20 to 40 percent of the thickness of the high resistivity layer ~0.
For one gigahertz operation, the grooves 44 are typically spaced abo~t 5 microns from the sourceO
A cross-sectional view of a completed SIT according to the present invention is shown in FIG~ 4~ ~fter the forma-tion of -the V-shaped grooves 44, gate junctions are formed by a shallow gate di~fusion 50 (P-type conductivity in the presen-t e~ample). The diffusion produces a region of graded resistivity in the hi~h resistivity layer 40.
Typically, the gate diffusions 50 are appro~imately one micron thickness and are confined to the regions near the rece.ssed sur~aces of the V-grooves 44. A shallow ~-t.ype ' ~i~7 ~ 3 source di~J~uc.ion 52 is formed in the region be-t~een the V-shaped grooves 54 on the upper surface o the high resistivity layer 40. The soùrce diffusion 52 facili-tates the making of a low resistance contact to layer 40.
As an alternative to gate and source diffusions, known techniques of ion implantation can be used to form gate and source regions. Gate metallizations 54 are applied to the surface o~ the gate diffusions 50 to form ohmic gate con-tacts. Source metalli~ation 56 is applied to the surface of source diffusion 52 to form an ohmic source contact.
Drain metalliza-tion 58 is applied to the lower surface of the substrate 42 to form an ohmic drain contact. The high resistivity layer 40 provides a channel 60 for curren-t flow between the source 56 and the drain 58.
- 15 A three dimensional view, partly in section, of the SIT of FIG. 4 is shown in FIG. 5. In the portion G~ the semiconductor wafer shown in FIG. 5, the gate metallization 54 and the associated gate diffusion 50 par-tially surround the source metallization 56 and the source dif~usion 52.
This configuration provides good control by -the gate of tne current flowing between the source and drain. To obtain higher power capability, multiple vertical channels, each controlled by gates located on opposite sides of the chan-nel, can be formed by utilizing known patterns of ~nter--locking source and gate re~ions.
The operation o~ -the SiT shown in FIG. 4 is generally the same as that described hereinabove in connection with the SIT shown in FIG. 1. The gate junctions which are formed at the interface between the gate diffusions 50 and the high resis-tivity layer 40 have an associated dep7etion region which exterlds into the high resistivity layer 40.
When a reverse bias voltage is applied -to the gate ' . . . .
..
, ~7 f~,L~ 3 junction-;, the d.-:pl2tion regions expand into the channol 60 and control the current hetween the source 56 ana the drain 58. As illustrated in FIG. 2,-the bias voltage applied to the gate junctions establishes an associated threshold drain voltage. When the applied drain voltage is ~reater than the threshold value, drain current flows. Conversely, when the applied drain voltaye is less than the threshold value, current does not flow. The magnitude of the thresh-old drain voltage increases as the magnitude of the applied gate voltage increases~ The drain current .increases with-out saturating when an increasing drain voltage, greater in magnitude than the threshold drain voltage, is applied to the drain contact.
The SIT shown in FIG. ~ has a gate struct~re which achieves good curren~ control ~7hile avoiding the problems associated with deep gate diffusionsr The shall.ow o,a-te diffusions 50, typically one micron i.n thickness, have very s~all series resistances, thus improving the high frequency response of ~he device. Also, the shallow gate diffusions 50 require a relatively short processing time, thus avoid-in~ migration of impurities from the substrate 42 into the high resis-tivity layer 40 during the gate diffusion process Anoth0r SIT having an improved gate structure is shown in FIG. 6. The SIT of FIG. 6 includes a high xesistivi~y layer 62, a sub.strate 64, a source diffusion 66, a source metal.lization 6~, a drain metallization 70, and a silicon dioxide layer 72 which correspond to the hign resistivi.ty la-~er 40, the substra-te 42, the source diffusion 52, the source metalli~ation 56, the drain metallization 58, and the silicon dioxi.de l~yer 48, respectively, of the .SIT
sho~7n in ~IG~ 4 and are fabricated in -the manner descri~ed hereina~ove. OE~enin~s are made in the silicon dioxide - s,~7 ~ 3 layer on oppos te sides of the source metallization 5~ by known masking techniques and metal-to-semiconductor recti-fying contacts are formed in the openings by applying gate metallizations 7~ directly to the higl~ resistivity layer 62. By way of example, the gate metallizations 74 can be aluminum, chromium, nickel, or tungsten. Ai the interface between the gate metallizations 74 and the high resistivity layer 62, metal-to-semiconductor rectifying contacts or Schottky cont~cts are formed. The rectifying contacts, in effect, form gate junctions as in the case Oc P-type gate diffusions. The high resistivity layer 62 provides a chan-nel 76 ~or current flow between the source 68 and the drain 70. When a reverse bias voltage is applied to gate metal-liæatio~s 74, depletion regions 78 extend into the high resistivity layer 62. When the reverse bias voltage has sufficient magnitude, the depletiQn regions 7~3 extend into the channel 76 underneath the source diffusion 66 and con-trol the drain current between the source 6~ and the drain 70~
The Scho-ttky gate contact has a very low series resis-tance, thus resulting in an SIT with good high frequency responseO Furthermore, the eli~ination of the deep gate diffusion eliminates the impurity migration from the sub-strate 64 into the high resistivity la~er 62 durlng tne gate diffusion process. However~ the location of the gate ~unctions on the upper surface of the high resistivity Layer 62 results in a reduced degree of drain current control~
A cross-sectional view of a preferred e~bodiment of the present invention is illustraLed in FIG. 7. An SIT has a gate structure wherein metal-to-semiconductor rectifying gate contacts are formed in groov~s. The SIT of FIG. 7 ~.~J~ 3 includes a hish resistivity layer 80, a substrate ~2, a source diffusion 84, a source metallization 86, a drain metallization 88, and a silicon dioxide layer 90 which correspond to the high resistivity layer 40, the substrate 5 42, the source diffusion 52, the source metallization 56, the drain metallization 58, and the silicon dioxide layer 48, respectively, of the SII~ illustrated in FIG. 4 and described hereinabove. V-shaped grooves 92 are formed in gate locations on opposite sides of the source diffus-on 8~r 10 as described hereinabove in connection with the SIT shown in FIG. 4. Gate metall.izations 94 are formed in grooves 92 SG as to form metal-to-semiconductor rectifying gate con-tacts or Schottky contacts. The high resist.ivity layer 80 provides a channel 96 for current flow between the source 15 86 and the drain 88.
The gate junctions have an associated depletion region 98 which extends into the high resistivity layer 80. When a reverse bias voltage of sufficient maynitude is appl..ied to th~ gate ~unctions, the depletion regions 98 e~pand into the channel 96 underneath the source diffusion a4 and con trol the drain current passing between the source 86 and the drain 88 as described hereinabove. The SIT shown in FIG. 7 has drain current-drain voltage characteristi.cs similar to those shown in FIG. 2.
For one gigahertz operation, the high resistivity layer 80 has a thickness of less than 15 microns, typically, about 12 microns, and has a resistivity greai:er -than 30 ohm centimeters, typically, about 40 ohm centimeters. r~ne yrooves 92 have a depth which i.s in the range o~ 20 to 40 percent of the thic~ness of the high resist.ivity layer 80.
rrhe yate structure shown in FIG. 7 has sufficient deptn into the high resistivity layer 80 to provide good control ,3~ 3 of the d~ain cuL-rent. The Schottky gate contacts have extremely low series resistance, thus improviny the high frequency response of the SIT. Also, since no gate diffu-sions are utilized, the problem of impurity migration from the substrate 82 into the high resistivity layer 80 during the gate diffusion process is eliminated.
The static induction transistors described hereir.~
above, with high resistivity layers having a thickness of ahout 12 microns and a resistivity of about 40 ohm centi-meters, are capable of operation at one gigahertz with asupply voltage of 100 volts. These SIT's have a cutoff frequency in the range of 2 to 3 gigahertz. It is to be understood that thicker high resistivity layers can be used and produce devices having higher voltage capability.
Eowever, the maximum operating frequency is lower when the high resistivity layer is thicker. Similarly, thinner high resistivity layers produce devices having lower voltage but higher frequency capabilities. Furthermore, while resis-tivities in the range of 30 to 40 ohm centimeters are pre-ferred, high resistivity layers having resistivities in therange of 15 to 100 ohm centimeters can be used in sta-tic induction transistors.
While there has been shown and-described what is at present considered the preferred embodiments of the inven-tion, it will be obvious to those skilled in the art thatvarious changes and modifications may be made therein with-out departing from the scope of the invention as dafined by the appended claims.
.. . ..
:
Claims (16)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A field effect semiconductor device comprising:
a low resistivity ohmic drain contact;
a low resistivity ohmic source contact;
a high resistivity layer of semiconductor material of one conductivity type, said high resistivity layer includ-ing a first surface with said source contact formed there-on and a second surface with said drain contact formed thereon such that said high resistivity layer between said source and drain contacts defines a channel for conducting a current therebetween and said high resistivity layer further including first and second grooves formed in the first surface of said high resistivity layer on opposite sides of said source contact, said grooves including recessed surfaces in said high resistivity layer; and first and second rectifying gate junctions in regions proximate the surfaces of said first and second grooves, respectively, whereby said gate junctions have associated depletion regions which extend into said high resistivity layer and which, in response to a reverse bias voltage applied to said gate junctions, control said current by expanding into said channel and establishing an associated threshold drain voltage which increases in magnitude as said reverse bias voltage applied to said gate junctions increases in magni-tude, whereby said current is cut off when a voltage, lower on magnitude than said threshold voltage, is applied to said drain contact and whereby said current increases with-out saturating when an increasing voltage, greater in mag-nitude than said threshold voltage, is applied to said drain contact.
2?,387
a low resistivity ohmic drain contact;
a low resistivity ohmic source contact;
a high resistivity layer of semiconductor material of one conductivity type, said high resistivity layer includ-ing a first surface with said source contact formed there-on and a second surface with said drain contact formed thereon such that said high resistivity layer between said source and drain contacts defines a channel for conducting a current therebetween and said high resistivity layer further including first and second grooves formed in the first surface of said high resistivity layer on opposite sides of said source contact, said grooves including recessed surfaces in said high resistivity layer; and first and second rectifying gate junctions in regions proximate the surfaces of said first and second grooves, respectively, whereby said gate junctions have associated depletion regions which extend into said high resistivity layer and which, in response to a reverse bias voltage applied to said gate junctions, control said current by expanding into said channel and establishing an associated threshold drain voltage which increases in magnitude as said reverse bias voltage applied to said gate junctions increases in magni-tude, whereby said current is cut off when a voltage, lower on magnitude than said threshold voltage, is applied to said drain contact and whereby said current increases with-out saturating when an increasing voltage, greater in mag-nitude than said threshold voltage, is applied to said drain contact.
2?,387
2. The field effect semiconductor device as defined in claim 1 wherein said first and second gate regions each include semiconductor material of the opposite conductivity type with ohmic contacts thereto.
3. The field effect semiconductor device as defined in claim 2 wherein said low resistivity drain contact includes a substrate of semiconductor material of the one conductiv-ity type contiguous said second surface of said high resis-tivity layer, said substrate having sufficient thickness to provide mechanical support for said device.
4. The field effect semiconductor device as defined in claim 3 wherein said grooves are V-shaped.
5. The field effect semiconductor device as defined in claim 4 wherein said high resistivity layer has a thickness and wherein said V-shaped grooves have a depth which is 20 to 40 percent of the thickness of said high resistivity layer.
6. The field effect semiconductor device as defined in claim 5 wherein said gate regions are regions of graded resistivity.
7. The field effect semiconductor device as defined in claim 6 wherein said high resistivity layer is an epitaxial layer.
8. The field effect semiconductor device as defined in claim 7 wherein said high resistivity layer has a resistiv-ity of at least 30 ohm centimeters.
?2,387
?2,387
9. The field effect semiconductor device as defined in claim 8 wherein said high resistivity layer has a thickness of less than 15 microns.
10. The field effect semiconductor device as defined in claim 1 wherein said first and second gate junctions each include metal adhered to said surfaces of said grooves, thereby forming metal-to-semiconductor rectifying contacts in said grooves.
11. The field effect semiconductor device as defined in claim 10 wherein said low resistivity drain contact in-cludes a substrate of semiconductor material of said one conductivity type contiguous said second surface of said high resistivity layer, said substrate having sufficient thickness to provide mechanical support for said device.
12. The field effect semiconductor device as defined in claim 11 wherein said grooves are V-shaped.
13. The field effect semiconductor device as defined in claim 12 wherein said high resistivity layer has a thick-ness and wherein said V-shaped grooves have a depth which is 20 to 40 percent of said thickness of said high resis-tivity layer.
14. The field effect semiconductor device as defined in claim 13 wherein said high resistivity layer is an epi-taxial layer.
15. The field effect semiconductor device as defined in claim 14 wherein said high resistivity layer has a resis-tivity of at least 30 ohm centimeters.
16. The field effect semiconductor device as defined in claim 15 wherein said high resistivity layer has a thick-ness of less than 15 microns.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13089680A | 1980-03-17 | 1980-03-17 | |
| US130,896 | 1980-03-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1149083A true CA1149083A (en) | 1983-06-28 |
Family
ID=22446867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000373040A Expired CA1149083A (en) | 1980-03-17 | 1981-03-16 | Static induction transistors with improved gate structures |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS56146282A (en) |
| CA (1) | CA1149083A (en) |
| DE (1) | DE3110123A1 (en) |
| GB (1) | GB2071912A (en) |
| IT (1) | IT1138998B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3230945A1 (en) * | 1982-08-20 | 1984-02-23 | Telefunken electronic GmbH, 7100 Heilbronn | METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR |
| FR2569056B1 (en) * | 1984-08-08 | 1989-03-10 | Japan Res Dev Corp | TUNNEL INJECTION TYPE STATIC INDUCTION TRANSISTOR AND INTEGRATED CIRCUIT COMPRISING SUCH A TRANSISTOR |
| CH670333A5 (en) * | 1986-04-30 | 1989-05-31 | Bbc Brown Boveri & Cie | |
| CH676402A5 (en) * | 1988-11-29 | 1991-01-15 | Asea Brown Boveri | Solid state pinch diode - has three zone structure with channel form and schottky electrode regions |
| US5705830A (en) * | 1996-09-05 | 1998-01-06 | Northrop Grumman Corporation | Static induction transistors |
| US8659057B2 (en) * | 2010-05-25 | 2014-02-25 | Power Integrations, Inc. | Self-aligned semiconductor devices with reduced gate-source leakage under reverse bias and methods of making |
-
1981
- 1981-03-10 IT IT20238/81A patent/IT1138998B/en active
- 1981-03-16 JP JP3669381A patent/JPS56146282A/en active Pending
- 1981-03-16 GB GB8108222A patent/GB2071912A/en not_active Withdrawn
- 1981-03-16 DE DE19813110123 patent/DE3110123A1/en not_active Withdrawn
- 1981-03-16 CA CA000373040A patent/CA1149083A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE3110123A1 (en) | 1982-02-18 |
| GB2071912A (en) | 1981-09-23 |
| JPS56146282A (en) | 1981-11-13 |
| IT1138998B (en) | 1986-09-17 |
| IT8120238A0 (en) | 1981-03-10 |
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