DE3070051D1 - Pipeline control apparatus for generating instructions in a digital computer - Google Patents

Pipeline control apparatus for generating instructions in a digital computer

Info

Publication number
DE3070051D1
DE3070051D1 DE8080103280T DE3070051T DE3070051D1 DE 3070051 D1 DE3070051 D1 DE 3070051D1 DE 8080103280 T DE8080103280 T DE 8080103280T DE 3070051 T DE3070051 T DE 3070051T DE 3070051 D1 DE3070051 D1 DE 3070051D1
Authority
DE
Germany
Prior art keywords
clk
instruction
instructions
macro
pipeline register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8080103280T
Other languages
English (en)
Inventor
John Thomas Gehmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wincor Nixdorf International GmbH
Original Assignee
Nixdorf Computer AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nixdorf Computer AG filed Critical Nixdorf Computer AG
Application granted granted Critical
Publication of DE3070051D1 publication Critical patent/DE3070051D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Nitrogen Condensed Heterocyclic Rings (AREA)
DE8080103280T 1979-09-10 1980-06-12 Pipeline control apparatus for generating instructions in a digital computer Expired DE3070051D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/073,597 US4310880A (en) 1979-09-10 1979-09-10 High-speed synchronous computer using pipelined registers and a two-level fixed priority circuit

Publications (1)

Publication Number Publication Date
DE3070051D1 true DE3070051D1 (en) 1985-03-14

Family

ID=22114647

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8080103280T Expired DE3070051D1 (en) 1979-09-10 1980-06-12 Pipeline control apparatus for generating instructions in a digital computer

Country Status (5)

Country Link
US (1) US4310880A (de)
EP (1) EP0025087B1 (de)
AT (1) ATE11607T1 (de)
CA (1) CA1145478A (de)
DE (1) DE3070051D1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621242A (en) * 1979-07-28 1981-02-27 Fujitsu Ltd Pipeline control method for computer operation
US4493020A (en) * 1980-05-06 1985-01-08 Burroughs Corporation Microprogrammed digital data processor employing microinstruction tasking and dynamic register allocation
US4390946A (en) * 1980-10-20 1983-06-28 Control Data Corporation Lookahead addressing in a pipeline computer control store with separate memory segments for single and multiple microcode instruction sequences
JPS60156151A (ja) * 1983-12-23 1985-08-16 Nec Corp メモリアクセス制御装置
US5008807A (en) * 1984-07-05 1991-04-16 Texas Instruments Incorporated Data processing apparatus with abbreviated jump field
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
US5179693A (en) * 1985-03-29 1993-01-12 Fujitsu Limited System for controlling operation of processor by adjusting duty cycle of performance control pulse based upon target performance value
JPH0789319B2 (ja) * 1985-04-22 1995-09-27 株式会社日立製作所 デ−タ処理装置における先行制御装置
JPS6282402A (ja) * 1985-10-07 1987-04-15 Toshiba Corp シ−ケンス制御装置
JPS6393038A (ja) * 1986-10-07 1988-04-23 Mitsubishi Electric Corp 計算機
US5210834A (en) * 1988-06-01 1993-05-11 Digital Equipment Corporation High speed transfer of instructions from a master to a slave processor
US5099450A (en) * 1988-09-22 1992-03-24 Syracuse University Computer for reducing lambda calculus expressions employing variable containing applicative language code
JPH05173779A (ja) * 1991-12-25 1993-07-13 Toshiba Corp デジタル演算集積回路
US8295966B2 (en) * 2009-06-30 2012-10-23 Lam Research Corporation Methods and apparatus to predict etch rate uniformity for qualification of a plasma chamber
US8271121B2 (en) * 2009-06-30 2012-09-18 Lam Research Corporation Methods and arrangements for in-situ process monitoring and control for plasma processing tools
US8473089B2 (en) * 2009-06-30 2013-06-25 Lam Research Corporation Methods and apparatus for predictive preventive maintenance of processing chambers
US8538572B2 (en) * 2009-06-30 2013-09-17 Lam Research Corporation Methods for constructing an optimal endpoint algorithm
US8618807B2 (en) * 2009-06-30 2013-12-31 Lam Research Corporation Arrangement for identifying uncontrolled events at the process module level and methods thereof
US8983631B2 (en) * 2009-06-30 2015-03-17 Lam Research Corporation Arrangement for identifying uncontrolled events at the process module level and methods thereof
CN101916180B (zh) * 2010-08-11 2013-05-29 中国科学院计算技术研究所 Risc处理器中执行寄存器类型指令的方法和其系统

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3576542A (en) * 1968-03-08 1971-04-27 Rca Corp Priority circuit
US3753014A (en) * 1971-03-15 1973-08-14 Burroughs Corp Fast inhibit gate with applications
DE2355992A1 (de) * 1972-12-21 1974-06-27 Gen Electric Hoechstgeschwindigkeit-mikroprogrammsteuereinheit und verfahren zur steuerung von datenverarbeitungsanlagen
IT993428B (it) * 1973-09-26 1975-09-30 Honeywell Inf Systems Unita di controllo di calcolatore microprogrammato con microprogram mi residenti in memoria e sovrap posizioni delle fasi interpretati ve di una microistruzione con la fase esecutiva della precedente microistruzione
IT1041882B (it) * 1975-08-20 1980-01-10 Honeywell Inf Systems Memoria dinamica a semiconduttori e relativo sistema di recarica
GB1527289A (en) * 1976-08-17 1978-10-04 Int Computers Ltd Data processing systems
US4090238A (en) * 1976-10-04 1978-05-16 Rca Corporation Priority vectored interrupt using direct memory access
US4159519A (en) * 1977-11-21 1979-06-26 Burroughs Corporation Template family interfacing structure for providing a sequence of microinstructions to a pipelined microprogrammable data processing system

Also Published As

Publication number Publication date
ATE11607T1 (de) 1985-02-15
EP0025087A2 (de) 1981-03-18
US4310880A (en) 1982-01-12
EP0025087A3 (en) 1982-04-21
EP0025087B1 (de) 1985-01-30
CA1145478A (en) 1983-04-26

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: SIEMENS NIXDORF INFORMATIONSSYSTEME AG, 4790 PADER

8339 Ceased/non-payment of the annual fee