DE2965080D1 - Integrated semiconductor circuit structure and method for realizing the same - Google Patents

Integrated semiconductor circuit structure and method for realizing the same

Info

Publication number
DE2965080D1
DE2965080D1 DE7979104339T DE2965080T DE2965080D1 DE 2965080 D1 DE2965080 D1 DE 2965080D1 DE 7979104339 T DE7979104339 T DE 7979104339T DE 2965080 T DE2965080 T DE 2965080T DE 2965080 D1 DE2965080 D1 DE 2965080D1
Authority
DE
Germany
Prior art keywords
realizing
same
circuit structure
semiconductor circuit
integrated semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE7979104339T
Other languages
English (en)
Inventor
Jean-Pierre Capuron
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE2965080D1 publication Critical patent/DE2965080D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11801—Masterslice integrated circuits using bipolar technology
DE7979104339T 1978-11-30 1979-11-06 Integrated semiconductor circuit structure and method for realizing the same Expired DE2965080D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7834433A FR2443185A1 (fr) 1978-11-30 1978-11-30 Topologie de circuits integres semi-conducteurs et procede pour l'obtention de cette topologie

Publications (1)

Publication Number Publication Date
DE2965080D1 true DE2965080D1 (en) 1983-04-28

Family

ID=9215779

Family Applications (1)

Application Number Title Priority Date Filing Date
DE7979104339T Expired DE2965080D1 (en) 1978-11-30 1979-11-06 Integrated semiconductor circuit structure and method for realizing the same

Country Status (4)

Country Link
EP (1) EP0011737B1 (de)
JP (1) JPS5575237A (de)
DE (1) DE2965080D1 (de)
FR (1) FR2443185A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1218104B (it) * 1986-06-27 1990-04-12 Sgs Microelettronica Spa Metodo di progettazione di microcalcolatori integrati e microcalcolatore integrato a struttura modulare ottenuto con il metodo suddetto
US5073729A (en) * 1990-06-22 1991-12-17 Actel Corporation Segmented routing architecture
EP0493989A1 (de) * 1990-12-31 1992-07-08 International Business Machines Corporation Masterslice-Chip-Zelle ausgestattet mit einer Vielzahl von Typen logischer Elemente

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1024661A (en) * 1974-06-26 1978-01-17 International Business Machines Corporation Wireable planar integrated circuit chip structure
JPS51117588A (en) * 1975-04-09 1976-10-15 Fujitsu Ltd Manufacturing method of semiconductor equipment
US4006492A (en) * 1975-06-23 1977-02-01 International Business Machines Corporation High density semiconductor chip organization
DE2643482A1 (de) * 1976-09-27 1978-03-30 Siemens Ag Halbleiterplaettchen zur herstellung hochintegrierter bausteine

Also Published As

Publication number Publication date
FR2443185B1 (de) 1981-11-20
EP0011737A1 (de) 1980-06-11
FR2443185A1 (fr) 1980-06-27
JPS5575237A (en) 1980-06-06
EP0011737B1 (de) 1983-03-23

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee