DE2962592D1 - Checking the memory addressing circuits of computers - Google Patents
Checking the memory addressing circuits of computersInfo
- Publication number
- DE2962592D1 DE2962592D1 DE7979302728T DE2962592T DE2962592D1 DE 2962592 D1 DE2962592 D1 DE 2962592D1 DE 7979302728 T DE7979302728 T DE 7979302728T DE 2962592 T DE2962592 T DE 2962592T DE 2962592 D1 DE2962592 D1 DE 2962592D1
- Authority
- DE
- Germany
- Prior art keywords
- computers
- checking
- memory addressing
- addressing circuits
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/964,992 US4227244A (en) | 1978-11-30 | 1978-11-30 | Closed loop address |
Publications (1)
Publication Number | Publication Date |
---|---|
DE2962592D1 true DE2962592D1 (en) | 1982-06-03 |
Family
ID=25509283
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE7979302728T Expired DE2962592D1 (en) | 1978-11-30 | 1979-11-29 | Checking the memory addressing circuits of computers |
Country Status (4)
Country | Link |
---|---|
US (1) | US4227244A (de) |
EP (1) | EP0012018B1 (de) |
JP (1) | JPS6034145B2 (de) |
DE (1) | DE2962592D1 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4334307A (en) * | 1979-12-28 | 1982-06-08 | Honeywell Information Systems Inc. | Data processing system with self testing and configuration mapping capability |
US4385349A (en) * | 1980-11-20 | 1983-05-24 | International Business Machines Corporation | Central processor supervised controller system having a simulation of the controller in the central processor for test purposes |
US4449182A (en) * | 1981-10-05 | 1984-05-15 | Digital Equipment Corporation | Interface between a pair of processors, such as host and peripheral-controlling processors in data processing systems |
US4608669A (en) * | 1984-05-18 | 1986-08-26 | International Business Machines Corporation | Self contained array timing |
US4726023A (en) * | 1986-05-14 | 1988-02-16 | International Business Machines Corporation | Determination of testability of combined logic end memory by ignoring memory |
FR2629248B1 (fr) * | 1988-03-25 | 1992-04-24 | Sgs Thomson Microelectronics | Procede de test de memoire a programmation unique et memoire correspondante |
US5231640A (en) * | 1990-07-20 | 1993-07-27 | Unisys Corporation | Fault tolerant processor/memory architecture |
JP2549209B2 (ja) * | 1991-01-23 | 1996-10-30 | 株式会社東芝 | 半導体記憶装置 |
GB9417266D0 (en) * | 1994-08-26 | 1994-10-19 | Inmos Ltd | Testing a non-volatile memory |
US7234099B2 (en) * | 2003-04-14 | 2007-06-19 | International Business Machines Corporation | High reliability memory module with a fault tolerant address and command bus |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3049692A (en) * | 1957-07-15 | 1962-08-14 | Ibm | Error detection circuit |
US3270318A (en) * | 1961-03-27 | 1966-08-30 | Sperry Rand Corp | Address checking device |
GB948519A (en) * | 1961-11-10 | 1964-02-05 | Ass Elect Ind | Improvements relating to arrangements for detecting signal transmission errors in telegraph and like systems |
US3665175A (en) * | 1968-09-03 | 1972-05-23 | Ibm | Dynamic storage address blocking to achieve error toleration in the addressing circuitry |
DE2209253A1 (de) * | 1972-02-26 | 1973-09-06 | Ibm Deutschland | Verfahren und schaltungsanordnung zur fehlerpruefung einer speicheradressierung |
DE2423260A1 (de) * | 1974-05-14 | 1975-11-20 | Siemens Ag | Verfahren und schaltungsanordnung zur pruefung von daten verarbeitenden anlagen, insbesondere fernsprechvermittlungsanlagen mit ueber ein busleitungssystem an eine steuerzentrale angeschlossenen peripheren einrichtungen |
US3982111A (en) * | 1975-08-04 | 1976-09-21 | Bell Telephone Laboratories, Incorporated | Memory diagnostic arrangement |
-
1978
- 1978-11-30 US US05/964,992 patent/US4227244A/en not_active Expired - Lifetime
-
1979
- 1979-11-29 EP EP79302728A patent/EP0012018B1/de not_active Expired
- 1979-11-29 DE DE7979302728T patent/DE2962592D1/de not_active Expired
- 1979-11-30 JP JP54156300A patent/JPS6034145B2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
EP0012018A1 (de) | 1980-06-11 |
JPS5577100A (en) | 1980-06-10 |
EP0012018B1 (de) | 1982-04-21 |
US4227244A (en) | 1980-10-07 |
JPS6034145B2 (ja) | 1985-08-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8327 | Change in the person/name/address of the patent owner |
Owner name: UNISYS CORP. (N.D.GES.D.STAATES DELAWARE), BLUE BE |
|
8328 | Change in the person/name/address of the agent |
Free format text: EISENFUEHR, G., DIPL.-ING. SPEISER, D., DIPL.-ING. RABUS, W., DR.-ING. BRUEGGE, J., DIPL.-ING., 2800 BREMEN MAIWALD, W., DIPL.-CHEM.DR., PAT.-ANWAELTE, 8000 MUENCHEN |
|
8339 | Ceased/non-payment of the annual fee |