DE2953861A1 - - Google Patents

Info

Publication number
DE2953861A1
DE2953861A1 DE19792953861 DE2953861A DE2953861A1 DE 2953861 A1 DE2953861 A1 DE 2953861A1 DE 19792953861 DE19792953861 DE 19792953861 DE 2953861 A DE2953861 A DE 2953861A DE 2953861 A1 DE2953861 A1 DE 2953861A1
Authority
DE
Germany
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19792953861
Other languages
German (de)
Other versions
DE2953861C2 (US20020095090A1-20020718-M00002.png
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of DE2953861A1 publication Critical patent/DE2953861A1/de
Application granted granted Critical
Publication of DE2953861C2 publication Critical patent/DE2953861C2/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Bus Control (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Microcomputers (AREA)
  • Executing Machine-Instructions (AREA)
DE2953861A 1978-11-08 1979-11-03 Expired DE2953861C2 (US20020095090A1-20020718-M00002.png)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/959,038 US4316244A (en) 1978-11-08 1978-11-08 Memory apparatus for digital computer system

Publications (2)

Publication Number Publication Date
DE2953861A1 true DE2953861A1 (US20020095090A1-20020718-M00002.png) 1982-09-16
DE2953861C2 DE2953861C2 (US20020095090A1-20020718-M00002.png) 1989-01-26

Family

ID=25501594

Family Applications (2)

Application Number Title Priority Date Filing Date
DE19792944419 Granted DE2944419A1 (de) 1978-11-08 1979-11-03 Digitalrechnersystem
DE2953861A Expired DE2953861C2 (US20020095090A1-20020718-M00002.png) 1978-11-08 1979-11-03

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE19792944419 Granted DE2944419A1 (de) 1978-11-08 1979-11-03 Digitalrechnersystem

Country Status (8)

Country Link
US (1) US4316244A (US20020095090A1-20020718-M00002.png)
JP (1) JPS55102050A (US20020095090A1-20020718-M00002.png)
AU (1) AU532100B2 (US20020095090A1-20020718-M00002.png)
CA (1) CA1134051A (US20020095090A1-20020718-M00002.png)
DE (2) DE2944419A1 (US20020095090A1-20020718-M00002.png)
FR (1) FR2443099B1 (US20020095090A1-20020718-M00002.png)
GB (1) GB2034944B (US20020095090A1-20020718-M00002.png)
NL (1) NL7907768A (US20020095090A1-20020718-M00002.png)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56152049A (en) * 1980-04-25 1981-11-25 Toshiba Corp Microprogram control system
US4467417A (en) * 1981-09-16 1984-08-21 Honeywell Information Systems Inc. Flexible logic transfer and instruction decoding system
WO1985000453A1 (en) * 1983-07-11 1985-01-31 Prime Computer, Inc. Data processing system
US4622630A (en) * 1983-10-28 1986-11-11 Data General Corporation Data processing system having unique bus control protocol
US4764896A (en) * 1985-07-01 1988-08-16 Honeywell Inc. Microprocessor assisted memory to memory move apparatus
US5179716A (en) * 1986-07-02 1993-01-12 Advanced Micro Devices, Inc. Programmable expandable controller with flexible I/O
ES2022246B3 (es) * 1986-09-26 1991-12-01 Siemens Ag Dispositivo de carga de avance para la preparacion microprogramada y cubierta de mandos de maquina en un procesador.
US4980850A (en) * 1987-05-14 1990-12-25 Digital Equipment Corporation Automatic sizing memory system with multiplexed configuration signals at memory modules
EP0338317B1 (en) * 1988-04-20 1996-01-10 Sanyo Electric Co., Ltd. Information processor operative both in direct mapping and in bank mapping and the method of switching the mapping schemes
CA2011518C (en) * 1989-04-25 1993-04-20 Ronald N. Fortino Distributed cache dram chip and control method
US5369749A (en) * 1989-05-17 1994-11-29 Ibm Corporation Method and apparatus for the direct transfer of information between application programs running on distinct processors without utilizing the services of one or both operating systems
US5369767A (en) * 1989-05-17 1994-11-29 International Business Machines Corp. Servicing interrupt requests in a data processing system without using the services of an operating system
US5155809A (en) * 1989-05-17 1992-10-13 International Business Machines Corp. Uncoupling a central processing unit from its associated hardware for interaction with data handling apparatus alien to the operating system controlling said unit and hardware
US5283868A (en) * 1989-05-17 1994-02-01 International Business Machines Corp. Providing additional system characteristics to a data processing system through operations of an application program, transparently to the operating system
US5144692A (en) * 1989-05-17 1992-09-01 International Business Machines Corporation System for controlling access by first system to portion of main memory dedicated exclusively to second system to facilitate input/output processing via first system
US5325517A (en) * 1989-05-17 1994-06-28 International Business Machines Corporation Fault tolerant data processing system
US5113522A (en) * 1989-05-17 1992-05-12 International Business Machines Corporation Data processing system with system resource management for itself and for an associated alien processor
AU644141B2 (en) * 1990-01-05 1993-12-02 Maspar Computer Corporation A method of controlling a router circuit
CA2073185A1 (en) * 1990-01-05 1991-07-06 Won S. Kim Parallel processor memory system
US5313590A (en) * 1990-01-05 1994-05-17 Maspar Computer Corporation System having fixedly priorized and grouped by positions I/O lines for interconnecting router elements in plurality of stages within parrallel computer
US5280474A (en) * 1990-01-05 1994-01-18 Maspar Computer Corporation Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays
US5301299A (en) * 1990-06-07 1994-04-05 Intel Corporation Optimized write protocol for memory accesses utilizing row and column strobes
KR100295074B1 (ko) * 1992-12-22 2001-09-17 리패치 응용주문형집적회로인에러정정코드메모리제어기
DE19983015B4 (de) * 1999-01-25 2006-02-23 Mitsubishi Denki K.K. Peripherievorrichtung zum Überprüfen eines Ablaufprogramms für eine programmierbare Steuereinrichtung
EP1643658A1 (en) 2004-10-04 2006-04-05 Sony Deutschland GmbH Power line communication method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1935390B2 (de) * 1968-07-15 1977-01-20 International Business Machines Corp., Armonk, N.Y. (V.StA.) Integrierter halbleiterspeicher
US4048623A (en) * 1974-09-25 1977-09-13 Data General Corporation Data processing system

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1935390U (de) 1965-12-06 1966-03-24 Huelsta Moebelwerk Alois Huels Scharnier fuer moebeltueren.
US3764988A (en) * 1971-03-01 1973-10-09 Hitachi Ltd Instruction processing device using advanced control system
US3736566A (en) * 1971-08-18 1973-05-29 Ibm Central processing unit with hardware controlled checkpoint and retry facilities
FR2226079A5 (US20020095090A1-20020718-M00002.png) * 1973-04-13 1974-11-08 Honeywell Bull Soc Ind
US3810110A (en) * 1973-05-01 1974-05-07 Digital Equipment Corp Computer system overlap of memory operation
US3900836A (en) * 1973-11-30 1975-08-19 Ibm Interleaved memory control signal handling apparatus using pipelining techniques
JPS50128948A (US20020095090A1-20020718-M00002.png) * 1974-03-29 1975-10-11
US4024508A (en) * 1975-06-19 1977-05-17 Honeywell Information Systems, Inc. Database instruction find serial
DE2537787A1 (de) 1975-08-25 1977-03-03 Computer Ges Konstanz Modularer arbeitsspeicher fuer eine datenverarbeitungsanlage und verfahren zum durchfuehren von speicherzugriffen an diesem speicher
US4045781A (en) * 1976-02-13 1977-08-30 Digital Equipment Corporation Memory module with selectable byte addressing for digital data processing system
US4156925A (en) * 1976-04-30 1979-05-29 International Business Machines Corporation Overlapped and interleaved control store with address modifiers
US4095265A (en) * 1976-06-07 1978-06-13 International Business Machines Corporation Memory control structure for a pipelined mini-processor system
US4079455A (en) * 1976-12-13 1978-03-14 Rca Corporation Microprocessor architecture
DE2704560C2 (de) * 1977-02-03 1979-01-18 Siemens Ag, 1000 Berlin Und 8000 Muenchen Datenverarbeitende Anlage mit paralleler Bereitstellung und Ausführung von Maschinenbefehlen
US4122359A (en) * 1977-04-27 1978-10-24 Honeywell Inc. Memory protection arrangement
US4130899A (en) * 1977-11-25 1978-12-19 Ncr Corporation System for operating volatile memory in normal and standby modes
US4189767A (en) * 1978-06-05 1980-02-19 Bell Telephone Laboratories, Incorporated Accessing arrangement for interleaved modular memories

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1935390B2 (de) * 1968-07-15 1977-01-20 International Business Machines Corp., Armonk, N.Y. (V.StA.) Integrierter halbleiterspeicher
US4048623A (en) * 1974-09-25 1977-09-13 Data General Corporation Data processing system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
DE-Z.: Elektron-Rechenanlagen, 1970, H. 2, S. 95-103 *

Also Published As

Publication number Publication date
JPS55102050A (en) 1980-08-04
US4316244A (en) 1982-02-16
DE2944419A1 (de) 1980-05-14
DE2953861C2 (US20020095090A1-20020718-M00002.png) 1989-01-26
FR2443099B1 (fr) 1988-03-25
CA1134051A (en) 1982-10-19
GB2034944B (en) 1982-12-22
NL7907768A (nl) 1980-05-12
FR2443099A1 (fr) 1980-06-27
DE2944419C2 (US20020095090A1-20020718-M00002.png) 1988-08-18
AU5222879A (en) 1980-05-15
AU532100B2 (en) 1983-09-15
GB2034944A (en) 1980-06-11

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