DE2933335A1 - CIRCUIT ARRANGEMENT FOR CONVERTING THE FREQUENCY OF ANALOG AC VOLTAGES OF A ENCODER INTO SPEED VALUES OF BINARY DISPLAY - Google Patents

Description

Wabco Fahrzeugbremsen GmbH Hanover, August 10, 1979

WP 41/79 - Dr. König circuit arrangement for converting the frequency of analog alternating voltages of a rotary encoder in speed values in binary representation.

The invention relates to a circuit arrangement for converting the frequency of analog AC voltages of a Encoder in speed values binary representation.

It is known to count counting pulses falling in the period of the rotary encoder in order to obtain speed values in binary representation. The percentage The pitch error of the encoder gear determines the minimum speed error or the error of the period duration value. Disturbances can only be retrospectively with great Effort can be eliminated.

It is also known to generate voltages in binary representation from analog voltages indirectly via analog / digital converters to win.

The disadvantage of both known methods is that additional circuitry is always necessary for extraction of the desired binary data words.

The object of the present invention is therefore to provide a circuit arrangement with which the Frequency of the alternating voltage of the encoder directly

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can be converted into binary speed values «.

This task of the invention requires oils in. Characteristics of claim 1 specified haiinahmen lot.

The advantages of the solution according to the invention can be seen in particular in the fact that the digital Ge * -

practically

Speed data words are dependent on manufacturing tolerances of the pole wheel of the encoder system. The circuit arrangement according to the invention is relatively insensitive to interference. The information frequency is poured, so that with the Circuit arrangement according to the invention a high resolution can be achieved.

Further developments which are advantageous and expedient for solving the problem are characterized in the subclaims. The invention is to be explained in more detail below, reference being made additionally to the accompanying drawing shall be.

In the drawing, FIG. 1 shows a block diagram of the circuit arrangement according to the invention and FIG. 2 shows a flow chart of the program flow in the computer.

The invention was based on the idea of the mode of operation of an analog frequency voltage converter known per se, which converts the frequency of the encoder signals proportionally into a voltage value proportional to the speed, to be digitally reproduced in such a way that from the encoder signal frequency speed data words can be obtained directly in binary representation.

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As is well known, in the case of the analog frequency, voltage s, conversion is a capacitor in the periodic interval < d ~ ._ Γ-x-transmitter alternating voltage over a defined kui. “Jö Zi. Ii, charged with a constant current and discharged in the intervening period. Charging is therefore carried out proportionally to the current strength and time by constant amounts. As is known, the discharge takes place according to an exponential function. The addition is equivalent to the charging and the subtraction to the discharging. The output voltage of the frequency converter is a measure of the rotational speed scanned by the rotary encoder.

The invention now proposes to use a computer in place of the frequency-to-voltage converter, as it were this can be taken from the basic circuit diagram of FIG. The computer has the task of charging and discharging perform the appropriate additions or subtractions of the capacitor.

The step-by-step charging of a capacitor with a constant current I over a short, defined period of time A t can be described by the equation

AV = £ I Δί,

where V is the potential of the capacitor and C is the capacitance of the capacitor.

Since C, I and Δ t are assumed to be constant, ΔV is also constant.

1 30013/0205

ORIGINAL INSPECTED

This increase in potential by the amount of & V takes place as a function of the frequency of the encoder signals, which means that the increase in t'-ji.euLiaL · -.miso happens more frequently, the higher the frequency.

The discharge of the capacitor between the charging processes can be described by the equation

v = v _o . _e ~ ^{t / c>}

where V is the initial potential, V is the potential still present at time t and X is the time constant of the exponential function.

The speed of discharge dV = ^ J. * V is that

dt Γ instantaneous value of potential V directly proportional.

_{This results in a potential V 1} after the (n + 1) th period of the sensor signals has passed

^V n ₊ 1

"K

At a constant sensor signal frequency, the values V * lie in a value range, the bandwidth of which is determined by ^ V. The potential V is a direct measure of the rotational speed v given by the frequency of the encoder signals.

The potential V can now be replaced by a binary data word Z, the increase of which has to be done ^{by adding a data word ΔZ and decreasing it by subtracting a data word ΔΖ 1.}

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ORIGINAL INSPECTED

As described for the complete digital replica of the response ^above: "i CQU _5> - .. s ^ ,? aniiu liinrosa must also digitize Entladungenorgang be done in the present case in that gradually as long as data words Δ Z are subtracted from ^1, up through the occurrence of a. new sensor signal the subtraction is briefly interrupted by adding the data word Δ Ζ.

Starting from an initial data word Z ^, the new data word Z ₁ results after the first subtraction step after the occurrence of a sensor signal

and after the η-th subtraction to

Reference should now be made to FIGS. 1 and 2.

Fig. 1 shows a rotary encoder 2, which generates an alternating voltage, the frequency of which corresponds to the scanned rotational speed is proportional. A pulse shaper 4 is connected to the sensor 2, which as a function of the period the sensor signals generate pulses that are fed to a computer and activate this computer.

The computer runs - controlled by the impulses - a program for converting the frequency of the sensor signals; i ~

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ORIGINAL INSPECTED

Speed information in binary Po πα through, üa *. at the output of the computer ~> s eL-sfb -iini-.odi :; bii-.Mv; Gv.? ^ 1- "Li -? - :;. Keitsdatenwort can now be fed to a block-protected Fanrzfjagbrer.iScu'lcMjp · for example.

The Procjivimm i sv hI carried out by the computer? The flow diagram shown in FIG. 2.

Each sensor pulse causes the he> · hat i: correspond to three the above explanations for jewel i rf vorh- ■■ · - '■ * ■ <η speed data word Z is a constant'_r:; iwi · digkei ts-value corresponding Geschwind! ! gkeitsdatenwf > \ t ^ Z to be added.

A fraction AZ * - -Q- · Z is formed from the data word Z present in each case and in the next calculation step

subtracted from the data word Z + Δ Z. The fraction Λ Z ¹ er-η "

is obtained from the time constant X of the specified exponential function and the computation time Δ t (computer cycle time).

After the output of the resulting data word Z _{n + 1} = Z _n + / JZ - Δ Z ' with Δ Z' = t / r · Z _n follows a new computing cycle, with cyclical subtraction and with the program step / through which the addition of the constant speed data word Δ Z takes place until a new sensor pulse occurs. The addition program is only activated by a sensor pulse.

It is advisable to do this before outputting the speed data word to carry out another filtering, · 3- ■

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BATH ORIGINAL

COPY

can be based on the maximum accelerations in order to eliminate disturbance variables *

With a constant sensor frequency, the speed data words move in a data area, the bandwidth of which is determined by the value after each sensor pulse is added to the existing data word Z, namely by the value ^ Z. The bandwidth is for the The entire speed range remains constant as long as there is no division into individual speed ranges.

The constant data word to be added / \ Z results from the consideration that with a constant sensor frequency the addition component £ Z and the subtraction component over the respective period interval T must be the same.

Starting from a data word Z, the times t result. and t ^ with t = t .. + T for the data words Z ₁ and Z_ values of

^Z 1 ^{= Z} o * ^e " ^{ti / r and Z} 2 ^{= Z} o ' ^e ~ ^{tl / €} ' It is Δ Z = Z ₁ - Z ₂ = Z _o (e ~ ^t '\ ^ ^r - _e " ^t 2 ^ ^T ) or approximated

. _z

where T is the sensor signal period at the maximum Ge speed is.

Finally, a numerical example with realistic prerequisites should be given.

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ORIGINAL INSPECTED COPY

-1ο-

-1ο-

Requirements :

1.) Maximum wheel speed V. - ■■ 1 km / h = 8.4 Hz. From this eco:,:. ι period ¹ p. _n = o, 794 · 1o ~ ε ξ

2.) For θ = 5s GeF

z \ x '^ t addi g st = r' ■. ■ ·. . · R

ler: ■ - .: ·! I 4.

3.)) ie ¹ V: jhen '-Iu' ·. _: , 4,) The - ■ '· tko t.it.i et - E r

let - - 2o 1o κ * ™.

Av.s den tigen a ten = 1: ^ ε. ·. :> \ ': -:!: -: ■■■ - 1,) Add ν cnsaiteil ^ Z,. c P ■><. ·. ™ c : r? Vpa. ■:

Z = 15o x 437 x c, 79 4 _. J ^ Cl =; -,, f 2o · 1c " ³

2 ) The subtraction anti; i ">/;. ^r 'j viecht e ' - ' ie per computing cycle 3 7t; ic t · - ■ -jlfct ^ t. ^1. c * · ^Z 1 ^{= Z} m * *

κι . ' α

" st d < i Aus <j; .l a> .ii.tt-: n '< . ■■ ■ jederr Sabtiakticn: t cbr.i \ τ ■■ rbalhsr- ν. .-». it?

3.) The Z, .hl M ler Suit:.: Ε: t '' τ ι ν ¹ ^ is

/ Γ »

13J0013 / 0205

BATH ORIGINAL

COPY

Claims (5)

Wabco Pahrzeugbreiaaen GmbH Hanover, August 10, 1979 WP 41/79 - Dr. King Claims 1. Circuit arrangement for converting the frequency of analog alternating voltages of a rotary encoder into speed values binary representation, characterized in that depending on the period or sub-periods of the alternating voltage of the rotary encoder (2) in a pulse converter connected to the rotary encoder (4) trigger pulses for activating a Computer (6) are generated, which processes a predetermined program of work steps for converting the pulse frequency into binary speed data words. 2. Circuit arrangement according to claim 1, characterized in that a program counter is set to an initial address by the trigger pulses, which is assigned to an addition program for adding a predetermined constant speed data word Δ ^{z to} the respective existing, loaded into a memory speed data word Z _n that the Program counter then to one Dr.K./H. -2- 130013/0205 Address advances, which a subtraction program for subtracting a fraction L'L 'of the respective existing speed data word Z from the speed At Keitsdatenwort Z + Δ Z is assigned and that the program counter switches cyclically to the address for the subtraction program until the occurrence of the next trigger pulse. 3. Circuit arrangement according to claim 1 or 2, characterized in that filtering of the speed data word is carried out in the program cycle after the processing of the subtraction program. 4. Circuit arrangement according to claim 2, characterized in that the subtraction program is processed in steps controlled by the computing time (cycle time) of the computer (6). 5. Circuit arrangement according to claim 2, characterized in that the factor 1 / F is a constant which is determined by the time constant Γ of a predetermined exponential function and the computing time (program cycle time) ^ t of the computer and is determined as ^ Z '= Z · ί t / Γ # • β * "3 · 130013/0205 ORIGINAL INSPECTED