DE2407968C2 - Digital voltage level meter - Google Patents

Description

The invention relates to a digital voltage level meter with a capacitive feedback Amplifier, the output voltage of which depends on a voltage to be measured Value is brought, and the output voltage after switching off the voltage to be measured is fed back to the amplifier input, the time span from the beginning of the feedback phase until a given voltage value is reached by the exponentially changing Output voltage is measured digitally.

In a known voltage level meter of this type (German Auslegeschrift 1 271257), the output voltage of the amplifier brought to a value that depends on the voltage to be measured, that initially in a first Meiiphase a capacitor connected upstream of the amplifier input this voltage is charged and the thus stored charge in a second measuring phase on the Feedback capacitor is transmitted. The feedback phase then closes as the third Measurement phase. This provides an instantaneous value to be measured that occurs during the first measuring phase The evaluation is based on tension. However, this can be caused by superimposed interference voltage components be falsified, which leads to incorrect measurements.

The invention is based on the object of providing a voltage level meter of the type mentioned at the beginning /. to be used to measure the level of the input voltage integrated over a specified period of time, H. thus a logarithmic evaluation of the ratio of the integrated input voltage to a specified reference voltage. This is achieved according to the invention in that the voltage to be measured via an input switch during a fixed period of time to the Amplifier input is applied so that the amplifier serves as an integrator and the feedback Output voltage represents the integration result achieved after the time span has elapsed.

_The advantage achieved with the invention consists mainly in the C opening time of the gate circuit 8

special in that the integration of the input counting pulses are counted. The number result will be

nnung with the help of the already for the logarithmic then in a display device 11 digital dai -

ίΡ v.rtiini? the input voltage or via an output 12 in the form of

Q. altungsteiie uurchiuninai is, Mi uaL> üei rtuiwaiiu ₅ preferably Koaierien uignaicn rsigi.uv .. - _c ^

rr pin's own integrator is no longer necessary. Furthermore can give.

Snannurlgspegelinesser ^{according to the invention by the crslc Pliase of the} actual measuring process

^α ^ ^Γ only a slight change in its circuit starts after a previous discharge of the integra-

• Separate measurement of the input voltage at the capacitance Cl by briefly closing the

c U- of the input level can be used. OK switch Λ4. After Cl is discharged, the

The integrating voltage measurement voltage Uc takes place, which is integrated and with regard to its level

i, \ _P m known principle of double ink compared to a given reference value, the β £ ^ ^^ ^ ^^ closing the switch S \

^g remäß a preferred development of ER to the inverting input of the Operations' he _{n 1} T r V O is placed rückzukoppelnde the output voltage 15 stävkers. 1 The resulting Aulwarts-ln-κΐ-rn does not match the integration result of Ue. the output voltage corresponding to a linear increase in the reference voltage value - Ua of the integrator \ £ ™ *} · '* ^auI !

nSanges building up output voltage only after its expiry .Sl opens again. "Ic on Inte,! Rub polarity as the voltage to be measured, 20 vallende output voltage reached then provides uas heirn exceeding the reference voltage with entge- integration result. The lur the expanded evaluation"! _Neeb et7ter polarity feedback and the time processing for Available.

SLum reaching the reference voltage from Fig. 2 shows in a diagram ..as deiVeriau

Essen This ensures that the logarithmic of - Ua over time represents 1, zi.to e, η η

^g Trhe evaluation of the ratio of the integrated a ₅ during an upward integration within the

nteErfincLg will subsequently find one in voltage at 1 - Uo not. In the case of the drawing, the preferred embodiment shown in FIG. 3 shows that the linear upward integration has a value

mosbeispiels next described. It shows - UaI results, which is greater than the Relerenzs, a inuiife

TSTS Schematic diagram of the embodiment - -Ua J * ^^ j ^ $ *% $. ^ ™

positive level value. , .nineither the switch S3 is closed and.

js ^^^: ^^^^ ⁴⁰ = ^fc * ^itaßj ^ ^{3 olf}

running input of an operational amplifier11 remains (H g ^ - I ^ _{f:. 2 SQ be} . leads, whose non-inverting input to ground ^B _n f ^ '^ UeMeSphase so that the is at the Auspotential and its output 2 practice. A g '"" ¹ ^ reversal level 3 emerging voltage capacitor C1 is connected to the inverting input output 6 cr ^ ^h _ ^r ^ _m , _lorausgBng 2 I. When a switch is closed, Cl becomes + U * J ^IC J ¹ ^ ° _{Pre7eichen unlC r} differentiates and thus S4 is short-circuited. In this circuit, d glfj ^d ^, ^c f ^; _{au (white like the} input spand oation amplifier 1 e an active integrator ^^ J ^ ß S3 f dn invert-

S4 short-circuited in each case. In di g fj ^ f ^; _{au (white} gg

the operational amplifier 1 e.nen active integrator ^^ J ^ were called from S3 to the inverting

thusClalsintegration capacity. The output 2 voltage Lt. ^^, _{rs γ rüi: kgpk is} oppelt

of the integrator is approaching via a resistance «3 an dt η ₅ o J" ^ | _{influB d} ^ _{cr feedback}

Input of a polarity reversing stage 3 switched, υni _ _{li (I in} a second

which are fed back via a resistor J4. An Jj ^^^^ nd of - Ua \. the value

on the other hand, the output 2 with the first input wans 1 is not a ο. _b ^ ^ ^^

a comparator 4 connected whose second input d uRc ^^^ J _T1 . _Fig . 2 reveals

gang panne via the closed switch .S6 ml of a ₅₅ ^ ^'1 J ¹ J _{"St. Diesc ZcitS} falling Kurvenab-

Connect reference voltage source S «, st. de the Re- ncn that uu_m ^^. 1 ^ _{Zeitabli: ingigkeit on}

reference voltage - Uo generated _wcisl n _a s end of 77 is made by the comparator

The inverting input of the operation is astonishing in the softness of its input voltage.

kers 1 can after its activation by Uc ^{Wahl- lcs} ^ \! ; _{wdtcs comparator} signal Kl emits Da wise via a switch .S2 and a resistor 60 - ■ ungcn ^ - »closing the switch

«2 with the output 2 of 1 or via a shell e, Je Ig» ^ a _t ^ _d ^ ^ _mm ^

S3 and the resistor R2 mil the output 6 of the ^ -inu P _{cnts> p} i _cht the opening time of the

Polarity reverser 3 are connected. De. vo. ^ ™ Period of time Tl. The result of the

The output of the comparator * 4 is finally to a 1 «^ do _t jd ^ P counting process-st then a logic circuit? led, the emc lorscha ung8 6 ₅ h ^ major 8 _{n ww min dic Re} lercnz-

controls by means of their output signals. Here de ™ ^ _{d ß sjc acts on the linegrall} "nsc. -

Gate circuit 8 with a counting pulse generator 9 and ^ ™ f,, ^ corresponds! To the Em

oinpin counter 10 together in such a way that the respective object doesn t

5 ^J 6

should avoid stress levels in relative terms, then the charge of the gray capacity at C 1 is then the

Counting result in counter 10 at the same time as the value switching of the input voltage Uc during the

of the predetermined time interval Π measured integrated over the time interval 71 and finally after

Finiianiisspannunuspecels proportional. The switch-off receives the connection of + Ua

tenon Fegehvert is a negative Vor / eichen / u / uord- 5 over S3 or from - Ua over 52 as well as the simultaneous

new the / weckförmcrwl-iso in the display

tune 11 is displayed with. The causes for the desired gate circuit 8. This Schaldsequence can

Peeelangabc necessary logarithmic closures - for the purpose of carrying out integrated

The measurement result also results from the converted measurements of the input voltage level

• / .line of the integration progression - UaI in the digital «repeat. It is particularly recommended that the

time to be measured Π by means of the exponen- Schalllei .Vl to 54 to be trained as an electronic switch

tial curves course 14. den.

If the case shown in FIG. 3 is | Ual \> \ Uo \ According to a preferred development of the hrlin-

before, the second measuring phase begins with the fact that after the dung the sounding can be carried out in a simple manner

the opening of 51 is now modified on the integrator so that it can be used as an

output from 1 is fed back. The polarity reversal switch 56 from the input of the comparator 4 to the integrator input leads to an ab- ao and via a switch 55 which, instead of the downward integration, the switches 52 and 53, which remain open in FIG with exponential time dependency \ eran sen, in the / wide measuring phase at which inverting is evident. The time span in which the output led to the input of the integrator 1. The from - Uo voltage -Ua. based on the value - Ua _:. The enabled input of the comparator 4 is finally the value of the reference voltage - Uo 15 reaches beyond a switch 56 which is closed when the switch 56 is open, is again denoted by TL , through which the up switch 57 is assigned ground potential. Switching on the second comparator signal Kl limited by - Uo to the integrator input causes a downward integration, which is evaluated when the mass counter 10 is reached, in the manner already described by means of read downward integration. The counter output potential obtained is provided by the output voltage - Ua of the input, which is again proportional to the input level which is tegrator 1 to the predetermined reference value 30, ie when the comparator is relative. must be in gnals K2. is interrupted. The time span from this case a positive sign is assigned to the closing of the switch 55 to the occurrence of K2 den, which is then preferably displayed in the display device 11 as a measure for the input voltage Uc. ^{un (} l is determined by means of circuit parts 8, 9. 10 and 11

Conveniently, the counter 10 may additionally evaluated in the manner described above _35th Even a timer can be used, which can understand the specified function of the switch time interval 71 for the upward integration of Uc 55 to 57 as well as the switching of the level measurement. For this purpose the logic circuit 7 are sung to the voltage measurement and vice versa rnitgleichzeitig with the switching command for closing by means of the tapped off at 15 outputs the Lo-51 a, the gate circuit 8 openable gate pulse Ti _'40 gikschaltung 7 automatically and in particular after starting. which triggers a counting process in 10. To be controlled according to a given program. The switches 55 to 57 are also preferably output as 10 a signal E, which is formed in the logic circuit electronic switch, device 7 a switching command to open the switch. The measuring circuit according to the invention is tnsbcson-

51 triggers. 45 f ^for measurements of noise level of a particular post-

The logic circuit 7 can, with particular advantage, be used with the directional transmission system or its parts as an automatic sequence control-designed advantage. Here, also the achievable with the turned lems, the called abgege- with their via the outputs 15 of the invention surrounded switching commands for either the individual switch 51 voltage measurement in place of a level defines a switching sequence to 54, the first of the _decision-50 measurement of particular Interest.

1 sheet of drawings

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Claims (7)

Claims: 24,968 1. Digital voltage level meter with a capacitive feedback amplifier, the S output voltage of which is brought to a value dependent on a voltage to be measured, and in which the output voltage is fed back to the amplifier input after the voltage to be measured is switched off, with the »° time period from the beginning the feedback phase is measured digitally by the exponentially changing output voltage until a predetermined voltage is reached, characterized in that the voltage to be measured ( Ue ) is applied to the amplifier input via an input switch (51) for a fixed time span (Tl), so that the amplifier (1) simultaneously serves as an integrator and the output voltage to be fed back (- UaI, »° - Ua2) represents the integration result achieved after the time span (71) has elapsed. 2. Digital voltage level meter according to claim 1, characterized in that the output voltage to be fed back (- UaI, - UaI) when a reference voltage (- Uo) corresponding to the integration result for a reference voltage value is not reached due to the output voltage (- Ua) with the same polarity as the voltage to be measured ( Ue), which is built up during the integration process, when the reference voltage (- Uo) is exceeded with opposite polarity, is fed back and that the time span (72 ) is measured until the reference voltage (- Uo) is reached. 3. Digital voltage level meter according to claim 2, characterized by a polarity reversal stage (3) and a comparator (4) connected to a reference voltage (- Uo). each of which are connected downstream of the integrator (1) by a group of switching means (52, 53) which, depending on the occurrence or absence of a signal when the reference voltage (- Uo) is reached, by the integrator output voltage (- Ua) during the time interval (71 ) formed, first comparator signal (Kl) the output voltage of the integrator (1) or the inverter (3) switch through as a feedback voltage and further switching means (8) that a preferably digital timer (9, 10, 11) from this through-connection until the occurrence of a during the feedback phase formed in an analogous manner, switch effective second comparator signals (Kl). 4. Digital voltage level meter according to claim 3, characterized in that the time interval (71) predetermined for the integration of the input voltage (Ue ) is derived from the timer (9, 10, 11). 5. Digital voltage level meter according to one of claims 1 to 4, characterized by a sequence controller (7), the output signals of which initially via the input switch (Sl) the connection of the input voltage ( Ue) for the duration of the predetermined time interval (71) and then the connection of the respective feedback voltage (+ Ua, - Ua) and the activation of the timer (9th lü, H) automatically and preferably in repetitive measuring cycles. 6. Digital voltage level meter according to one of the claims! to 5, characterized in that for optional integrating measurement of the input voltage (Ue) instead of the input level, the reference voltage (- Uo) can be switched off from the input of the comparator (4) and fed to the integrator input instead of the feedback voltage (+ Ua. ~ Ua) and that the comparator input switched from the reference voltage (- Uo) f 1 is connected to ground potential. 7. Digital voltage level meter according to one of claims 3 to 6, characterized in that the feedback voltage (- Ua, + Ua) through- switching group of switching means (52, 53), the connection of the input voltage ( Ue) causing the input switch (51) and if necessary, the switches (55, 56, 57) causing the switchover to the integrating input voltage measurement are designed as electronic switches.