DE2931121C2 - - Google Patents

Info

Publication number
DE2931121C2
DE2931121C2 DE19792931121 DE2931121A DE2931121C2 DE 2931121 C2 DE2931121 C2 DE 2931121C2 DE 19792931121 DE19792931121 DE 19792931121 DE 2931121 A DE2931121 A DE 2931121A DE 2931121 C2 DE2931121 C2 DE 2931121C2
Authority
DE
Germany
Prior art keywords
gate
input
output
inverter
digital processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE19792931121
Other languages
German (de)
English (en)
Other versions
DE2931121A1 (de
Inventor
William Clayton Austin Tex. Us Bruce
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE2931121A1 publication Critical patent/DE2931121A1/de
Application granted granted Critical
Publication of DE2931121C2 publication Critical patent/DE2931121C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30079—Pipeline control instructions, e.g. multicycle NOP
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
DE19792931121 1978-07-31 1979-07-31 Verfahren zur durchfuehrung einer loesch- und warte-instruktion fuer einen digital-prozessor Granted DE2931121A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US92962978A 1978-07-31 1978-07-31

Publications (2)

Publication Number Publication Date
DE2931121A1 DE2931121A1 (de) 1980-02-21
DE2931121C2 true DE2931121C2 (enrdf_load_stackoverflow) 1988-09-01

Family

ID=25458184

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19792931121 Granted DE2931121A1 (de) 1978-07-31 1979-07-31 Verfahren zur durchfuehrung einer loesch- und warte-instruktion fuer einen digital-prozessor

Country Status (6)

Country Link
JP (1) JPS5523598A (enrdf_load_stackoverflow)
DE (1) DE2931121A1 (enrdf_load_stackoverflow)
FR (1) FR2432737A1 (enrdf_load_stackoverflow)
GB (1) GB2027238B (enrdf_load_stackoverflow)
MY (1) MY8500477A (enrdf_load_stackoverflow)
SG (1) SG16584G (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1217310A (en) * 1981-09-14 1987-02-03 George B. Park Heat recoverable article
JP2602198B2 (ja) * 1984-10-15 1997-04-23 三井東圧化学株式会社 ポリイミド樹脂粉末からなる耐熱性接着剤
JP2596536B2 (ja) * 1984-10-15 1997-04-02 三井東圧化学株式会社 ポリイミド樹脂粉末からなる耐熱性接着剤
GB2506169A (en) * 2012-09-24 2014-03-26 Imagination Tech Ltd Limiting task context restore if a flag indicates task processing is disabled

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3970998A (en) * 1974-10-15 1976-07-20 Rca Corporation Microprocessor architecture
US4003028A (en) * 1974-10-30 1977-01-11 Motorola, Inc. Interrupt circuitry for microprocessor chip

Also Published As

Publication number Publication date
JPS5523598A (en) 1980-02-20
FR2432737A1 (fr) 1980-02-29
GB2027238A (en) 1980-02-13
GB2027238B (en) 1982-12-01
MY8500477A (en) 1985-12-31
JPS6313213B2 (enrdf_load_stackoverflow) 1988-03-24
FR2432737B1 (enrdf_load_stackoverflow) 1984-02-10
DE2931121A1 (de) 1980-02-21
SG16584G (en) 1985-03-08

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition