DE2902488A1 - Elektronische schaltung zur durchfuehrung der addition von dualzahlen - Google Patents

Elektronische schaltung zur durchfuehrung der addition von dualzahlen

Info

Publication number
DE2902488A1
DE2902488A1 DE19792902488 DE2902488A DE2902488A1 DE 2902488 A1 DE2902488 A1 DE 2902488A1 DE 19792902488 DE19792902488 DE 19792902488 DE 2902488 A DE2902488 A DE 2902488A DE 2902488 A1 DE2902488 A1 DE 2902488A1
Authority
DE
Germany
Prior art keywords
low
deep
gate
output
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19792902488
Other languages
German (de)
English (en)
Other versions
DE2902488C2 (sv
Inventor
Josef Hoelzle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19792902488 priority Critical patent/DE2902488A1/de
Publication of DE2902488A1 publication Critical patent/DE2902488A1/de
Application granted granted Critical
Publication of DE2902488C2 publication Critical patent/DE2902488C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3852—Calculation with most significant digit first
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/481—Counters performing arithmetic operations

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
DE19792902488 1979-01-23 1979-01-23 Elektronische schaltung zur durchfuehrung der addition von dualzahlen Granted DE2902488A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19792902488 DE2902488A1 (de) 1979-01-23 1979-01-23 Elektronische schaltung zur durchfuehrung der addition von dualzahlen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19792902488 DE2902488A1 (de) 1979-01-23 1979-01-23 Elektronische schaltung zur durchfuehrung der addition von dualzahlen

Publications (2)

Publication Number Publication Date
DE2902488A1 true DE2902488A1 (de) 1980-07-31
DE2902488C2 DE2902488C2 (sv) 1988-12-29

Family

ID=6061211

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19792902488 Granted DE2902488A1 (de) 1979-01-23 1979-01-23 Elektronische schaltung zur durchfuehrung der addition von dualzahlen

Country Status (1)

Country Link
DE (1) DE2902488A1 (sv)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998011481A1 (en) * 1996-09-12 1998-03-19 Board Of Regents, The University Of Texas System Fast n-bit by n-bit multipliers using 4-bit by 4-bit multipliers and cascaded adders

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DE-B.: Schecher, "Funktioneller Aufbau digitaler Rechenanlagen", Springer 1973, S. 29-33 *
IBM Techn. Discl. Bull., Vol. 17, Nr. 1, June 1974, S. 118-119 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998011481A1 (en) * 1996-09-12 1998-03-19 Board Of Regents, The University Of Texas System Fast n-bit by n-bit multipliers using 4-bit by 4-bit multipliers and cascaded adders
US5912832A (en) * 1996-09-12 1999-06-15 Board Of Regents, The University Of Texas System Fast n-bit by n-bit multipliers using 4-bit by 4-bit multipliers and cascaded adders

Also Published As

Publication number Publication date
DE2902488C2 (sv) 1988-12-29

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee