DE2838982A1 - METHOD FOR PRODUCING MULTI-LAYER PCB - Google Patents

METHOD FOR PRODUCING MULTI-LAYER PCB

Info

Publication number
DE2838982A1
DE2838982A1 DE19782838982 DE2838982A DE2838982A1 DE 2838982 A1 DE2838982 A1 DE 2838982A1 DE 19782838982 DE19782838982 DE 19782838982 DE 2838982 A DE2838982 A DE 2838982A DE 2838982 A1 DE2838982 A1 DE 2838982A1
Authority
DE
Germany
Prior art keywords
conductor tracks
conductor
levels
conductor track
produced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19782838982
Other languages
German (de)
Other versions
DE2838982B2 (en
Inventor
Klaus-Peter Kreft
Siegfried Schlag
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent Deutschland AG
Original Assignee
Standard Elektrik Lorenz AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Elektrik Lorenz AG filed Critical Standard Elektrik Lorenz AG
Priority to DE19782838982 priority Critical patent/DE2838982B2/en
Priority to GB7929756A priority patent/GB2030781B/en
Priority to SE7907298A priority patent/SE7907298L/en
Priority to NL7906603A priority patent/NL7906603A/en
Priority to FR7922427A priority patent/FR2447131A1/en
Priority to BE2/58053A priority patent/BE878645A/en
Priority to ES483975A priority patent/ES483975A1/en
Publication of DE2838982A1 publication Critical patent/DE2838982A1/en
Priority to BE2/58599A priority patent/BE883783R/en
Publication of DE2838982B2 publication Critical patent/DE2838982B2/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0133—Elastomeric or compliant polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

S. Schlag - K.-P. Kreft 6-2S. Schlag - K.-P. Kreft 6-2

Verfahren zum Herstellen von Mehrebenen-Leiterplatten.Method of manufacturing multilevel printed circuit boards.

Verfahren zum Herstellen von Mehrebenen-Leiterplatten mit zwei oder mehr Leiterbahnebenen und Verbindungen zwischen Leiterbahnen verschiedener Leiterbahnebenen, bei welchem zunächst auf der Oberfläche eines Basismaterial's die Leiterbahnen der ersten bzw. ersten bei den Ebenen erzeugt werden, sodann die mit Leiterbahnen versehene(n) Ebene(n) mit einer Isolierschicht abgedeckt und anschließend die dem gewünschten Leiterbahnmuster der nächsten Ebene entsprechenden Leiterzu^e hergestellt werden, wobei Leiterzüge und Verbindungen zwÄshen Leiterzügen gleichzeitig erzeugt werden.Method of manufacturing multilevel printed circuit boards with two or more conductor track levels and connections between Conductor tracks of different conductor track levels, in which the conductor tracks are initially on the surface of a base material the first or first at the levels are generated, then the level (s) provided with conductor tracks with a Covered insulating layer and then the conductor to ^ e corresponding to the desired conductor track pattern of the next level be established, with conductor tracks and connections between Conductor trains are generated at the same time.

Ein solches Verfahren ist bekannt (DE-PS 15 40 297).Such a method is known (DE-PS 15 40 297).

Bei dem bekannten Verfahren zum Herstellen von Mehrebenen-Leiterplatten wird von einem nicht metallisierten Basismaterial ausgegangen, das an den für die Verbindung zwischen den Leiterbahnen verschiedener Leiterbahnebenen vorgesehenen Stellen gelocht ist. Danach werden durch eine stromlose Metallabscheidung die Leiterbahnen der beiden ersten Ebenen erzeugt, wobei gleichzeitig die Lochwandungen metallisiert und dadurch die Verbindungen zwischen den Leiterbahnen verschiedener Leiterbahnebenen hergestellt werden. Danach wird die derart erzeugte Leiterplatte mit einer Isolierschicht überzogen, wobei jedoch die Durchverbindung^steilen freigelassen werden. Auf dieser Isolierschicht werden anschließend ausschließlich durch stromlose Metallabscheidung Leiterbahnen der nächsten Leiterbahnebenen erzeugt. In the known method for producing multilevel printed circuit boards a non-metallized base material is assumed, which is used for the connection between the conductor tracks of different conductor track levels provided points is perforated. After that, a currentless Metal deposition produces the conductor tracks of the first two levels, with the hole walls being metallized at the same time and thereby the connections between the conductor tracks of different conductor track levels are established. After that, will the printed circuit board produced in this way is covered with an insulating layer, but the through-connection is left exposed will. Conductor tracks of the next conductor track levels are then produced on this insulating layer exclusively by electroless metal deposition.

030012/0253030012/0253

S. Schlag - K.-P. Kreft 6-2S. Schlag - K.-P. Kreft 6-2

Bei einem anderen Ausführungsbeispiel des bekannten Verfahrens sind als Verbindung zwischen den Leiterbahnen verschiedener Leiterbahnebenen keine Lochungen vorgesehen, sondern lediglich Kontaktflächen, die beim Aufbringen der Isolierschicht freigelassen werden.In another exemplary embodiment of the known method, the connection between the conductor tracks is used different conductor track levels no holes are provided, but only contact areas that are used when applying the Insulating layer can be left exposed.

Das bekannte Verfahren zur Herstellung von Mehrebenen-Leiterplatten ist noch zu aufwendig, als daß Mehrebenen-Leiterplatten - wie an sich erwünscht - in noch stärkerem Maße für viele Zwecke eingesetzt würden. Dies ist in erster Linie darauf zurückzuführen s daß das Herstellen der Leiterbahnen durch stromlose Metallabscheidung vergleichsweise teuer ist.The known method for the production of multilevel printed circuit boards is still too expensive for multilevel printed circuit boards - as is desirable per se - to be used to an even greater extent for many purposes. This is primarily due to the fact that s the production of the conductor tracks is relatively expensive by electroless metal deposition.

Außerdem weisen auch die durch stromlose Metallabscheidung hergestellten Durchverbindungen zwischen den Leiterbahnen verschiedener Leiterbahnebenen eine geringe Zuverlässigkeit, insbesondere unter Wärmebelastung, auf, weil stromlos abgeschiedenes Kupfer eine geringe Haftfestigkeit aufweist.In addition, the through connections produced by electroless metal deposition also have interconnects between the conductor tracks different conductor track levels have a low reliability, especially when exposed to heat, because it is deposited without current Copper has poor adhesive strength.

Der Erfindung liegt daher die Aufgabe zugrunde, ein Verfahren zum Herstellen von Mehrebenen-Leiterplatten anzugeben, mit dem Mehrebenen-Leiterplatten, insbesondere solche mit drei oder vier Ebenen, von guter Qualität hergestellt werden können.The invention is therefore based on the object of specifying a method for producing multilevel printed circuit boards the multilevel circuit boards, especially those with three or four levels, are made of good quality can.

Diese Aufgabe ist erfindungsgemäß dadurch gelöst, daß die Leiterbahnen der beiden ersten (inneren) Leiterbahnebenen durch Ätzen eines kupferkaschierten Basismaterials hergestellt, anschließend diese Leiterbahnebenen ganzflächig mit einerAccording to the invention, this object is achieved in that the conductor tracks of the first two (inner) conductor track planes produced by etching a copper-clad base material, then these conductor track levels over the entire surface with a

0300127025303001270253

S- Schlag - K.-P. Kreft 6-2S-stroke - K.-P. Kreft 6-2

Isolierschicht beschichtet, danach die Bohrungen hergestellt und durch Anwendung des Semi-Additiv-Verfahrens die Leiterbahnen der weiteren Leiterbahnebenen erzeugt werden.The insulating layer is coated, then the holes are made and the semi-additive process is used the conductor tracks of the other conductor track levels are generated.

Mit dem erfindungsgemäßen Verfahren lassen sich Mehrebenen-Leiterplatten herstellen, die wesentlich preiswerter und zuverlässiger sind als die mit dem bekannten Verfahren hergestellten Mehrebenen-Leiterplatten.With the method according to the invention, multilevel printed circuit boards produce that are much cheaper and more reliable than those with the known method manufactured multilevel printed circuit boards.

Nachstehend weitere Einzelheiten der Erfindung anhand eines Ausführungsbeispiels:Further details of the invention based on an exemplary embodiment are given below:

Der "Kern" der Mehrebenen-Leiterplatte besteht aus einer ein- oder zweiseitigen, geätzten Schaltung, die durch Anwendung bekannter Druck- und Ätzverfahren aus ein- bzw. zweiseitig kupferkaschiertem Basismaterial (Epoxy-Glas, Epoxy-Papier, Phenolharz-Papier) hergestellt wird.The "core" of the multilevel circuit board consists of a one or two sided, etched circuit, which by application known printing and etching processes from one or two-sided copper-clad base material (epoxy glass, epoxy paper, Phenolic resin paper).

Die Leiterbahnen des Kerns werden oxidiert, um eine ausreichende Haftung zwischen Kupfer und der nachfolgend aufzubringenden Isolierschicht zu gewährleisten.The conductor tracks of the core are oxidized to a sufficient level To ensure adhesion between copper and the insulating layer to be applied subsequently.

Danach wird die Leiterplatte durch Tauch-, Giess- oder Walzenbeschichtung bzw. Siebdruck mit einem flüssigen Kunststoff, dem sog. Haftvermittler, beschichtet. Sowohl die elektrostatische Pulverbeschichtung mit Epoxidharz als auch das Auflaminieren vorgehärteter Haftvermittlerfolien sind für diesen Zweck ebenfalls geeignet.Then the circuit board is coated with a liquid plastic by dip, pour or roller coating or screen printing. the so-called adhesion promoter, coated. Both the electrostatic powder coating with epoxy resin as well are the lamination of pre-cured adhesion promoter films also suitable for this purpose.

Die Dicke der Isolierschicht ist dabei abhängig von den zuThe thickness of the insulating layer depends on the to

- 6 030012/0253 - 6 030012/0253

- 6 S. Schlag - K.-P. Kreft 6-2- 6 S. Schlag - K.-P. Kreft 6-2

erzielenden Isolationswerten und kann von 30 um bis ca. 100 um schwanken.achieving insulation values and can range from 30 µm to approx. 100 to fluctuate.

Als Isolierschicht werden vorzugsweise die von 'der Semi-Additiv-Technik bekannten Acrylnitril-Butadien-Phenolharz-Gemische oder andere zur Anwendung der Semi-Additiv-Technik geeignete Kunststoffe verwendet.The semi-additive technology is preferably used as the insulating layer known acrylonitrile-butadiene-phenolic resin mixtures or others for the application of the semi-additive technique suitable plastics are used.

Im Anschluss an die Isolierstoff-Beschichtung wird eine Wärmebehandlung durchgeführt, um einen bestimmten Aushärtungsgrad des Isolierstoffes zu erzielen.After the insulating material coating, a Heat treatment carried out in order to achieve a certain degree of hardening of the insulating material.

Bei Verwendung einer Acrylnitril-Butadien-Phenolharz-Haftvermittlerfolie, die mit Hilfe eines sog. Hot-Roll-Laminators aufgetragen wurde, werden bevorzugt folgende Bedingungen eingehalten:When using an acrylonitrile-butadiene-phenolic resin adhesion promoter film, which was applied with the aid of a so-called hot roll laminator, the following conditions are preferred adhered to:

Temperatur: l60° C Zeit : 2 hTemperature: 160 ° C Time: 2 h

Die mit Isolierstoff beschichtete Leiterplatte wird anschließend unter Anwendung der bekannten Verfahrensschritte der Semi-Additiv-Technik weiterbearbeitet:The circuit board coated with insulating material is then made using the known process steps the semi-additive technology further processed:

Bohren bzw. Stanzen der Leiterplatte Chrom-Schwefelsäure-Behandlung der Isolierschicht Chemische Verkupferung Negativer Leiterbilddruck Galvanischer Aufbau der Leiterbahnen undDrilling or punching the circuit board Chromium-sulfuric acid treatment of the insulating layer Chemical copper plating Negative printed circuit pattern Galvanic structure of the conductor tracks and

Bohrungen aus Kupfer Entfernen des Leiterbilddruckes Ätzen des LeiterbildesBoring made of copper. Removal of the printed circuit pattern

_ γ . <5UU I i/ U&Sö_ γ. <5UU I i / U & Sö

S. Schlag - K.-P. Kreft 6-2S. Schlag - K.-P. Kreft 6-2

Weitere Verfahrensschritte, wie Aufschmelzen von Zinn/ Blei-Überzügen und/oder Drucken von Lötstopplack bzw. Isolationslack und/oder Service- bzw. Bestückungsdrucke, sind ebenfalls anwendbar.Further process steps, such as melting of tin / lead coatings and / or printing of solder mask or Insulation varnish and / or service or component prints can also be used.

Obwohl sich das Ausführungsbeispiel auf 3- bzw. 4-lagige Mehrebenen-Leiterplatten beschränkt, ist die Anwendung des Verfahrens ohne weiteres auch zur Herstellung von Mehrebenen-Leiterplatten mit mehr als 4 Leiterebenen möglich.Although the exemplary embodiment is based on 3 or 4-ply Multilevel printed circuit boards are limited, the application of the method is also readily available for the production of Multi-level circuit boards with more than 4 conductor levels possible.

2/02^32/02 ^ 3

Claims (3)

STANDARD ELEKTRIK LORENZ
AKTIENGESELLS CHAFTSTANDARD ELECTRICS LORENZ
SHARED SOCIETY StuttgartStuttgart S. Schlag - K.P. Kreft 6-2S. Schlag - K.P. Kreft 6-2 AnsprücheExpectations Verfahren zum Herstellen von Mehrebenen-Leiterplatten mit zwei oder mehr Leiterbahnebenen und Verbindungen zwischen Leiterbahnen verschiedener Leiterbahnebenen, bei welchem zunächst auf der Oberfläche eines Basismaterials die Leiterbahnen der ersten bzw. ersten beiden Ebenen erzeugt werden, sodann die mit Leiterbahnen versehenein) Ebene(n) mit einer Isolierschicht abgedeckt und anschließend die dem gewünschten Leiterbahnmuster der nächsten Ebenen entsprechenden Leiterzüge hergestellt werden, wobei Leiterzüge und Verbindungen zwischen Leiterzügen gleichzeitig erzeugt werden dadurch gekennzeichnet, daß die Leiterbahnen der beiden ersten (inneren) Leiterbahnebenen durch Ätzen eines kupferkaschierten Basismaterials hergestellt, anschließend diese Leiterbahnebenen ganzflächig mit einer Isolierschicht beschichtet, danach die Bohrungen hergestellt und durch Anwendung des Semi-Additiv-Verfahrens die Leiterbahnen der weiteren Leiterbahnebenen erzeugt werden.Method for the production of multilevel circuit boards with two or more conductor track levels and connections between conductor tracks of different conductor track levels, in which first the conductor tracks of the first or first two levels are generated on the surface of a base material, then the level (s) provided with conductor tracks with an insulating layer and then the conductor tracks corresponding to the desired conductor track pattern of the next levels are produced, with conductor tracks and connections between conductor tracks being produced simultaneously, characterized in that the conductor tracks of the first two (inner) conductor track levels are produced by etching a copper-clad base material, then these conductor track levels over the entire surface coated with an insulating layer, then the holes are made and the conductor tracks of the other conductor track levels are generated using the semi-additive process. Bö/Sara
5.9.7ÖBo / Sara
5.9.7Ö 0300127025303001270253 ORIGINAL INSPECTEDORIGINAL INSPECTED - 2 S. Schlag - K.-P. Kreft 6-2- 2 p. Blow - K.-P. Kreft 6-2 2) Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Isolierstoffschicht(en) aus flüssigem oder pulverförmigem Werkstoff durch Gießen, Tauchen oder Pulverbeschichten erzeugt werden.2) Method according to claim 1, characterized in that the insulating material layer (s) are produced from liquid or powdery material by casting, dipping or powder coating. 3) Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Isolierstoff schicht^ en) als Folie aufgebracht werden.3) Method according to claim 1, characterized in that the insulating material layers ^ s) are applied as a film. - 3 030012/0253 - 3 030012/0253
DE19782838982 1978-09-07 1978-09-07 Method of manufacturing multilevel printed circuit boards Ceased DE2838982B2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
DE19782838982 DE2838982B2 (en) 1978-09-07 1978-09-07 Method of manufacturing multilevel printed circuit boards
GB7929756A GB2030781B (en) 1978-09-07 1979-08-28 Multilayer printed circuit
SE7907298A SE7907298L (en) 1978-09-07 1979-09-03 PROCEDURE FOR MANUFACTURING PRINTED CIRCUITS WITH MULTIPLE LAYERS
NL7906603A NL7906603A (en) 1978-09-07 1979-09-04 METHOD FOR MANUFACTURING A MULTIPLE LAYERING A CARDBOARD
FR7922427A FR2447131A1 (en) 1978-09-07 1979-09-07 METHOD FOR MANUFACTURING MULTI-LAYER PRINTED CIRCUIT BOARDS
BE2/58053A BE878645A (en) 1978-09-07 1979-09-07 MANUFACTURING METHOD FOR MULTILAYER PRINTED FLOW CARDS
ES483975A ES483975A1 (en) 1978-09-07 1979-09-07 Multilayer printed circuit
BE2/58599A BE883783R (en) 1978-09-07 1980-06-12 VERVAARDIGINGSWERKWIJZE VOOR MEERLAGIGE GEDRUKTE STROOMLOOPKAARTEN

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19782838982 DE2838982B2 (en) 1978-09-07 1978-09-07 Method of manufacturing multilevel printed circuit boards

Publications (2)

Publication Number Publication Date
DE2838982A1 true DE2838982A1 (en) 1980-03-20
DE2838982B2 DE2838982B2 (en) 1980-09-18

Family

ID=6048893

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19782838982 Ceased DE2838982B2 (en) 1978-09-07 1978-09-07 Method of manufacturing multilevel printed circuit boards

Country Status (7)

Country Link
BE (1) BE878645A (en)
DE (1) DE2838982B2 (en)
ES (1) ES483975A1 (en)
FR (1) FR2447131A1 (en)
GB (1) GB2030781B (en)
NL (1) NL7906603A (en)
SE (1) SE7907298L (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3631632A1 (en) * 1985-09-29 1987-04-02 Asahi Chem Res Lab METHOD FOR CREATING ELECTRICALLY CONDUCTIVE CIRCUITS ON A BASE

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4816070A (en) * 1985-08-29 1989-03-28 Techo Instruments Investments Ltd. Use of immersion tin and alloys as a bonding medium for multilayer circuits
US4715894A (en) * 1985-08-29 1987-12-29 Techno Instruments Investments 1983 Ltd. Use of immersion tin and tin alloys as a bonding medium for multilayer circuits
SE455148B (en) * 1985-11-15 1988-06-20 Leeb Karl Erik DEVICE CONTAINING A SUBSTRATE AND DERPA APPLICATED CONDUCTING SAMPLES FOR THE PREPARATION OF SAMPLE CARDS AND PROCEDURE FOR PREPARING THE DEVICE
GB8630392D0 (en) * 1986-12-19 1987-01-28 Prestwick Circuits Ltd Producing printed circuit boards
US4804575A (en) * 1987-01-14 1989-02-14 Kollmorgen Corporation Multilayer printed wiring boards
JPH03196691A (en) * 1989-12-26 1991-08-28 Cmk Corp Formation of insulating layer of printed wiring board
DE4237611A1 (en) * 1992-11-09 1994-05-11 Lueberg Elektronik Gmbh & Co R Circuit board prodn. and circuit board - uses further layer of resin-impregnated fabric to cover conductive paths formed on composite baseboard

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB892451A (en) * 1957-12-03 1962-03-28 Radio And Allied Ind Ltd Improvements in and relating to the manufacture of printed circuits
US3349162A (en) * 1965-08-23 1967-10-24 Automatic Elect Lab Intra-connection techniques for multilayer printed wiring boards
DE1924775B2 (en) * 1969-05-14 1971-06-09 METHOD OF MANUFACTURING A CIRCUIT BOARD
GB1310880A (en) * 1969-06-13 1973-03-21 Microponent Dev Ltd Multi-layer printed circuit board assemblies

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3631632A1 (en) * 1985-09-29 1987-04-02 Asahi Chem Res Lab METHOD FOR CREATING ELECTRICALLY CONDUCTIVE CIRCUITS ON A BASE

Also Published As

Publication number Publication date
ES483975A1 (en) 1980-04-01
GB2030781A (en) 1980-04-10
BE878645A (en) 1980-03-07
NL7906603A (en) 1980-03-11
FR2447131A1 (en) 1980-08-14
GB2030781B (en) 1982-10-13
DE2838982B2 (en) 1980-09-18
SE7907298L (en) 1980-03-08

Similar Documents

Publication Publication Date Title
DE4125879C2 (en) Printed circuit boards and processes for their manufacture
DE68909853T2 (en) Process and film for making printed circuit boards.
DE3545989C2 (en)
DE3525416C2 (en)
DE102006051762B4 (en) High-density printed circuit board and method for its production
DE1078197B (en) Printed circuit
DE102006045127A1 (en) Method for producing a high-density printed circuit board
DE3700910A1 (en) METHOD FOR BUILDING ELECTRICAL CIRCUITS ON A BASE PLATE
DE3800890C2 (en)
EP0549791A1 (en) Multilayer printed circuit board and method of manufacture
DE2838982A1 (en) METHOD FOR PRODUCING MULTI-LAYER PCB
CH654161A5 (en) METHOD FOR PRODUCING PRINTED CIRCUIT BOARDS with perforations, whose walls METALLISIERT ARE.
DE3688255T2 (en) METHOD FOR PRODUCING MULTI-LAYER BOARDS.
DE2251829A1 (en) METALIZED PANEL PRODUCTION METHOD
DE69027530T2 (en) METHOD FOR INCREASING THE INSULATION RESISTANCE OF PCB
EP3657914A1 (en) Printed circuit board for led module and method to manufacture the same
EP0282078B1 (en) Process for making an electrical-circuit board comprising a metal core and basic material for the same
DE2515875A1 (en) Multilayer printed circuits made by additive system - to give thin dielectric coating without etching
DE3006117C2 (en) Process for the production of printed circuit boards with at least two conductor additions
EP0016952B1 (en) Method of making prints provided with masks
DE69922271T2 (en) CIRCUIT BOARD MANUFACTURING METHOD
DE3623505C2 (en)
DE19512272C2 (en) Method for producing a multilayer printed circuit board for a chassis of a consumer electronic device and printed circuit board produced according to this method
DE3328342A1 (en) Method of soldering chip components onto printed circuit boards
DE3412502A1 (en) Method for producing printed-circuit boards

Legal Events

Date Code Title Description
OAP Request for examination filed
OD Request for examination
8235 Patent refused