DE2753607A1 - MONOLITHIC INTEGRATED BIPOLAR MEMORY - Google Patents

Description

<v? ·. L ' .... ρ-. MUNICH2 ι 34 LANDVVCHK ^ TfI. 3T 8ΟΓ3Ο TtL. O C3 / ÜUÜ7

Munich, December 1, 1977 Lawyer files: 27 - Pat. 18l

Raytheon Company ,. lk \ Spring Street, Lexington, Mass. 02173 »United States of America

Monolithically integrated bipolar storage

The invention relates to monolithically integrated bipolar read-only or read-only memories (ROM) and programmable pest value memories (PROM). It relates in particular to a circuit for controlling the power loss in the ROM or PROM modules and a circuit for controlling the programming in PROM blocks.

As is known, monolithically integrated bipolar ROM and PROM modules are used to a large extent for storing program and microprogram control commands, since they are comparatively fast and non-volatile and the stored ones Do not lose control commands even if the supply

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voltage fails. Monolithically integrated bipolar RON and PROM components generally comprise an array of memory elements, which is also referred to below as a "memory array" for short, and which is connected to an addressing circuit and an output circuit. Such an addressing circuit contains npn output transistors whose emitter electrode is connected to a ground line, whose collector electrode is connected to the + V line and whose base electrode is connected to a control signal. Depending on this control signal, the individual transistors can be selectively switched between the "ON" or saturation state and the "OFF" state. In order to reduce the quiescent power loss of an unselected memory module consumed by the addressing circuit, the memory module has a corresponding preparation circuit for controlling the quiescent power loss, which is also referred to below as a "quiescent power control circuit". The switching process in question is known as "power switch. If such a memory module is in the idle state, an undesirably high power consumption - typically of the order of 0.5 W per module - has hitherto occurred despite the idle power control circuit. A known quiescent power control circuit uses a pnp -Schalttransistor whose emitter electrode 'is connected with its base electrode having a Steuereignalquelle and via a resistor also ^v to the supply voltage' to the positive pole of a supply voltage V _cc and the collector electrode are connected to the + V _0Q -Leitung of the memory device. to a possible To achieve a short access time for the ROM or PROM component, the pnp switching transistor should be of a fast switching type.A class of very fast high-current transistors has a Schottky clamping diode between the base and the collector zone en can easily be formed in monolithic integrated circuits of pnp transistors by placing a platinum-silicon layer under the metallic contact of the base zone, which extends below these contacts from a part of the base zone of p-conducting to an adjacent part of the collector zone of η -conductive material extends. The alternate

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effect between the platinum and the n-conductive silicon a diode between the base and collector of the transistor. However, this manufacturing technique cannot be used for the formation of pnp transistors with Schottky diodes.

Another quiescent power control circuit uses an npn transistor operating as an emitter follower with an between the Base electrode and the positive pole V 'of the supply voltage

CC

voltage-switched resistor, which is referred to below as the `` response resistance ". The emitter electrode of this npn transistor is connected to the + V" line, its collector electrode

CC

connected to the positive pole of the supply voltage V.

CC

The npn transistor is in the "OFF" state (and thus the memory module is de-energized) when a signal with a low level value is fed to its base electrode. However, this results in power consumption in the response resistor when the memory module is in the idle state. The resistance value of the response resistance should be low, around the voltage drop V _ri -, between the voltages V '_ and + V__ as low

UiJ CC CC

as possible when the memory module is activated. The reduction in the resistance value of the response resistor, however, leads to a higher power consumption in this resistor when the memory module is in the idle state.

The invention is based on the problem of solving the difficulties arising from the problems described above and to provide an improved memory power-up arrangement and, in particular, an improved quiescent power control circuit which is suitable for use in very high-speed applications Save and should be suitable for manufacture as a monolithic integrated circuit. The invention is also intended to provide a way to Show creation of improved monolithically integrated bipolar ROM or PROM modules with a very fast idle power control circuit. This task is carried out by the in the characterizing part of claim 1 mentioned features solved.

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According to the invention, the memory field contained in a monolithically integrated circuit is generated by means of a transistor, a Schottky diode is formed between its base and collector zone, selectively and as a function of a control signal connected to or disconnected from an earth line.

In a preferred embodiment, the monolithic integrated circuit comprises a semiconductor substrate, a first conductor formed on this semiconductor substrate, via which the circuit can be connected to a positive potential of a supply source, a second conductor formed on the semiconductor substrate, which functions as a ground conductor and is connected by the circuit can be connected to a negative pole of the supply source, a third conductor, a memory field formed on the semiconductor substrate, an addressing circuit consisting of a multiplicity of interconnected active and passive elements formed on the semiconductor substrate with a multiplicity of output transistors , each of which can be supplied depending on its base Control signals can be switched between a conductive and a non-conductive state, the collector electrode of each of these output transistors being connected to the first conductor and its emitter electrode to the third conductor and a quiescent power control circuit formed on the semiconductor substrate and including a pair of transistors arranged in an active response configuration, one of them having the emitter electrode connected to the second conductor functioning as a ground conductor and the collector electrode connected to the third conductor is connected and a Schottky diode is formed between the collector and the base zone of this transistor.

In the following, the invention will be explained in more detail with reference to the exemplary embodiment shown in the drawing:

Fig. 1 shows a block diagram of a programmable read-only memory (PR (Mf) according to the invention,

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Fig. 2 is a diagram showing the relationship between Figs. 2A and 2B,

2A show - put together - a circuit diagram of the ^{PROM 1} S ^{shown in 1111 (1 2B} FIG. 1

Fig. 3 shows - in a somewhat distorted representation - a cross section through a pnp transistor, which in the case of the one shown in Fig. PROM shown is used,

Fig. 4 shows - in a somewhat distorted representation - a cross section through an npn transistor, which in the in Fig. 1 shown PROM is used.

The illustrated in Fig. 1 programmable read-only memory (PROM) 10 is using conventional manufacturing methods for Manufacture of monolithic integrated circuits on a single crystalline semiconductor substrate made of p-type silicon educated.

The PROM 10 includes an array 14 of memory elements for storing 2048 bits in an arrangement of 512 words of 4 bits each, an addressing circuit 16 for controlling the memory array 14 as a function of binary signals sent from an address signal source (not shown) to input connections Aq to Aq, a ROM output activation circuit for activating a selected copy of the 512 four-bit words, which is to be connected to output terminals O ₁ to O ^ via output buffer circuits 20a to 20d, a ROM program activation circuit for storing bit information in the Memory field 14 as a function of a program activation signal applied to an activation connection E, a circuit 24 'for switching on the power, by means of which the addressing circuit 16 is supplied to the activation connection E as a function of an idle or chip control signal source (not shown).

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or the chip control signal can be connected to a (not shown) + 5V supply voltage, a + V _{Ä line} 26 for

cc

The positive potential of the + SV supply voltage is supplied via a "V." designated connection, as well as a ground conductor 28 for supplying the negative potential (wet) of the + SV supply voltage via a connection labeled "GND". The individual switching functions are explained below.

The addressing circuit 16 includes an X address inverter circuit 30, an X decoding circuit 32, a Y address inverter circuit 34 and a Y decoding circuit 36, whose Details are shown in Figure 2A.

First, the X address inverter circuit 30 will be described in more detail. It comprises a plurality (in example 5) of X-address inverters 38a to 38e, which in the manner shown with the respective input terminals A ^ to Ag are connected. The X address inverter 38e is shown as an example. It has a pnp transistor 40, the base electrode 40b of which with the input terminal Ag, whose emitter electrode 4Oe via a resistor 42 to the + V_ line and whose collector

CC

Electrode 40c with the ground conductor 28 are in connection. The formation of such a transistor 40 in the semiconductor substrate 12 is shown in FIG. 3. The transistor is electrically isolated from other active elements formed in the substrate 12 by p ⁺ -conducting regions 42 which are diffused into an η -conducting epitaxial layer 44 in the manner shown. An n ⁺ -conducting region 46, which is diffused into the epitaxial layer 44 in the illustrated manner, forms the base zone of the transistor 40. A p -conducting region 48 diffused into the epitaxial layer 44 in the illustrated manner forms the emitter zone of the Transistor The base electrode 40b is formed over the oxide layer 49 and is in ohmic contact with the base zone 46. The emitter electrode 40e is in ohmic contact in the manner shown

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Contact with the p ⁺ -conducting insulation area. The usual manufacturing processes for monolithically integrated circuits are used for production. The p-conducting substrate 12 therefore forms the collector zone of the transistor 40, the collector electrode 40c is connected to the ground conductor 56 (FIG. 2A) and thus controls the interconnection between the ground conductor 28 and the collector zone of the transistor 40 (ie the substrate 12) the p ⁺ -conducting insulation region 42.

Again, the X-address inverter shown in Fig. 2A Referring to Fig. 38e, the emitter electrode 40e of transistor 40 is also connected to the base electrode of an npn multiple emitter transistor 48 connected, which is equipped with a Schottky clamp diode. The collector electrode of the transistor 48 is connected to the + V_ line via a resistor 43

CC

tied together. An emitter electrode of the transistor 48 is connected at a node 54 to the collector electrode of a transistor 52. The circuit point 54 is connected via a resistor 45 to the + V line 26 and to a line A ' _Q

CC O

closed. The second emitter of transistor 48 is connected to the base electrode of transistor 52 and, via a resistor 47, to a switched ground conductor 56. The emitter electrode of the transit gate 52 is also connected to the switched ground conductor 56. It should be mentioned here, with reference to FIG. 1, that the switchable earth conductor 56 provided in the addressing circuit is connected from the circuit 24 for power connection to the earth conductor 28 when the PROM 10 is activated, and that the switched earth conductor from the circuit 24 to Power connection is disconnected from the earth conductor 28 again when the PROM 10 is to go into the idle state. These switching states are controlled by an idle or chip control signal that is fed to terminal 1. The nature of this control is explained below. Suffice it to say here that when the switched ground conductor 56 is connected to the ground conductor 28 (thus activating the PROM 10), the PROM 10 is connected to the + 5V supply voltage (not shown). That

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The signal appearing on the line A ' ₈ is then the complement of the signal present at the input terminal Ag for the following reasons: (1) If the signal at the input terminal A _{Q has} a high level value (i.e. represents a logical ^W 1 ^W ), the Transistor 40 in its "OFF" state and transistors 48 and 52 in their "ON" state, thereby connecting node 54 to the switched ground conductor and therefore to ground potential, so that a low level value (ie a logic "0") is generated; (2) When the signal at the input terminal A _{3 is} low, the transistor 40 is turned on and controls the transistors 48 and 52 in the "OFF" state, whereby the node 54 is disconnected from the line 56 and a signal with generated high level value on the line Ä'g. When the PROM is idle and the switched ground conductor 56 is disconnected from the ground conductor 28, the transistors 48 and 52 are essentially non-conductive so that there is essentially no power loss across the resistors 43, 45 and 47 either. The collector electrode of the transistor 48 is connected to the base electrode of the transistor 50 via a resistor 57 in the manner shown. The collector electrode of the transistor 50 is connected to the base electrode of a transistor 60 and via a resistor 58 to the + ν _{Λ line} 26. An emitter electrode of the transistor 50 is connected to the emitter electrode 60 and to the collector electrode of the transistor 62 at the node. A second emitter electrode of the transistor 50 is connected to the base electrode of the transistor 62 and via a resistor 66 to the switched ground conductor 56. The emitter electrode of transistor 62 is also connected to switched ground conductor 56. Line A ' ₈ is connected to node 54; if the switched earth conductor is interconnected with the earth conductor 28 by the circuit 24 for power connection (FIG. 1), the signal on this line A ¹ Q bit matches the signal at the input _{terminal A 8.} The operation of the transistors 50 and 62 as a function

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the signal at the base electrode of transistor 50 is dependent on the operation of transistors 48 and 52 from the signal at the base electrode of transistor 48 is equivalent. When the PROM 10 is idle, the switched Ground conductor 56 is thus separated from ground conductor 28, transistors 50, 60 and 62 are essentially non-conductive and thus there is essentially no power consumption in the resistors 57, 58 and.

The Y address inverter circuit 34 is considered in more detail below: It comprises a multiplicity of (in example 4) identically constructed Y address inverters 70a to 70d. These inverters 70a to 70d are connected to the relevant input connections A _Q to A in the manner shown. One example of the inverters 70a to 70d - namely the inverter 70d - is shown in more detail: it comprises a pnp transistor 72 which is designed in a similar manner to the transistor 40 (FIG. 3). The base electrode of this transistor 72 is connected to the input terminal A * as shown. Its collector electrode is connected via a resistor to the + V "line 26 and to the base electrode of a transistor

74 connected. Its collector electrode is connected both to the base electrode of a transistor 76 and via a resistor 73 connected to the + V_ line 26. The emitter electro

CC

De of the transistor 74 is connected to the base electrode of a transistor 78 and via a resistor 80 to the switched ground conductor 56. The collector electrode of the transistor 76 is connected to the + V "line 26, its emitter electrode

CC

de is connected to a circuit point 84 via a Schottky diode 86. The collector electrode of the transistor 78 is connected to the node 84, and its emitter electrode is connected to the switched ground conductor 56. The line Ä '* is connected to the circuit point 84. When the PROM 10 is activated, that is, the switched earth conductor 56 is interconnected with the earth conductor 28, the signal on the line 'is the complement of the signal at the input - for the following reasons

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- JT-

AS 27S3607

Terminal A,: (1) When the signal at input terminal A, is high, transistor 72 becomes "OFF" and transistors 74 and 78 are turned on and connect node 84 to ground potential; (2) When the signal at input terminal A i is low, transistor 72 is turned on, thereby driving transistors 74 and 78 to their non-conductive state so that node 84 goes high. The signal at node 84 is ^{fed to the base electrode of transistor 74 f} via a Schottky diode 90 and a resistor 92. (The common connection point between the Schottky diode 90 and the resistor 92 is connected to the + V "line 26 via a resistor 94 in the manner shown.) The transistors 74 ', 76' and 78 ',

the resistors 80 ', 73 * and the diode 86 * are arranged in the same way as the above-described transistors 74, 76 and 78, the resistors 80, 73 and the diode 86. It follows that when the PROM 10 is in the working state , (ie, switched ground conductor 36 is interconnected with ground conductor 28), the signal on line A ¹ (which is the signal on the collector electrode of transistor 78 ') corresponds exactly to the signal on input terminal A ^. Likewise, it follows that when PROM 10 is idle, essentially no power is consumed in resistors 73 'and 80'.

The X decoding circuit 32 will now be described in more detail below: It contains a multiplicity of (here 32) identically constructed logic NAND gates 100 _Q to ICK) ₅₁ . The NAND element 10Oq is shown as an example; It comprises a multiple emitter input transistor 102, the base electrode of which is connected to the + V- line 26 via a resistor 104.

CC

In the present illustration, the transistor 102 has five emitter electrodes, each of which via a connection arrangement 105 to one of the X-address inverters 38a to 38e connected. The connector assembly 103 includes a

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Variety of connectors (not shown). These serve to connect the lines 5 ¹ ^, ^ '5 »^' 6 '^ V ¹ ^ ¹⁰ ^' θ ^m ** ^ ^e ~ while one" of the five emitter electrodes of the transistor 102. The collector electrode of the transistor 102 is via a Resistor 110 is connected to the base electrode of a transistor 108. The collector electrode of transistor 108 protrudes through a resistor 112 to the + V "line 26 and over

CC

a Schottky diode 116 in communication with the collector electrode of a transistor 11A. The emitter electrode of the transistor 108 is connected to the base electrode of the transistor 114 and via a resistor 117 to the connected earth conductor 56 connected. The emitter electrode of transistor 114 is connected to switched ground conductor 56, its collector electrode is in communication with the + V_ line 26. if

CC

the PROM 10 is activated, ie the switched earth conductor 56 is interconnected with the earth conductor 58, the transistor 114 is activated in response to signals with a high level value on each of the lines '^, ¹ , -, · / -, £'" and £ '»controlled in its conducting state. It returns to its "OFF" state when the signal on any of these lines goes low. The signal at the collector electrode of transistor 114 is passed on to line Rq. The line Rq therefore has a low level value when a binary word 00000 appears at the input connections A ^ to Ag. For every other binary word at these input connections, however , the signal on line Rq has a high level value. When the PROM 10 is activated, the NAND gates 10Oq to 10Oz ₁ deliver, depending on the binary signals present at the input connections A ^ to Ag, on the lines Rq to signals with a high level value according to the following table *

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Binary signals on line with low lines with high Input terminals like signal level signal level

^A 4 * 5 ^A 6 OOOOO R ₀

10 0 0 0 R ₁ R ₀ , R ₂ -R ₃₁

0 1111 R ₃₀ R ₀ -R ₂₉ , R ₃₁

11111 R ₃₁ R ₀ -R ₃₀

The lines R ₀ to R ₃₁ t to which the output signals of the NAND elements 100 _Q to 10 O _{31 are} applied are connected to the memory field 14. When the PROM 10 is idle, transistors 102, 108 and 114 are non-conductive, so there is essentially no power dissipation in resistors 104, 110, 112 and 117.

Before the details of the Y multiplexer and the decoding circuit 36 are explained, it should be mentioned that the memory field 14 has four identically designed diode matrices 400a to 40Od. The diode matrix 400c shown as an example consists of a right-angled matrix of cell and column conductors, namely it has 32 row conductors, which are connected to lines R ₀ to R _{31 as shown} , and sixteen column _{conductors labeled C 0} to C _{1 C} . The row and column conductors are connected to one another at the crossing points prior to programming with conventional fusible lines and diodes, as described, for example, in the reference "The Integrated Circuit Catalog For Design Engineers", Texas Instruments, Incorporated, Dallas, Texas, page 9-366 is described. The programming and reading of the memory

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field is explained below; here it suffices to point out that the memory field 14 is programmed in that currents are passed through selected specimens of the fusible links which break those fusible links and that the data is read from the memory array by determining whether a selected fusible link is broken.

The Y-multiplexer and the decoding circuit 36 are explained in more detail below: The latter contains a plurality of (in the present example 4) identically designed diode decoding circuits 402a to 402d. The exemplary illustration of the decoder circuit 402c shows a diode decoder 404 which is connected to the + V _{cc line} 26 and the signals on the lines A'q,. Ä'q »A ¹ ^, 1 '^ ₁ A' ₂ , Ä ' ₂ , A ^f , and Α ¹ , is connected. The diode decoder consists of a matrix of sixteen column lines 408q to 40e ₁₅ and eight row conductors 410 _Q to 41Oy. The row conductors 41O ₀ to 41O ₇ are connected to one of the lines A'q to A ', and ä'q to Ä', via the connection arrangement 406 according to the following table:

Line connected with row conductor

A ' _o - 41O ₄

* ^f 0 * ^41O 5

A ^ -> 41O ₂

A ' ₂ - * 41O ₀

i ' ₂ · »41O ₁

41O ₆

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The column conductors 408q to 408, .- are shown in FIG Way, each with the base electrode of one of the transistors 41 2q to 4 ^ 2, .C connected. The emitter electrodes of the transistors 412q to ^ ¹ 2 ^ c are each connected to one of the lines Cq to C ₁ C. The collector electrodes of the transistors 412 to 412.] c are connected in common to a line 416 _Q. The line 416 ″ leads to an output buffer circuit 20c (FIG. 1), which in turn is connected to the output terminal 0, (FIG. 1). The mode of operation and the structure of the output buffer circuit are explained below; Suffice it to say here that when the PROM is activated for programming, current from a (not shown) connected to the output terminal 0, +20 V supply voltage via line 416c to a selected copy of the transistors 412 _Q to 412 ^ e and via this to a selected copy of the sixteen column conductors Cq to C ^ c flows in the diode matrix 400c. The appropriate copy of the transistors 412 _Q to 412 ^ is selected as a function of the signals on the lines A'q to A ¹ , and A'q to A '. The following table shows the relationship between the signals on lines A'q to A ¹ , and i ' _o to Ä', and the selected example of transistors 412 _Q to 412 ₁₅ :

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A ' _o Ä' _o

Signal on the lines A ^ A ' ₂ Ä' ₂ A ' ₃ Ä' Selected transistor

L. H H L. H L. H L. H L. L. H H L. H L. L. H L. H H L. H L. H L. H L. L. H H L. L. H H L. L. H H L. H L. L. H L. H H L. L. H L. H L. H H L. H L. H L. H L. L. H L. H H L. H L. L. H H L. L. H H L. L. H L. H L. H H L. L. H H L. H L. L. H L. H L. H H L. L. H L. H H L. L. H L. H L. H L. H L. H L. H L. H

412 412

14 13

412 412 412 412 412, 412 ₍

412 «

412 ^

412 _:

412 j

412! 412,

11 10

L - low signal level H - high signal level

By the selected copy of the transistors 412 to 412 ^ - and thus through a selected copy of the sixteen columns

heads C _n to C

current flows through the matrix 40Oc

selected copy of row conductors Rq to IU ₁ via the fusible link that lies between the selected row conductor and the selected column conductor. This stream is of sufficient size to create the fusible link

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to separate. One of the thirty-two row conductors is selected by controlling the transistor 114 in one of the 32 NAND gates 10Oq to 100, .. into its conductive state. For example, if the row conductor connected to line Rq is to be selected, the input signals at input terminals A ^ to Ag have the value 00000. Therefore, the signals on lines XV to Ä'g have a high level value, transistor 102 becomes non-conductive and transistor 114 is driven into its conductive state (assuming PROM 10 activated, ie, switched ground conductor 56 is connected to ground conductor 28). If the fusible connection F is to be "opened", the binary signals 111100000 must be present at the input connections Aq to A ». Current flows from the +20 V supply voltage (not shown) connected to output terminal O ^ to output _{buffer circuit 20c, then to line C 1} Ct via fusible link F, via line Rq, transistor 114, den connected earth conductor 56, the circuit (24) for power connection (Fig. 1) to the earth conductor 28 and finally to the (not shown) earth connection of the +20 V supply voltage. In this way, the output buffer circuits 402a to 402d provide the "column addresses" for the fusible links in the relevant matrices 400a to 40od. The "row addresses" of the fusible links in all of the matrices 400a through 40Od are selected by the signals on lines Rq through R ^ ₁ , since these lines are connected to all of the matrices 400a through 40Od as shown.

FIG. 2B exemplifies one of the output buffer circuits 20a to 20d - namely the output buffer circuit 20c - shown. It comprises a programming section 502 and a reading section 504. The programming section 502 includes a pair of transistors 506, 508 which are Darlington connected is arranged. The emitter electrode of transistor 508 is

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27S3607

connected to line 416c, the collector electrodes of the transistors 506 and 508 are connected to the output terminal 0 i. The emitter electrode of transistor 506 is shown in FIG Connected to a diode 510 and the base electrode of transistor 508. The base electrode of transistor 506 is across a resistor 514 and a diode 516 with the line 512 leading to the output of the PROM program activation circuit 22 tied together. The cathodes of diodes 516 and 510 are connected to one another and to line 512. The reading section 504 includes a transistor 522, the emitter electrode of which is connected to the ground conductor 28 and the collector electrode of which is a Schottky diode 524 and the output terminal 0 are connected. Its base electrode is connected to the earth conductor 28 via a resistor 526, Connected via the resistor 530 to the base of a transistor 528 and to the emitter of this transistor 528. the The collector electrode of transistor 528 is connected to the base electrode of a transistor 534 and the anode of a Schottky diode 536 and connected to the + V "line 26 via a resistor 532. The collector electrode of transistor 534 is over a resistor 538 is connected to the + V line 26. the

CC

The emitter electrode of the transistor 534 is connected to the anode of the Schottky diode 524. The base electrode of the transistor 528 is connected to the emitter electrode of a transistor 540 via a diode 542 and a resistor 541. the The collector electrode of the transistor 540 is connected to the + V "line 26 via a resistor 544. The base electrode

CC

of transistor 540 is finally via a resistor 546

with the + V ^ line 26, via the Schottky diode 548 and the cc

Diode 550 to the cathode of diode 536 and across the Schottky diode 542 connected to line 416c. The details of the PROM program activation circuit 22 and circuit 24 for Power connections are described below. It suffices here to point out that ^ ate when the connection E was a Program activation signal is supplied, a voltage, in the present example +21 V, occurs on line 512 and that the earth conductor 28 from the circuit 24 to the power

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circuit is connected to the switched ground conductor 56. As a result of this +21 V voltage on line 512, transistors 506 and 508 receive base current. Thereupon flows from the positive pole of the supply voltage (not shown) connected to the output terminal 0, current via transistors 506 and 508 to line 416c and to ground conductor 28 (i.e. to the negative pole of the supply voltage), whereby a selected fusible link in matrix 400c is severed in the manner described above. While this programming process generates the ROM output enable circuit 18 for reasons explained below become a low voltage on line 520. The line 520 is in the manner shown with the The cathode of the diode 550 and the cathode of the Schottky diode are connected. Hence the tension during the programming process The low voltage on line 520 will forward diodes 548 and 550, causing transistor 540 is controlled in its non-conductive state while the diode 542 is reverse biased. Since transistor 540 is off, the transistors become and 522 are controlled in their non-conductive state and thus prevent the positive pole of the (not shown) with the output terminal 0, connected supply voltage is connected to ground conductor 28 via transistor 522.

When the "read" operation is selected, line 512 is open circuit. Therefore, no control current flows to transistors 506 and 508. In addition, the signal on line 520 is high, so that diodes 548, 550 and 536 are blocked. Therefore, transistor 540 can be turned on or off depending on the signal levels on line 416c. The signal level on line 416c depends on whether or not the fusible link selected _{by the signals at input terminals A 0} through A _{8 is broken.} For example, if that

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PROM 10 is activated (ie, switched ground conductor 56 is connected to ground conductor 28), one of the selected row conductors (ie, one of lines Rq to R ,,.) Is connected to switched ground conductor 56 via switched-on transistor 114 and therefore has one low signal level. In addition, current can flow through a selected one of the column conductors C ₀ to C ₁ J-. Thus, for example, when the column conductor Rq and the conductor C ^ c are selected, depending on whether the fusible link F is broken or not, current will flow through the transistor 412. ^ or not. The signal level on line 416c is therefore low when connection F is not disconnected, so that transistor 540, transistor 528 and transistor 522 are switched off and a voltage with a high level value is generated at output terminal 0 ,. If, however, the connection F is broken, no current flows through the transistor 412 ^ to the line 416c, the transistors 540, 528 and 522 are conductive and thus generate 0 at the output terminal with a low level value.

The PROM program activation circuit 22 will now be described in detail described: It contains a Zener diode 600 (which in the present example has a Zener voltage of 6 V), a diode 602 and a resistor 604. All of these elements are connected as shown between the activation terminals E and the input terminal 606 of the circuit 24 is switched for switching on the power. Line 512 leads to the connection point between the zener diode 600 and the diode 602. The ROM output activation circuit 18 comprises a multiple emitter transistor 607 (which is designed in a similar manner to the transistor 40 in FIG. 3), the base electrode of which is connected to the activation connection E and the collector electrode of which is connected to the ground conductor 28 connected is. One of its emitter electrodes is connected to the + V "line 26 via a resistor 608 and via a Schottky

CC

Diode 612 connected to the base electrode of transistor 610.

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2? 27536G7

Its second emitter electrode is in the manner shown connected to the base electrode of transistor 610. The collector electrode of this transistor 610 is with the base electrode of the transistor 614 and via a resistor 613 to the + V "" - line 26 connected. The collector electrode of the transistor

614 is also with the + V. Line 26 connected. His

CC

The emitter electrode is connected to the collector electrode of the transistor 616 via a Schottky diode 618 and via a Schottky diode

617 connected to the collector electrode of transistor 619. The base electrode of the transistor 616 is connected to the emitter electrode of the transistor 610, via a resistor 620 with the base electrode of transistor 610, through a resistor 623 is connected to the base electrode of the transistor 619 and to the ground line 28 via a resistor 621. The emitter electrode of transistor 619 is also connected to the ground conductor 28 connected. The base electrode of the transistor 619 is connected to the collector electrode of the via a Schottky diode 640 Transistor 642 connected. The base electrode of the transistor 642 is connected to its emitter electrode via a resistor 646 and connected to line 512 via resistor 644. The emitter electrode of transistor 642 is connected to the ground conductor 28 connected. The emitter electrode of transistor 616 is also connected to ground conductor 28. The Schottky diode

618 is connected to the collector electrode of transistor 616, which is also connected directly to line 520 and across a resistor 624 to the + V. Line 26 in connection

CC

stands.

The circuit 24 for switching on the power includes a transistor 700. Its base electrode is via one of one Schottky diode 704 bridged resistor 702 is connected to the terminal 606, its collector electrode is connected to the base electrode of a transistor 707 and via a resistor 706 with the + V line 26 in connection. The emitter electrode

CC

of transistor 700 is connected to the base electrode of a transistor 710 and connected to the earth conductor 28 via a resistor 708

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bound. The collector electrode of transistor 707 is connected to the + V line 26, while its emitter electrode with the base electrode of a transistor 712 and via a resistor 714 with the emitter electrode of the transistor 712 connected is. The collector electrode of transistor 712 is connected to the + V line 26. The transistor 710

CC

is with its emitter electrode with the earth conductor 28 and with its collector electrode with the resistor 71A and ... one Circuit point 715- connected to the emitter electrode of transistor 712. The circuit point 715 is with the switched ground conductor 56 in connection.

During the "programming" operation, a +27 V signal from a (not shown) Supply voltage applied, the opposite pole of which is connected to the ground conductor 28. This +27 V signal makes the Transistor 642 is controlled in its conductive state, whereby transistor 619 becomes non-conductive. Consequently current flows through the zenard diode 600, the diode 602, the Resistor 604 and resistor 702, by means of which the transistors 700 and 710 are controlled in their conducting state. This applies (1) a +21 V signal to line 112 and (2) the switched ground conductor 56 through the transistor connected to ground conductor 28, thereby activating PROM 10. Note that transistor 607 is off and transistors 610 and 616 are turned on, causing line 520 to go low is brought. Because of the +21 V signal on line 512 and the low signal level on line 520, a current flows from a (not shown) +20 V voltage supply, which is connected between the output terminals O ^ to O ^ and the Ground conductor 28 is connected, via the programming section 502 of the output buffer circuits 20a to 20d, whereby fusible connections in the diode matrices of the memory array are selected in the manner described above will.

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During the reading process, the activation terminal E is supplied with a voltage with a low level value (in the present example +0.3 V), by means of which the Zener diode 600 is blocked, so that the line 512 becomes floating. What is achieved hereby is that (1) the transistor 642 is controlled in its non-conducting state and (2) the programming section of the output buffer circuits 20a to 20d is controlled in its inactive state. (In this case, of course, no supply source is connected to the output connections O ₁ to O ^, since these output connections have to supply logic signals which correspond to the individual bits of the four-bit word to be read out from the programmed PROM 10). The +0.3 V signal at the activation terminal E controls the transistor in its conductive state, so that the transistors 610, 616 and 619 become non-conductive and the line 520 carries a high signal level. Through the switched-on transistor 614 and the polarized in the forward direction Diode 617 will also "pull" terminal 606 to a high signal level. Since the line is floating and the line 520 is calibrated to a high signal, the reading section 504 of the output buffer circuits 20a to 20d provides output _{signals to the output terminals O 1} to 0 ^ which match the signals on the lines 416a to 416d. These signals depend on the state (energized or disconnected) of the fusible links which are addressed in the manner described above by the signals at the input connections A ₀ to A ₇ . The PROM 10 is activated, i.e. the switched earth conductor 56 is connected to the earth conductor 28 via the transistor 710), because the transistors 610, 616 and 619 become non-conductive, and a high signal level arises at the connection terminal 606 via the conductive transistor 614, as soon as the transistor 607 is switched on by the low signal level (+0.3 V) at the activation terminal E. The signal level at the connection terminal 606 controls the transistor 700 in its conductive state and

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in turn turns on transistor 710, which activates PROM 10.

To disable the PROM 10 or put it in its quiescent state (i.e., the connection between the switched ground wire 56 and the earth conductor 28) becomes the activation connection E is supplied with a high level signal (that is, 3.5 V). This blocks the Zener diode 600, so that the line 512 is floating and the transistor 642 is non-conductive. The transistor 607 is through the high Signal level is also controlled in its non-conductive state, so that the transistors 610, 616 and 619 are conductive will. The switching of the transistor 710 into its non-conductive state and thus the inactivation of the PROM 10 go because of the active response configuration of transistors 712 and 710 and because of those associated with transistor 710 Schottky Clamp Diodes run very quickly.

4 shows the structure of the transistor 710: In order to form it on the substrate 12, an n ⁺ -conducting subcollector zone 800 is diffused into the latter. An η-conductive epitaxial layer 44 is grown on the substrate 12. It should be mentioned that, as is known, slight diffusion from the subcollector zone 800 into the epitaxial layer 44 takes place during this production step. Isolation regions 42 ′ are formed around transistor ^{710 by diffusing p +} -type material through epitaxial layer 44 to substrate 12. A base region 802 is formed in the epitaxial layer by allowing p-type material to diffuse into the epitaxial layer 44. The emitter zone 804 and the collector ^{zone 808 are formed in that n +} -conducting material is allowed to diffuse into the base zone 802 or into the epitaxial layer 44. Subsequently, a layer of silicon dioxide SiO _{2 is} formed over the surface and a window 812 is made in the epitaxial layer 44 in one of the usual ways.

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This window 812 made in layer 810 extends extends over a portion of the base region 802 and over an adjacent portion of the epitaxial layer as shown 44. One of the known methods is a film of platinum silicide in the area exposed by window 812 educated. Further windows 820 and 822 are formed in the SiOg layer 810 over the emitter zone 804 and the collector zone, respectively 808 trained. Then metallic contacts 710b, 71Oe and 710c are made for the base, emitter and the collector zones are formed, which serve as the base, emitter and collector electrodes of the transistor 710. The platinum silicide film 814 forms a Schottky clamp diode between the Base and emitter regions of transistor 710.

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Claims (13)

Claims Monolithically integrated formed on a semiconductor substrate bipolar circuit with a memory field consisting of a multiplicity of memory elements and a Addressing circuit for addressing this memory field as a function of address signals, characterized in that that a power control circuit (24) is provided which includes a transistor (710), between its base (820; Fig. 4) and collector zone (800) a Schottky diode (by means of 814) is formed that this transistor (710) equipped with a Schottky diode between the addressing circuit (16, FIG. 1) and a conductor track (28) functioning as a ground conductor is arranged so that the base electrode (710b) of the transistor (710) can be connected to a control signal (at E) that the Arires- * And the ground conductor (28) sierschaltung (i6) / with the aid of the transistor (710) under the control of said control signal selectively connectable to one another or are separated from one another and that the conductor track the ground conductor (28) forming the addressing circuit (16) and the power control circuit (24) are arranged together with the memory field (14) on the same semiconductor substrate (12). 2. Monolithic integrated circuit according to claim 1, characterized in that the power control circuit (24) has a further transistor (712) contains, which together with the transistor (710) equipped with a Schottky diode is arranged in an active response configuration. 3. Monolithic integrated circuit according to claim 1 or 2, characterized in that a program (22) and an output activation circuit (18) are provided, by means of which the following functions can be carried out: 809823/0788 a) Control of the programming of the memory field (14) and Activation of the transistor (710) equipped with a Schottky diode in such a way that the addressing circuit (16) is connected to the ground conductor (28) in response to a first level value of the control signal; b) Read activation of the programmed memory field (14) and activation of the one equipped with a Schottky diode Transistor (710) such that the addressing circuit (16) as a function of a second level value of the control signal is connected to the ground conductor (28) and c) Control of the transistor (710) equipped with a Schottky diode in such a way that depending on one third signal level of said control signal, the addressing circuit (16) is disconnected from the ground conductor (28) is. 4. Monolithic integrated circuit according to one of the preceding claims, characterized in that the memory field (14) contains a plurality of fusible connections (F) which between the crossing points of row (R _Q to R ^ ₁ ) and column lines (R Q to R ^ 1) and column lines ( Cq to C ^ t-) are arranged. 5. Monolithic integrated circuit according to one of the preceding Claims, characterized in that the program activation circuit and the output activation circuit includes a zener diode and that said control signal is applied via this Zener diode to the base of the transistor equipped with a Schottky diode. 6. Monolithic integrated circuit according to one of the preceding Claims, characterized in that two conductor tracks (26 and 28) on the semiconductor substrate are designed, which are connected to the positive or the negative pole of a supply voltage source (V ") CC 809823/0788 are bindable that a third conductor track is provided, which can be connected to or detached from the second-mentioned conductor track (28) with the aid of the aforementioned power control circuit (2k) under the influence of the aforementioned control signal (at E) and that the addressing circuit (16) is connected between the first (26) and the third conductor track (56). 7. Monolithic integrated circuit according to claim 6, characterized in that the equipped with a Schottky diode Transistor 710 between the second conductor track (28) connected to ground potential and the third conductor track (56) is arranged and that this transistor (710) as a function of said control signal (at S) between his .conducting
/ and its non-conductive state can be switched. 8. Monolithic integrated circuit according to claim 7 »thereby characterized in that a further transistor (712) is provided with said transistor (710) in one active response (pullup) configuration is arranged. 9. Monolithic integrated circuit according to one of the preceding Claims, characterized in that a program activation circuit (22) and an output activation circuit (18) are intended to carry out the following functions: a) Control of the programming of the memory field (14) and activation of the one equipped with a Schottky diode Transistor as a function of a first signal level of said control signal such that the second conductor track (28) is connected to said third conductor track (56), b) Control of the reading process by activating the transistor (710) equipped with a Schottky diode 809823/0788 in such a way that, depending on a second level value of said control signal, the second conductor track (28) is connected to the third conductor track (56) and c) control of the equipped with a Schottky diode Transistor (710) such that, depending on a third level value of said control signal, the third Conductor track (56) and the second letter track (28) are separated from one another. 10. Monolithic integrated circuit according to one of the preceding Claims, characterized in that the program activation circuit (22) and the output activation circuit (18) contain a zener diode via which said input signal the base electrode of the transistor equipped with a Schottky diode can be fed. 11. Monolithic integrated circuit according to one of the preceding claims, characterized in that the addressing circuit (16) includes a plurality of interconnected active and passive elements, including a plurality of output transistors (eg 60), each of which is connected to the memory array (14) and depending on the address signals (at Aq to Ag) can be selectively reversed between their conductive and non-conductive state so that the base electrodes can be controlled by the address signals, their collector electrodes with the first-mentioned conductor track (26) and their emitter electrodes with the third conductor track (56) ) are in connection and that one (712) of the transistors (710, 712) of the power control stage (24), which are arranged in the active response configuration, has its emitter electrode with the third conductor track (56) and the Schottky diode formed between the collector and base zones of the other transistor is in communication and that a base elec trode in a Lei s tung control circuit transistor contained (24) 809823/0788 a rest signal can be applied, by means of which this transistor can be selectively controlled in such a way that the second-mentioned conductor track (28) and the third conductor track (56) connected or separated from each other. 12. Monolithic integrated circuit according to claim 11, characterized characterized in that a program activation circuit (22) and an output activation circuit (18) are provided, by means of which the following switching functions can be carried out: a) Control of the programming of the memory field and activation of the one equipped with a Schottky diode Transistor (710) such that the second conductor track (28) functioning as a ground conductor as a function of a the first signal level of the control signal can be connected to or separated from the third conductor track, b) Activation of the read operation of the memory field (14) and activation of the transistor (710) equipped with a Schottky diode in such a way that the second as Conductor track (28) functioning as a ground conductor as a function of a second level value of said control signal is connected to the third conductor track (56) and c) Activation of the transistor (710) equipped with a Schottky diode in such a way that the third conductor track (56) is separated from the second conductor track (28) as a function of a third signal level value of the control signal. 13. Monolithic integrated circuit according to claim 12, characterized characterized in that the control signal of the base electrode of the transistor equipped with a Schottky diode via a Zener diode is fed. 809823/0788