DE10051164A1 - Method for masking data bits to be input into a semiconductor memory by a memory controller gives the data bits to be masked an increased voltage level. - Google Patents

Abstract

Data bits (DQ-Bit) waiting to be masked are fed to a semiconductor memory at a raised voltage level (Le2) that has changed when compared with unmasked bits. The DQ bits are input to a DRAM as a semiconductor memory. DQ bits with the increased voltage level are generated in a driver circuit with a driver logic. The driver circuit and driver logic are contained in a memory controller.

Description

The present invention relates to a method for masking DQ bits (data bits) that are stored by a memory Controller can be entered into a semiconductor memory.

In current memory bus systems, so-called burst writing prevents reading in of bits that have been transmitted but not to be read into the memory, such as a DRAM, by activating an additional DQM connection or pins. An example of such bits that are not to be read into the DRAM are data bits. This process, which is referred to as masking bits, will be explained in more detail below with reference to FIGS. 3 and 4.

In a memory or memory controller MEMC from a DQ logic DQL and a DQM logic DRML a DQ signal DQ or a DQM signal DQM generated. The DQ signal DQ from bits n - 2, n - 1,. , ., n + 3, n + 4 passes from the DQ logic DQL via ei driver DRV1 to a DRAM receiver (or receiver) DR. This DRAM receiver DR is also the DQM signal DQM via ei NEN driver DRV2 supplied.

The DQM signal DQM has a high level and a low level, as can be seen from FIG. 3. If the DQM signal DQM assumes its low level between two times t1 and t2, the bits n + 1, n + 2, n + 3 of the DQ signal DQ are masked in the DRAM receiver DR at the same time as the low level. These masked bits n + 1, n + 2, n + 3 do not reach a DRAM M connected downstream of the DRAM receiver DR.

In this known method, the DQ signal DQ and the DQM signal DQM from the memory controller MEMC externally transmitted to the DRAM M or the DRAM receiver DR. This is the timing of the signals DQ and DQM extremely critical table and susceptible to changes in line routing on a printed circuit board ("PCB routing") and Jitter phenomena (voltage fluctuations, CLK or clock Instabilities).

It should also be noted that the cable routing or the Routing for the DQM signal requires additional space and this cable routing is extremely precise to the cable routing must be coordinated for the DQ signal DQ. That is, the ever there are line lengths to be routed for the two signals DQ and DQM must be strictly observed. All of this leads for modules consisting of several DRAMs with a high packing density big problems.

Finally, it should also be borne in mind that the DRAM Receiver DR requires additional pins for the DQM signal DQM become what makes corresponding plugs in the module complex.

It is therefore an object of the present invention to provide a method to mask DQ bits specifically for increasing packing densities of memory modules and at high ones Clock frequencies are applicable and routing problems largely overcomes.

This task is carried out in a method of the aforementioned Art solved according to the invention in that the masked DQ bits the semiconductor memory with unmasked DQ  Bits changed, especially increased voltage level leads.

The method according to the invention thus performs one for the DQ bits changed, preferably increased, masking voltage level on: Are the DQ bits or the DQ signal on the changed or increased voltage level, the ent speaking bits masked. This means that the DRAM receiver is only DR another connection for the DQ signal or for the setting required by its masking. So it gets significant Space saved, which is a big one for building the module Advantage means.

Problems due to incorrect or lack of coordination tion between the DQ signal DQ and the DQM signal DQM largely avoided since the setting on the normal or increased voltage level for the DQ signal already in egg ner driver logic is made in the memory controller. These short signal paths also make time-critical pros problems due to routing on a printed circuit plate as well as jitter appearances and clock instabilities largely excluded.

The invention will be described in more detail below with reference to the drawings explained. Show it:

Fig. 1 is a schematic representation of the course of the DQ bits in the inventive method,

Fig. 2 is a block diagram of a circuit arrangement for implementing the method according to the invention,

Fig. 3 is a schematic representation of the course of DQ bits and a DQM signal in an existing method for masking the DQ bits and

Fig. 4 is a block diagram of a circuit arrangement for performing the existing method.

FIGS. 3 and 4 have already been explained in the introduction.

In the figures, components which correspond to one another are each provided with the same reference symbols. As can be seen from FIG. 1, in the method according to the invention the DQ signal, which consists of the DQ bits, has two different levels, namely a normal level Le1 and an increased level Le2. During the increased level Le2 between times t1 and t2, the bits of the DQ signal are masked. This means that these masked bits are not read into the DRAM M.

The level Le2 of the DQ signal with increased voltage V becomes during the time window between times t1 and t2 the time t, for example, by appropriate control nes driver circuit DRV and a driver logic DRV-L er testifies. Outside this time window between the times t1 and t2 the driver logic DRV-L controls the driver switch circuit DRV so that this the DQ signal with the lower Level Le1 delivers.

The key to the present invention is thus the introduction of two different levels Le1 and Le2 for the DQ Signal: The DQ signal is at the low level Le1, the bits of this DQ signal are not masked.  

If, on the other hand, the DQ signal DQ assumes the increased level Le2, then the bits of the DQ signal are masked.

Since the driver circuit DRV and the driver logic DRV-L in Memory controller MEMC are included, long omitted Signal paths for the QR signal and for the DQM signal. Thereby become routing problems or problems due to time Mismatches in the individual signal paths for the DQ signal DQ and the DQM signal DQM practically completely excluded sen. In addition, high packing densities can be achieved because practically no additional long ones for the DQM signal Signal paths are needed.

In the above embodiment, the masked bits of the DQ signals the increased level Le2. But it is also possible Lich, a lower level than for these masked bits provide the level of the normal signal Le1. Important is So only that the masked bits by a nor Color level of the DQ bits differing levels are marked.  

LIST OF REFERENCE NUMBERS

DQ data
DQM data masking
V voltage
t time
MEMC memory controller
DRV driver circuit
DRV-L driver logic
DR DRAM receiver
M memory
Le1 low level
Le2 high level
DQMG DQM signal generator

Claims (5)

1. A method for masking DQ bits (DQ), which are entered by a memory controller (MEMC) into a semiconductor memory (M), characterized in that the DQ bits (DQ) to be masked are connected to the semiconductor memory (M) voltage level (Le2) changed compared to unmasked bits (DQ). 2. The method according to claim 1, characterized in that the DQ bits (DQ) to be masked in the semiconductor memory (M) with an increased voltage level (Le2). 3. The method according to claim 1 or 2, characterized in that the DQ bits entered a DRAM as a semiconductor memory (M) become. 4. The method according to any one of claims 1 to 3, characterized in that the DQ bits with a change compared to unmasked DQ bits Voltage level in a driver circuit (DRV) with a Driver logic (DRV-L) are generated. 5. The method according to claim 4, characterized in that the driver circuit (DRV) and the driver logic (DRV-L) in the Memory controller (MEMC) are included.