DE2726700C2 - System for the suppression of unwanted echoes in an impulse radar - Google Patents

Description

The invention relates to a system for suppressing unwanted echoes in a coherent pulse radar through adaptation techniques. In particular, the present invention relates to a system in which the suppression or deletion of unwanted echoes is carried out by adaptation techniques can be where these echoes are caused by targets moving with a certain relative speed move to the radar. All of these unwanted echoes, for example due to reflections caused by the environment, the lake, rain, etc. is referred to as "blemishes".

The problem of suppression of clutter in radar systems has already been addressed in earlier techniques, namely through the use of so-called MTI suppressors (Moving Target Indicators). Such Suppressors are basically nothing more than filters whose parameters are set once and for all have been.

The operation of this suppressor is based on the analysis of the Doppler signal, which is from the radar echo is obtained as well as from a coherent generator. The usual MTI devices are designed in such a way that that the frequency response is zero when the Doppler

Is zero frequency, which results in that only those unwanted echoes are erased, which are generated by targets that are not moving relative to the radar.

The deletion of echoes that originate from targets turned out to be a particular problem move relative to the radar. Such echoes are generated, for example, by rain, by the sea, or by clouds of dust etc. caused. Under such conditions, the usual MTI devices are loose Assessment unsuitable to provide a sufficient mean improvement in the signal-to-clutter ratio. To solve the first of these problems, the so-called AMTI system (Airborne Moving Target Indicator System) as a moving target indicator for moving radar. With these oppressors the relative speed of the movable platform is compensated by the fact that the frequency of the Coherent oscillator is varied so that a Doppler frequency of zero is obtained for fixed targets.

With the AMTI devices, the frequency of the coherent oscillator can be changed at most once per scanning or deflection. Therefore, if during the same scan through the terrain and clutter caused by rain in different If there is a distance, an AMTI device allows effective suppression of the stronger clutter, however only a slight suppression of the remaining interference spots. In the case of stationary radar and moving So far, blemishes have not been satisfactory Solutions are found, and. '. In particular was not within a suppression that works according to the MTI system. Other techniques have been used instead, e.g. B. Batteries of Doppler filters, which, however, led to very complex circuits.

The object of the invention is to avoid the disadvantages mentioned above and to show a system which allows the suppression of unwanted echoes with simple means, both from such Echoes originating from targets that are stationary to the radar as well as from such targets, which have a non-zero speed relative to the radar.

To solve this problem, a system is proposed according to the invention, which with a conventional Suppressor is constructed, with an input with a constant weighting equal to 1 and an input with an evaluation is applied, which can be varied by adaptation or approximation. The review is variable in such a way that the frequency behavior or the frequency characteristic of one Moment to the next assumes the value zero for a value of the Doppler frequency equal to that The mean value of the frequency of the unwanted echcs is.

The invention and its mode of operation are illustrated below with reference to the figures of exemplary embodiments described. It shows

F i g. 1 is a block diagram of a system embodying the invention, this block diagram being a provides a simple illustration of the functioning of the invention,

FIG. 2 is a block diagram similar to FIG. 1, in which a method of using a multiple suppressor is shown,

F i g. 3 is a block diagram of a system embodying the invention in which the suppression is done by a common recursive MTI device.

FIG. 4 is a block diagram similar to FIG. 2, in which however, the complex form of the incoming radar signal (video signal) is taken into account, showing the operators that refer to the two Components, phase and frame, of the signal act,

F i g. Figure 4a is a detailed block diagram of the complex amplifier of Figure 4a. 4th

To understand how the Schill (circle /.u niiii'hen, follows a kiir / .c iruiihinuttic bypass of the main quantities that occur when the circuit is working.

To the mean Doppler frequency of the clutter or interference signal / 0 or - in other words, the mean Doppler phase value

Φο = 2, τ / ο T (T = repetition time)

To be able to estimate, it is sufficient to determine the clutter voltages of two successive passes or scans (sweeps) even if the suppression uses more than two passes. Therefore, if with Vi and V2 the complex video voltages, which occur one after the other according to the repetition time or repetition period duration and are present at the input of the MTI device

E [V ₁ * V ₂ ] - where:

~ mean value of the clutter ~ correlation coefficient ⁼ the conjugate complex value of Vi V ₂ ] = the estimated value of the product

The Doppler phase results from the following equation:

EW

LLYl
■ [vs

In order to determine the Doppler phase Φη or, more precisely, the complex number & * d , it is necessary to estimate the complex quantity or the complex product Vi * V2. For an interference spot or for an interference signal which extends over a larger area, this can be done by establishing a mean distance. The estimation of the complex number must be carried out on the basis of a necessarily limited number of distance or range sections, so that an error that changes over time occurs, which results in a reduction in the improvement in the signal-to-noise ratio compared with a non-adaptive suppression, which works with a clutter or interference signal at an average Doppler frequency equal to zero. In tests carried out, it was found that this reduction or this loss is very small and, in the special case, was less than 1.2 dB with correlation coefficients between 0.95 and 0.995.

It can be seen that in the case of a simple canceller, the values that are needed to lay fn around the zero-position of the frequency response to the frequency, and I - e ^'2 - ^{T' r} ° Tsind. Using these values results in a relationship between the output signal Vu (f) of the suppressor and the input signal V (f) , which is given by the following equation:

V (Q [X -exp {-] 2π (FF ₀ ) 7]
This then results in:

v, (f)

10

This corresponds to the frequency behavior of a simple suppressor with values of 1 and - 1 centered \ s on the frequency //>

As in Fig. 2, it is possible to build a multiple suppressor in which the zeros in the frequency response are each placed or centered on the frequency fa , simply by connecting several simple suppressors in cascade with one another, with the zero point for each suppressor is placed or centered on the frequency fo.

Referring to FIG. 1 will now be detailed the operation of the system embodying the invention is described.

The incoming complex video signal V, is fed to the circuit D, which causes a delay T corresponding to the repetition time. For this reason, signals V ₁ and V2 are simultaneously present at points 1 and 2, which represent the input signals of two successive runs. The operator C converts the complex signal V _t into the conjugate complex signal Vt *, which is then fed to one input of the multiplier circuit Mi, at the other input of which the signal V ₂ is applied. The multiplier circuit M \ supplies a complex output signal Vi * V2, which complex signal according to the above explanations (cf. equation 1) allows the Doppler phase to be determined.

The output of the multiplier circuit M \ is connected to a series circuit of delay circuits, each of these delay circuits or each delay element generating a delay ν which corresponds to the width of the area of the resolution space element. In the figure, four such delay elements R \ are shown only as an example. At the output of the multiplier and the multiplier circuits M \ are values of the product Vi * V? available that take into account successive areas of the resolution space elements. The value or weight estimation is carried out with the aid of the adder 5 by adding the signals Vi * V ₂ , with the exception of the signal which is present at the output of the second delay element R \ , for a reason which will be explained in more detail later is explained.

The output signal of the adder 5 is normalized to a value 1 with the aid of a coherent limiter L , which in this way supplies the estimated value & ^φ ο. The suppressor element E receives the delayed signal V ₂ at an input via the delay element R ₂ with a delay of 2r, ie with a delay that corresponds to twice the value or width of the range resolution cells. The signal Vi is at the second input of the suppressor Fan after this signal was delayed by 2r by a second delay element R ₂ and was evaluated with the factor Β ^φ ο by the multiplier circuit M _2.

Because of the delay elements R _2, the suppressor E acts on video signals which originate from two successive passes and which were already at their input a time span corresponding to 2r before the instantaneous signal V 1.

It must be pointed out that it is absolutely necessary to avoid that the weighting applied to the multiplier circuit M ₂ is obtained by using a video signal which is simultaneously with the signal applied to the input of the suppressor, that weighted with 1 as this would lead to the useful signal being partially deleted. For this reason there becomes'; Signal which leaves the central circuit of the chain of delay elements /? I and which is delayed in the same way as the signal which is passed through the delay elements R ₂ , does not, as already mentioned above, reach the adder S and for this reason does not take part in the evaluation e '* »so that the aforementioned undesirable surge effect is avoided.

In the case where the number of delay cells Rt is not four, as shown in FIG. 1 was only assumed for the sake of simplicity, but the number of delay elements is generally π, must pass through each delay element R ₂

a delay of y τ can be obtained. As has already been stated, in order to avoid partial cancellation of the useful signal, it is in fact necessary for the delay through the delay elements R _{2 to be} equal to half the delay obtained through the entire chain of delay elements /? I.

F i g. 3 shows another embodiment of the circuit according to FIG. 1, in which an N- subject suppressor is used, which consists of a cascade of N individual suppressors, each one with an adaptation evaluation which is the same as that provided by a single estimation block B.

In a further embodiment, the suppressor can be replaced by a recursive MTI device with evaluations that depend on the estimated frequency / d in order to set the zero point of the frequency response or frequency response of the MTI device to Fd . A block diagram of this embodiment is shown in FIG. 3 shown.

It should be noted that Figs. 1, 2 and 3 only schematic representations of the used Reproduce principle, since these figures in order to achieve greater simplicity in the description of the electrical signals and their composition from the two components, namely the real part and The imaginary part does not show the (components) actually exist, since these are complex Sizes

4 therefore shows a block diagram similar to that A block diagram of Fig. 1, but showing the circuit implementation necessary to achieve both mentioned components of the signal must be taken into account. In this figure the same reference numerals have been used as in Fig. 1 chosen to show those operations or switching elements that have similar functions as in Fig. 1 have.

In FIG. 4 was created with the symbols x and y, which are in Phase or the 90 ° shifted component of the

incoming video signal V, designated.

Each of these components is delayed by a time period of T, which is equal to the repetition period, with the aid of the delay element D.

The complex signal which is present at the inputs of the two circuits D is designated with V ₂ and the signal at the outputs of these two circuits D with Vi, in accordance with FIG. 1.

The sign of the delayed imaginary component of the signal is reversed by an inverter / and then forms the signal V ₁ * together with the pure components of the delayed signal. which conjugation complex is to the signal Vi. The signal Vi * is then fed to the complex multiplication circuit M \ , which is also fed at the same time by the incoming video signal with the two components x and y \ .

The components of the signal V \ * V _{2 which} are in phase and are phase shifted by 90 ° are present at the output of the multiplication circuit. Each of these components is fed to a series circuit of delay elements /? I

An adder S then adds the in-phase components (real part) of the signal Vi * V ₂ , which are supplied by the multiplication circuit M _t and the delay elements Rt , with the exception of the signal which is present at the output of the second delay element. The reasons for this have already been explained above.

Similarly, a second adder adds the corresponding components that are 90 ° out of phase (Imaginary part) of the delayed signals.

The two signals present at the outputs of the two adders then deliver, after previous normalization, which is carried out by the limiter L , the estimated value of & ί ^φ ο, or in other words the adaptation weight or the adaptation evaluation in its two components. One of the two suppression elements E receives at one input a component of the signal V ₂ , which has been delayed by the circuit R ₂ by the time 2r, ie by a time which is equal to twice the width of the range resolution cells. The other input of the same suppression element E the corresponding component of the output signal is fed to the complex multiplier circuit M _2, the inputs of which are supplied with the components of the signal Vi, each component also being delayed by a delay circuit R ₂ by the aforementioned amount of time of 2r. The second suppression element E acts in a similar way on the other component of the signal V ₂ , which was also previously delayed by a further delay circuit R ₂ , and on the corresponding component of the output signal of the multiplier circuit M ₂ . It must be taken into account here that the delay circuits R ₂ generate a time delay corresponding to 2r when the number of delay elements R \ equals 4. As already stated, there is a value for the delay period

to choose from -γ τ for the delay circuits R ₂ if the number of delay elements R \ is equal to η

As mentioned above, the multiplier circuit M ₂ is supplied with two components of the estimated and normalized value of the signal Vi * V ₂ = Β ^φ ο which forms the output signal or the adaptation evaluation of the suppressor

The construction of the two complex multiplier circuits M 1 and M ₂ is shown in greater detail in FIG. 4a shown.

The symbols IR, 1 /, 2.R and 2 / represent the real and Designated imaginary components of the two signals that are subjected to the multiplication. UR and UI denote the corresponding components of the signal which is present at the output of the multiplication circuit.

The multiplication circuit consists of four usual single multiplication circuits ii, 12, i3 and 14. The first (11) of these single multiplication circuits processes the two real components \ R and 2R of the input signals, while the second single multiplication circuit 12 takes into account the two corresponding imaginary components I / and 2 / . The outputs of the individual multiplication circuits 11 and 12 are connected to one another via an adder circuit 51.

which also has a conventional construction and which then supplies the real component UR of the output signal of the complex multiplication circuit.

The single multiplier circuit 13 supplies a product of the real component IR and the imaginary component 2 / of the input signals, while the single multiplier circuit 14 supplies the product of the components 1 / and 2R of these signals.

The output signals of the individual multiplier circuits 13 and 14 represent after a corresponding addition the imaginary component through the adder circuit S 2 of the output signal of the complex multiplication circuit.

The system according to the invention, which is shown in FIG. 4 is shown in its preferred embodiment be built with digital components or construction elements, with all the advantages that these Technology delivers.

In a typical embodiment using digital techniques, four bits were used to represent the proportions of the complex quantities that occur during operation, which increases the complexity of the circuit was kept within limits without thereby reducing the Improvement in the signal-to-noise ratio occurred in the case of a single suppressor

If the aim is to use a multiple suppressor, it may be advantageous to use a larger one Number of bits to use.

In a four-sit version, five printed circuit cards or circuit boards of 213.3 mm χ were used 196.8mm was used, each board being able to hold 45 micro-logic elements to accommodate the Part of the circuit that carries out the valuation estimate. indicated that all operators, multipliers, adders, delay elements, inverters and suppression and blanking elements are conventional and well known to those skilled in the art. For this Basically, a detailed description of these components was not given. As for the coherent limiter If so, programmable read-only memories (PROM) were used for this. These memories were used programmed according to the input-output function that was aimed for, whereby in the memory cells, which corresponded to the various input values indicated the values of the desired output signal became. In other words, the input signal represents the address of the memory cell in which the

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corresponding output signal is input.

All the elements necessary to manufacture the items already described Preferred embodiments are required are commonly available and will be generic on a relatively large scale in integrated form (MSI) from companies such as Texas, Fairchild, and others manufactured.

The delivery was explained above on the basis of special embodiments. It is understood, however, that Modifications and additions to both the components and the logic circuits used are possible, and that thereby the inventive idea is abandoned.

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Claims (8)

Patent claims: 1. System for suppressing unwanted echoes in a coherent pulse radar, characterized in that the suppression of unwanted echoes is carried out by adaptation or adjustment, namely by using a variable evaluation which is obtained by processing two complex video signals, which of two successive samples originate and one of which is converted into the complex conjugate video signal, then the complex conjugate signal is multiplied by the video signal of the other sample and the signal thus obtained is subjected to an even number of successive delays, each of which is equal to Width of the distance resolving element , and the signals delayed in this way are summed, with the exception of the signal whose delay corresponds to the mean value of the successive delays, and where the sum, preferably after normalizing the sum signal to 1, results in the var iable evaluation is obtained that with the variable evaluation the video signal from the one sample is multiplied before it is fed to an input of a suppressor, at the other input of which the video signal of the next sample is applied with a rating of 1, and that the video signals of both samples to a period of time equal to the width of the range resolution space element multiplied by half the number of delays. 2. System according to claim 1, characterized in that the video signals of two successive scans are applied simultaneously to the input or output of a delay element (D) which has a delay corresponding to the repetition time of the radar. 3. System according to claim 1 or 2, characterized in that the suppressor consists of several individual suppressors (Eu £ 2, Em) connected in cascade, each being given the same rating. 4. System according to claim 3, characterized in that the output signal of a single suppressor (E \) the first input of a subsequent further single suppressor (£ 2) and, preferably after a delay by a delay element (D), multiplied by the evaluation of the second input of the subsequent single suppressor (Ei) is fed. 5. System according to claim 3, characterized in that the suppressor of an MTI circuit, is preferably formed by a recursive MTI circuit. 6. System according to one of claims I to 5, characterized in that the two components, the real and imaginary components of the incoming video signal each to a delay element be supplied with a time delay corresponding to the repetition time of the radar that the output signals of these delay elements after a reversal of the imaginary component through an inverter two inputs of a first complex multiplication circuit are fed, whose both other inputs with the real or imaginary part of the incoming video signal directly applied that the outputs of the complex multiplication circuit of a first or second Delay as well as Adiiierschaltung are supplied, each of which initially successive and undertakes equal delays corresponding to the width of the range resolution space element and each of which then adds the delayed signals, and with the exception of the one signal, which has a medium delay, that the output signal these first and second delay and addition circuits the two inputs of a Limiter circuit, preferably a coherent limiter, that the two outputs this limiter is connected to the inputs of a second complex multiplier circuit are, the other two inputs of which are the output signals of the first two delay elements are fed via two second delay elements, each of which is the one already mentioned Average delay has that the two outputs of the second multiplier circuit respectively are connected to one of the two inputs of two suppressor elements, the two of which other inputs the real part or imaginary part of the incoming video signal after a delay by two further delay elements with a delay time equal to the mean delay are supplied that the output signal of the two suppressor elements, the output signal of the System with its two components, real part and imaginary part. 7. System according to claim 6, characterized in that all operators or components are digital work. 8. System according to claim 7, characterized in that the limiter of a programmable Read-only memory (PROM) is formed.