DE2726700A1 - SYSTEM FOR SUPPRESSION OF UNWANTED ECHOS FROM A PULSE RADAR - Google Patents

Description

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June 13, 1977
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SELENIA INDUSTRIE ELETTRONICHE ASSOCIATE S.ρ.Α., Via Tiburtina, Km 12,400-00131, Roma, Italy

System for suppressing unwanted echoes in an impulse radar

The invention relates to a system for suppressing undesired Echoes in a KohUrent impulse radar through adaptation techniques. In particular The present invention relates to a system in which the suppression or deletion of unwanted echoes by means of adaptation techniques can be performed where these echoes are caused by targets moving at a certain speed relative to the radar · The entirety of these unwanted echoes that for example, caused by reflections from the environment, the sea, rain, etc., is referred to as "clutter".

The problem of clutter suppression in radar systems was raised addressed in previous techniques through the use of of so-called MTI suppressors (Moving Target Indicators). Such oppressors are basically nothing more than filters, their parameters

709852/0895

Accounts: Bayerische Vereinsbank (sort code 750 200 73) 5 839 300 Postscheck München 89369-801

Place of jurisdiction is Regensburg

- * "777670Q

have been established once and for all.

The functionality of these suppressors is based on the analysis of the Doppler signal, which is obtained from the Uadar echo as well as from a Coherent generator. The usual MTI devices are designed so that the Frequency response is zero when the Doppler frequency is zero, which leads to the fact that only those unwanted echoes are deleted that are generated by targets that are not moving relative to the radar.

The deletion of echoes also turned out to be a particular problem, originating from targets moving relative to the radar. Such echoes are generated, for example, by kegen, by the sea, dust clouds, etc. evoked. Under such conditions the usual MTI devices are with a fixed evaluation not suitable to provide a sufficient mean improvement in the signal-to-clutter ratio. To the first To solve these problems, the so-called AMTI system (Airborne Moving Target Indicator System) as an indicator for moving Targets for moving radar. With these suppressors the relative speed becomes the movable platform compensated by the fact that the frequency of the coherent oscillator is varied so that a Doppler frequency from zero for fixed goals.

_t With the AMTI devices, the frequency of the coherent oscillator can be changed at most once per scan or deflection. Therefore, if there are clutter caused by the terrain and by rain at different distances during the same scan, an AMTI device allows an effective suppression of the stronger clutter, but only a slight suppression of the remaining clutter. In case of ! stationary radar and moving clutter could so far still be found a satisfactory solution, in particular not within a suppression that works according to the MTI system.

709852/0896

ORIGINAL INSPECTED

Instead, other techniques were used, such as batteries of Doppler filters, but these resulted in very complex circuits.

The object of the invention is to avoid the disadvantages mentioned above and to show a system, which with simple means the suppression of unwanted echoes allowed, both of those echoes that from targets that are stationary to the radar as well as from targets Targets originate that have a non-zero speed relative to the radar.

To solve this problem, a system is proposed according to the invention, which is built with a common suppressor, with one input with a constant weighting equal to 1 and an input is subjected to a weighting which varies by adaptation or equalization can be. The evaluation is variable in such a way that the frequency behavior or the frequency characteristic can be seen from one glance to the next assumes the value zero for a value of the Doppler frequency which is equal to the mean value of the frequency of the unwanted echoes.

709852/0896

ORIGINAL INSPECTED

~ ^Λ ~ 272670Ü

The invention and its mode of operation are described below with reference to the Figures described using exemplary embodiments. Show it:

Fig. 1 is a block diagram of a system incorporating the invention, this block diagram being a simple illustration of how it works the invention provides;

Fig. 2 «in a block diagram similar to FIG. 1, in which a method of the Use of a multiple suppressor is shown;

Fig. 3 is a block diagram of a system embodying the invention, in which the suppression by a standard recursive MTI device he follows;

Fig. 4 in a block diagram similar to Fig. 2, but in which the complex Form of the incoming radar signal / detection is carried, whereby the operators are shown acting on the two components, phase and frame, of the signal;

FIG. 4a is a detailed block diagram of the complex amplifier of FIG

Fig. 4.,

In order to make the operation of the circuit understandable, follows a brief mathematical introduction to the main quantities involved in Work of the circuit occur.

Around the mean Doppler frequency of the strength spot or interference signal f _ß or - in other words, the mean value of the Doppler phase

Φ = 2 ^ f T (T s repetition time) to be able to estimate. Sufficient ι ⁰ ° samples _t

es, the clutter voltages of two successive passes or / (sweeps) to consider even if the suppression is more than two Pass «is used. If, therefore, with V. and V «the complex video voltages corresponding to the repetition time or repetition period occur one after the other and at the input of the MTI device

Γ -ι 2 i φ are present, then E £ V ^ VgJ = S y ^{c β} °

709852/0896

ORIGINAL INSPECTED

- * - 272670Ü

2
Where: C = mean value of the clutter ? ■, = correlation coefficient

V / = the conjugate complex value of V. E [V * V ₂ I = the estimated value of the product The Ooppler phase is given by the following equation In order to determine the Doppler phase φ _n or, even more precisely, the com-

ί i D
plex number e ', it is necessary to estimate the complex size or the complex product V * V _2. For an interference spot or for an interference signal which extends over a larger area, this can be done by defining an average distance. The estimation of the complex number must be carried out on the basis of a necessarily limited number of distance or range sections, so that an error that changes over time occurs, which results in a reduction in the improvement in the signal-to-noise ratio compared with a non-adaptive suppression, which works with a clutter or interference signal at an average Doppler frequency equal to zero. In tests carried out, it was found that this reduction or this loss is very small and in the special case was less than 1.2 dB with correlation coefficients between 0.95 and 0.995.

From this it can be seen that in the case of a simple suppressor, the values that are required to set the zero position of the frequency response to the frequency f _Q are 1 and -e ″ oT. When using these values, there is a relationship between the output signal V (f) of the suppressor and the input signal V. (f), which is determined by the following

709852/0895

ORIGINAL INSPECTED Equation is given: V ₁ (O = V. (f) [i - e _xP (-j 2 T (ff _D ) τ] This then results in:

= 1 - exp (j2T (ff-f _D ) T)

and

This corresponds to the frequency behavior of a simple suppressor with Values of 1 and -1 centered on the frequency f ~.

As shown in Fig. 2, it is possible to use a multiple suppressor build in which the zeros in the frequency response are each placed or centered on the frequency f_, simply by the fact that several simple suppressors can be cascaded with one another, with each suppressor the zero is placed on the frequency f_ or is centered.

Referring to Fig. 1, the operation of the the system comprising the invention described.

The incoming complex video signal V. is fed to the circuit D, which causes a delay T corresponding to the repetition time. For this reason, signals V- and V ^ are present at points 1 and 2 at the same time, which represent the input signals of two successive cycles. The operator C converts the complex signal V ₁ into the conjugate complex signal V *, which is then fed to one input of the multiplier circuit M ^, at the other input of which the

70985 2/0895

ORIGINAL INSPECTED

Signal V. is present. The multiplier circuit M. supplies a complex output signal V ₁ * V-, which complex signal in accordance with the above explanations (cf. equation 1) allows the Doppler phase to be determined.

The output of the multiplier circuit M. is connected to a series circuit of delay circuits, each of these delay circuits or each delay element generating a delay T which corresponds to the width of the area of the resolution space element. In the figure, four such delay elements R. are shown only as an example. At the output of the multiplier and the multiplier circuits M. values of the product V ₁ * V ~ are available which take into account successive ranges of the resolution space elements. The value or weight estimation is carried out with the aid of the adder S by adding the signals V * V_, with the exception of the signal which is present at the output of the second delay element R ₁ , for a reason which will be explained in more detail later will.

The output signal of the adder S is normalized to a value 1, and

with the help of a coherent limiter L, which in this way delivers ^{the estimated value e * * D.} The suppressor element E receives at an input via the delay element K ~ the delayed signal V «with a delay of 2 T _f, ie with a delay that corresponds to twice the value or width of the range resolution cells. : The signal V. is present at the second input of the suppressor E after this signal has been delayed by 2 t by a second delay element R "and has been evaluated with the factor E '* ^ by the multiplier circuit M".

Because of the delay elements R ″, the suppressor E acts on video signals that originate from two successive passes and

709852/0895

ORIGINAL INSPECTED

-> - 27? R70Ü

at the input already a time span corresponding to 2 T before the instantaneous signal V. systems.

It must be pointed out that it is imperative to avoid the fact that the evaluation applied to the multiplier circuit M- is obtained by using a video signal which is associated with the signal present at the input of the suppressor is simultaneous, that it is evaluated with 1, since this would lead to the fact that the useful signal would also be partially deleted. Because of this, the signal which the middle circuit of the chain of delay elements R. leaves and which is delayed in the same way as the signal which is passed through the delay elements R «, not, as already mentioned above, arrives at the adder S and out of this

i Φ D

Basically in the evaluation e does not participate, so that the mentioned undesirable Deletion effect is avoided.

In the event that the number of delay elements or cells R. is not four, as was assumed in FIG Delay of χ T can be obtained. As already expressed, it is in fact necessary, in order to avoid partial deletion of the useful signal, that the delay through the delay elements R _{9 is} equal to half of the delay through the entire chain of the _; Delay elements R. is obtained.

FIG. 3 shows another embodiment of the circuit according to FIG which uses an N-subject suppressor, which is made up of a cascade of There are N individual suppressors, each individual with an adjustment that is the same as that provided by a single estimation block B. will.

709852/0895 ORIGINAL INSPECTED

- £ - 272B700

In a further embodiment, the suppressor can be replaced by a recursive MTI device with ratings that depend on the estimated Frequency f_., In order to set the zero point of the frequency response or frequency * gear of the MTI device to f_. to be determined. A block diagram of this implementation is shown in FIG. 3.

It should be noted that FIGS. 1, 2 and 3 are only schematic Representations of the principle used, as these figures To achieve greater simplicity in the description, the electrical signals and their composition from the two components, namely the real part and the imaginary part do not show the (components) actually present, since these are complex quantities.

Fig. 4 therefore shows a block diagram similar to the block diagram of Fig. 1, but showing the circuit design which is necessary to take into account both mentioned components of the signal. to show those operations or switching elements that have similar functions | nen as in Fig. 1 have

In FIG. 4, the symbols x. or y. the in phase or the around 90 shifted component of the incoming video signal V.

Each of these components is delayed by a period of time T, the is equal to the repetition time, with the help of the delay element D.

The complex signal that occurs at the inputs of the two circuits 0 is present, is denoted by V «and the signal at the outputs of this two circuits 0 with V., in accordance with Fig.

709852/0895

9RIGINAL INSPECTED

- * - 2 7? R 7 OO

The sign of the delayed imaginary component of the signal is reversed by an inverter I and then, together with the real components of the delayed signal, forms the signal V *, which is the conjugation complex to the signal V. The signal V * is then _{fed to the complex multiplication circuit M 1} , which is simultaneously also processed by the incoming video signal with the two components x. and y. is fed.

The components of the signal V. * V_ which are in phase and are phase shifted by 90 are present at the output of the multiplication circuit. Each of these compos «
leads.

Components are assigned to a series circuit of delay elements K.

An adder S then adds the in-phase components (i; ealteil) of the signal V * V ", that of the multiplication circuit M. and the delay elements κ, with the exception of the signal which is applied to the output of the second delay element. The reasons for this have already been explained above.

Similarly, a second adder adds the corresponding, um 90 phase-shifted components (imaginary) of the delayed signals.

The two signals present at the outputs of the two adders deliver then, after previous normalization, carried out by the limiter L. becomes, the estimated value of e '*, or in other words the adjustment weight or the adjustment score in its two components. One of the two suppressor elements E receives at an input a component of the signal V ~, which is transmitted by the circuit K «to the Time 2 T has been delayed, i.e. by a time equal to twice that Value is the width of the range resolution lines. The other input of the same suppression element E is the corresponding component of the Output signal supplied to the complex multiplier circuit M_, whose

709852/0895

ORIGINAL INSPECTED

272R700

Inputs with the components of the signal V. are applied, each component is also delayed by a delay circuit K ″ by the amount of time of 2 Γ already mentioned above. The second suppression element E acts in a similar way on the other component of the signal V., which was previously also delayed by a further delay circuit K_, and on the corresponding component of the output signal of the multiplier circuit M ~. It must be taken into account here that the delay circuits R- generate a time delay corresponding to 2 T when the number of delay elements U. is equal to four. As has already been explained, a value of r T for the delay circuits K. should be selected for the delay time if the number of delay _{elements K 1 is} equal to η.

As mentioned above, the multiplier circuit M_ becomes two components the estimated and normalized value of the signal V * V. = E supplied, which the adjustment signal or the adjustment evaluation of the The oppressor.

The construction of the two complex multiplier circuits M. and M-ist shown in more detail in FIG. 4a.

Here with the symbols IR, II, 2R and 21 are the real and imaninary components of the two signals which are subjected to the multiplication. UR and UI are the corresponding components of the signal, which is present at the output of the multiplication circuit.

The multiplication circuit consists of four customary single multiplication circuits 11, 12, 13 and 14. The first (11) of these single multiplication circuits processes the two real components IR and 2R of the input signals, while the second single multiplication circuit 12 takes into account the two corresponding imaginary components II and 21

709852/0895

ORlGiNAL INSPECTED

does. The outputs of the single multiplication circuits 11 and 12 are Connected to one another via an adding circuit SI, which is also a Has the usual construction and which then has the real component UR of the Output signal of the complex multiplication circuit provides.

The single multiplier circuit 13 supplies a product of the real Component IR as well as the imaginary component 21 of the input signals, while the single multiplier circuit 14 is the product of the components II and provides 2R of these signals.

The output signals of the individual multiplier circuits 13 and 14 set after a corresponding addition by the adding circuit S2, the imaginary component of the output signal of the complex multiplying, circuit.

The system according to the invention, which is shown in FIG. 4 in its preferred AusfUhrungsform is shown, can with digital components or structural elements with all the advantages that this technology provides.

In a typical embodiment that uses digital techniques four bits were used to represent the proportions of the complex quantities that occur during operation, which increases the complexity of the circuit was kept within limits without thereby reducing the improvement in the signal-to-noise ratio in the Case of a single oppressor occurred.

If the aim is to use a multiple suppressor, can it may be advantageous to use a larger number of bits.

In a four-bit version, five printed circuit cards or

709852/0895

ORIGINAL INSPECTED

Printed circuit boards measuring 213.3 mm by 196.8 mm were used, each board being able to accommodate 45 micro-logic elements to create the part of the circuit zv that does the evaluation estimate (β). At this point it should be pointed out that all operators, multipliers, adders, delay elements, inverters and suppression or blanking elements are of a conventional type and are well known to those skilled in the art. For this reason, a detailed description of these components has not been provided. As far as the coherent limiter is concerned, programmable read-only memories (PROM) were used for this. These memories were programmed according to the input-output function that was aimed for, the values of the desired output signal being specified in the memory cells that corresponded to the various input values. In other words, the input signal represents the address of the memory cell in which the corresponding output signal is input.

All elements preferred for making those already described Embodiment are required, are widely available and will be generally to a relatively large extent in integrated form (MSl) manufactured by companies such as Texas, Fairchild, and others.

The invention was explained above using special embodiments. It goes without saying, however, that modifications and additions are possible both in the components and in the logic circuits used are, and that thereby the inventive idea is abandoned.

709852/0895

ORIGINAL INSPECTED

L e r s e i t e

Claims (8)

? 7? R 7 η Ü Claims IJ system for suppressing unwanted echoes in a coherent pulse radar, characterized in that the suppression of unwanted echoes is carried out by adaptation, namely by using a variable weighting obtained by processing two complex video signals which originate from two successive scans and one of which is converted to the conjugate complex video signal, the conjugate complex / signal then being multiplied by the video signal of the other sample and the signal thus obtained being subjected to an even number of successive delays, each of which is equal to the width of the distance resolution element is, and wherein the signals delayed in this way are summed, with the exception of that signal whose delay corresponds to the mean value of the successive delays, and wherein the summation, preferably after normalization of the sum signal to 1, the vari Able evaluation is obtained that with the variable evaluation the video signal from the one sample is multiplied before it is fed to an input of a suppressor, at the other input of which the video signal of the next sample is applied with a rating of 1, and that the video signals of both samples to a period of time equal to the width of the range resolving space element multiplied by half the number of delays. 2. System according to claim 1, characterized in that the video signals two successive scans are present at the same time at the input or output of a delay element (D), which is a delay according to the repetition time of the kadar. VU9S52 / Ü895 ORIGINAL INSPECTED - * 3f- 277R700 3. System according to claim 1 or 2, characterized in that the suppressor consists of several individual suppressors (E ₁ E_, E) connected in cascade, each being given the same rating. 4. System according to claim 3, characterized in that the output signal of a single suppressor (E.) the first input of a subsequent one further individual suppressor (E ") and, preferably after a delay by a delay element (θ) multiplied by the Evaluation of the second input of the subsequent individual suppressor (E-) fed wild. 5. System according to claim 3, characterized in that the suppressor from an MTI circuit, preferably from a recursive MTI circuit is formed. 6. System according to any one of claims 1 to 5, characterized in that the two components, the real and imaginary parts, of the incoming video signal each have a delay element with a time delay are supplied according to the repetition time of the radar, that the output signals of these delay elements after a reverse! tion of the imaginary component are fed to two inputs of a first complex multiplication circuit by an inverter, the both other inputs are directly acted upon with the real or imaginary part of the incoming video signal that the outputs the complex multiplication circuit are supplied with first and second delay and adder circuits, each of which first makes successive and equal delays, each corresponding to the width of the distance resolution space element, and each of which then adds the delayed signals, with the exception of the one signal, which has an average 7ü986> / 089S ORIGINAL INSPECTED - ur- 272B70U Has delay that the output signal of these first and second delay and addition circuits are fed to the two inputs of a limiter circuit, preferably a coherent limiter, that the two outputs of this limiter are connected to the inputs of a second complex multiplier circuit, the other two inputs of which are the Output signals of the first two delay elements are fed via two second delay elements, each of which has the aforementioned average delay that the two outputs of the second Hu ¹ multiplier circuit are each connected to one of the two inputs of two suppression elements, the other two inputs of which are the real part or the real part. The imaginary part of the incoming video signal is supplied after delay by two further delay elements with a delay time equal to the average delay so that the output signal of the two suppressor elements is the output signal de s system with its two components, real part and imaginary part, forms 7. System according to claim 6, characterized in that all operators or components work digitally. 8. System according to claim 7, characterized in that the limiter is formed by a programmable read-only memory (PROM). 709852/0895