DE2715750C3 - Test circuit for a microcomputer - Google Patents

Description

The invention; relates to a circuit of the type specified in the preamble of claim 1

A new component, the microprocessor, has appeared on the electronics market for several years. He contains a computer control and arithmetic unit on a single semiconductor chip under association several thousand components. In the arithmetic unit of the microprocessor, arithmetic and logical Operations performed; the control unit only ensures that the commands entered.

The microprocessor represents the heart of a microcomputer, depending on the task at hand in connection with the microprocessor a more or less large number of further highly integrated Components is used. Since many microprocessors do not have the necessary clock is integrated in the module, the clock power supply is implemented by an external component. Another essential functional unit of the microcomputer is the system memory, which is mostly divided is in a program memory, in which the for the respective purpose of the microcomputer required user program, i.e. protected against power failure, is included. As storage are used in cases of read-only memories with random access (ROM). The other part of system memory is the data repository that stores information that is constantly changing. For this use case read / write memories with random access (RAM) are used.

Further components for the construction of the microcomputer are the input and output stones, over which the Microcomputer is connected to the environment. The system memory (s) and the input and output units of the microcomputer are connected to the microprocessor on the one hand via a bidirectional data bus, hereinafter referred to as data bus, and on the other hand via an address bus (address bus) tied together. Data can optionally be entered or output via the data collector line. to special time slots in which it is ensured that no data is yet available on the data bus are, the so-called status information is also sent to the status memory by the microprocessor also output via the data bus, with this information at later times serve for tax purposes. These and other well-known technical features of microprocessors are described in the company's corporate publication INTF.I. CORPORATION under the designation "From CPU to software", No. MCS-0Ö4-474 / 25K, 1974.

To carry out a software test on an application-specific microcomputer, the Numerous control signals for influencing the program flow are available to the user. For evaluation the various program states, e.g. B. from an externally caused program stop, is the Knowledge of the information contained in the internal registers of the microprocessor is essential because this information contains important data and markings that influence the program run. However, these internal registers of the microprocessor cannot easily be marked externally.

The information from the internal registers of the microprocessor is now available during execution some commands during certain cycles of operation on the data bus; an appraisal of this However, information is not sufficient, since it depends on chance whether it really is in a given period of time all internal registers of the microprocessor are taken into account as part of the desired test. With In other words, with such a procedure there is no completeness of the Tests guaranteed; Otherwise, repeated activation of the same internal registers would defeat the test additional time burden through unnecessary paperwork.

In order to become independent of the respective user program for a desired software test, it would be conceivable to use a subroutine which, when called, all internal registers of the microprocessor and in this way would ensure that the register test is complete. That Said subroutine would have to be activated from outside by an INTERRUPT, which is otherwise for this function would have to be reserved.

The disadvantage of this method can be seen in the fact that the functions are impaired for the user of the relevant microcomputer occurs, which means that the software test implemented in this way does not for this reason seems suitable.

From DL-PS 1 07 996 a circuit arrangement for data processing systems for displaying and Saving the content of internal control registers in data processing systems known that with a Interruption control are equipped. These too Arrangement has the above disadvantage.

The invention is based on the object of a test circuit for a microcomputer of the initially called type that allows the information of the internal registers of the microprocessor for external purposes, e.g. B. to provide an advertisement, with none Change of the user programming system intended for the microcomputer and no impairment the functioning of the microcomputer itself should occur. Furthermore, the internal registers of the Microprocessor display the same information content before and after executing the test.

According to the invention, the object is achieved by the features specified in the characterizing part of claim 1 solved.

With the aid of this test circuit according to the invention, it is advantageously possible without impairment the functions of the microcomputer to address the internal registers of the microprocessor by command, being a special program for the register reading function can be provided that is not contained in the system memory of the microcomputer, but in the register reading program memory of the typecircuit.

When entering external commands as part of a software test in the regular program sequence

ί the microcomputer must have the current command count of the microprocessor can be saved and changed. Since the instruction counter of the microprocessor is from but cannot be controlled directly from the outside, the command counter can be more advantageous

in a way either with the help of a non-maskable, resp. highest priority interrupt request or by the Looping in a CALL command; to be saved. In In both cases, the command counter of the microprocessor is automatically transferred to a storage bin,

¹ ^ where any change can be made. In this way, for a desired software test from. Starting from the test circuit, a special program is started in the microcomputer at an arbitrary address

- "or to be continued.

Advantageous further developments of the invention are characterized in the subclaims.

An embodiment of the invention is shown in the drawing and will be described in more detail below

-j explained

In order to make the drawing clearer, there are only a few for the microcomputer essential assemblies shown. Dabdi won't Reference is made to a special microcomputer or a special user program, since the The invention is in principle not limited to a specific microcomputer system of the one or more other manufacturer.

A fundamental building block of the microcomputer is

<> the microprocessor CPU itself, to which an external clock generator TG is connected. This clock generates, among other things, the two control clocks Φ 1 and Φ 2. A system memory SSR, an input unit ET and an output unit AT are connected to the bidirectional data bus line DS and to the address bus line AS of the microprocessor CPU. The system memory SSR is used to hold programs and data and, depending on the application of the microcomputer, can consist of several, quite different ones

· 'Save to be established. The same applies mutatis mutandis to the input unit ET, which receives information on a process to be controlled by the microcomputer via input lines EC; several different input units can therefore be provided. So

"Depending on the structure of the microcomputer, several output units can also be provided, which output the information for process control compiled by the microcomputer via output lines AG.

"'■"' Another essential component of the microcomputer is a status memory ZR, which is also connected to the data bus line DS of the microprocessor CPi /. The status memory ZR has the task of each at the beginning of each cycle

^{1) 11 of} the Daiensubeline DS existing status information to be temporarily stored. Dsr Zjstandsspeicher ZR is also with the clock generator TG to take over the control clock Φ 1 and also with a control signal output A 1 CPU of the microprocessor

'■''sors CPUiuv taking over a synchronization signal SYNC connected. The logic circuit VSG after the status memory ZR exists! in practice in a known manner from a number of

Linking elements which have the task of linking the status information stored in the status memory ZR with control signals DBIN or WR , which are output via the outputs A 2CPU or A 3CPU of the microprocessor CPU . The control signals formed in the logic circuit VSG IOW, Lor, MEMR and MEMW meaning "output unit write" read "input unit" read "memory" and write "memory" are the outputs A \ to A 4 of the logic circuit laminated to the these outputs assigned switching amplifiers SCR 1 to SCR 4, which are part of the test circuit. As will be explained in more detail below, these switching amplifiers have the task of not allowing any of the control signals supplied to pass through at a certain point in time, so that

or the output unit AT cannot be activated. In this state, no data transfer from or to these facilities is possible.

To block the switching amplifiers SCR 1 to SCR 4, a common blocking signal EXPR from a device UR 1 to be explained in more detail in the test circuit is used. The test circuit for the microcomputer described in its essential assemblies also contains an operation cycle counter MR, the dynamic stepping input EiMR of which is connected to the control signal output A 1 CPU of the microprocessor CPU , which outputs the synchronization signal SYNC before each operation cycle. The operation cycle counter MR has a Steuereingar.g E2MR, to which a related control signal is given to activate the counter. Without this control signal, the operation cycle counter MR is switched off, so that the supplied synchronization signals SYNC cannot advance the operation cycle counter from its basic position.

At the operation cycle counter MR, a first converter UR 1 is connected a programmable read-only memory chip (ROM) in shape, has the task to generate particular control signals in response to the counter position of the operation cycle counter MR, which via the outputs AG 1, AG 2 and AG3 are issued to subordinate institutions. Of these special control signals, the blocking signal EXPR has already been mentioned, which is used, among other things, to block the switching amplifiers SCR 1 to SCF 4. For this purpose, the blocking inputs of these switching amplifiers are connected to the output AG 1 of the converter UR 1. The control inputs ERLSR and EBR of a register reading program memory RLSR and a bidirectional bus driver BR are also connected to this output. With the operation cycle counter MR, a second converter UR 2 is still connected, which addresses the program memory register read RLSR depending on the count of the operation cycle counter MR. A register reading program is output via the bus driver BR mentioned to the data bus DS when the special blocking signal EXPR is present, which then ensures that neither the system memory SSR nor the input or output unit ETIA T can receive or output information.

An embodiment of a register reading program, which is contained in the register reading program memory RLSR and applies to microcomputers based on the system & 4S8080, is shown below.

Dl RST Φ

XTHL DCX H DCX H XTHL PUSH H PUSH D PUSH B PUSH PSW POPPSW POPB POPD POPH El

Disable interrupt
Save command counter

Correction of the command counter

Register contents in
Deposit storage

Outsource storage

Enable interrupt

Another essential component of the test circuit is a memory for register contents SR, which works in conjunction with an address counter AR and is connected by the bus driver BR at the appropriate time to the data bus DS for receiving information from internal registers of the microprocessor CPU . The memory for register contents SR kar ι be designed as read-write memory with random access (RAM).

To start the test circuit, a key contact TT is provided which, in conjunction with a resistor and a non-element NGc'.n, controls the AND element UD \ in such a way that a logic 1 is only applied to the non-element NG when the key contact 7T is closed, i.e. actuated. On the other hand, the AND element UD 1 is connected to that output A XZR of the status memory ZR which outputs the temporarily stored status information M 1. In this case, the microprocessor CPU has stated that the current cycle is the read cycle of the first command byte. A monostable trigger element MKD is connected to the AND element UD 1 with its dynamic control input EMKD, which controls a bistable trigger element BKD via its set input S. The reset input /? Of the bistable flip-flop SAkD is connected to the output AG 3 of the first converter UR 1. On the output side, the reset input of the address counter AR is also connected to the monostable multivibrator MKD. As a result, when the button contact 7Timers AR is pressed, a predefined basic setting is enforced. _o ? n. The incremental input FAR of the address counter AR is connected to the output of a further AND element UD2 . One input of the AND element UD2 is connected to the output AG2 of the first converter UR 1 and the second input is connected to the output A 4 of the logic circuit VSC. This ensures that the control signal MEMW of the first converter is given UR 1 output control signal as a stepping signal to the address counter of the logic circuit AR VSG at the appropriate time by means of the outcome AG 2 is achieved. Since the output of the AND element UD2 fen.er is connected to the memory for register contents SR , the output signal of the AND element UD 2 in the mentioned memory SR serves as a write signal, in which the information transmitted by the bus driver BR is below that of the address counter AR specified address can be saved.

The output of the bistable Kippgüedes BKD is with

the entrance ELMR the operation cycle counter MR and having an ^E: ngang EUR 1 of the first converter UR! tied together. This ensures that both the operation cycle counter MR and the first converter UR 1 are only actively switched when the bis'able flip -flop -, BKD : is set.

The mode of operation of the test circuit described in its structure in connection with the microcomputer is the following:

When the key contact TT is actuated, when the status information Mi "read operation code" is present, the monostable flip-flop MKD is moved into the unstable position. The completed actuation of the key contact 7T is thus stored for a predetermined period of time. When the monostable flip-flop MKD is switched, the bistable flip-flop BKD is set and thus the operation cycle counter MR is enabled for counting the individual synchronization signals SVWC. Furthermore, the first converter UR 1 evaluates the basic operating cycle counter position on the basis of its release. As a result of the function of the first converter UR 1, what is achieved below is that the program of the microcomputer in the system memory SSR is deactivated at predetermined times. For this purpose, the first converter UR 1 outputs the blocking signal EXPR via the output AG X , namely "read operation code" during each operation cycle. The switching amplifiers SCR 1 to SCR 4 are blocked with the aforementioned blocking signal EXPR , so that the microprocessor CPU is prevented from accessing the system memory SSR. In addition, the blocking signal EXPR switches the operation code of the commands of the register reading program contained in the register reading program memory RLSR via the bus driver BR , which is also activated by the blocking signal EXPR, to the data collection line DS. With such a command supply, the register content of the microprocessor CPU is on the data bus DS during a specific operating cycle. In order to have this * egisierinhaii available for test purposes independently of the further work flow in the microcomputer, the first converter UR 1 activated by the operation cycle counter MR switches the AND element UD 2 in conjunction with the control signal MEM W to output the register contents for the memory SR required write signal. The address counter AR is then incremented. The new address set in this way selects a new memory line in the memory for register contents SR for the next register contents of the microprocessor CPUaxis to be stored.

After all the register contents of the microprocessor CPU have been saved, for which the converter UR 2 supplies the necessary control information for the register reading program memory RLSR , the control signal for resetting the bistable flip-flop BKD is output by the first converter UR 1 via the output AG 3. In this switching position of the bistable flip-flop BKD , the operation cycle counter MR is again set in its inactive initial position MR and the converter UR i is switched off.

The first converter UR 1 then blocks the output of the blocking signal EXPR, so that the register reading program memory RLSR and the bus driver BR are switched off. Due to the absence of the blocking signal EXPR , the switching amplifiers SCR 1 to SCR 4 that were previously blocked are reactivated, so that normal operation of the microcomputer can be resumed.

The information from the microprocessor collected in the memory for register contents SR is available for test purposes; the evaluation of this information is not the subject of the present invention and is therefore not dealt with further.

The use of the test circuit with the operation cycle counter MR, the two converters UR i UR 2 in connection with the register reading program memory RLSR and the memory for register contents SR advantageously allows the use of a register reading program for test purposes, since: is independent of the format of the commands used .

In an advantageous embodiment of the inventive concept: the test circuit also enables the "register writing function", in that after the RcEiiicrinhmtc has been saved in the Kc !! cr; ~ cichcr 'P ^{1 IC} H ^D "f" h! - this stacked storage area can be specifically overwritten and thus Changed contents get there when restoring in the register.

1 sheet of drawings

Claims (4)

Patent claims: 1. Test circuit for a microcomputer, which essentially consists of a microprocessor, to whose data bus a system memory for programs and data as well as input and output units are connected, which are activated by addresses and separate control signals routed via an address bus, as well as with one of the State memory for status information lying on the data bus , characterized in that an operational cycle counter (MR) which can be incremented by synchronization signals (SYNC) of the microprocessor (CPU) and has two downstream converters (UR 1, UR2) is provided, the first converter (URi) having several outputs (AG 1, AG 2, AG 3) for special control signals, of which one output (AG X), which emits a blocking signal (EXPR) after an operating action starting the test circuit during each operation cycle, emits a blocking signal (EXPR) in this test case Register reading program stored in the test circuit under Um The system memory (SSR) loops into the data bus, and is connected to blocking inputs of switching amplifiers (SCR X to SCR 4), which in non-test mode provides the necessary for activating the system memory (SSR) and the input and output units (ET, AT) Control signals (IOW, IOR, MEMR, MEMW) forward that a register reading program memory (RLSR) containing the register reading program is connected to the second converter (UR2), which is used to activate the output (AGX) for the blocking signal (EXPR) of the first converter (UR X) and the output side is indirectly connected to the data bus line (DS) , to which a memory (SR) controllable by an assigned address counter (AR ) for receiving information from the internal registers of the microprocessor (CPU) is also connected indirectly . 2. Test circuit according to claim 1, characterized in that to activate the operation cycle counter (MR) a control input (E2MR) of this counter is connected to the output of a trigger element (BKD) , the set input (S) of which is connected to an AND element (UD X) is controllable, of which one input can be switched by a key contact (TT) and the second input is connected to that output (A \ ZR) of the state memory (ZR) that outputs the state information (MX) that says that the current cycle is the read cycle of a first command byte and that the reset input (R) of the trigger element (BKD) is connected to an output (AG 3) of the first converter (UR X) which characterizes the end of the register reading program. 3. Test circuit according to claim 1, characterized in that an AND element (UD 2) is connected to the incremental input (FAR) of the address counter (AR) , one input of which is connected to the output (AG ) serving to activate the address counter (AR) 2) of the first converter (URi) and the other input is connected to that output (A 4) of a logic circuit (VSG) connected downstream of the auxiliary storage device (ZK), which sends the control signal "write memory" (MEMW) & outputs 4. Test circuit according to claim 1, characterized in that the register reading program memory (RLSR) and the memory (SR) for the information from the registers of the microprocessor (CPU) with the data bus (DS) via a bus driver (BR) are connected by the a control input (EBR) is connected to that output (AGX) of the first converter (UR X) which carries the blocking signal (EXPR)