DE2715750B2 - Test circuit for a microcomputer - Google Patents

Description

The invention relates to a circuit of the im Preamble of claim 1 specified type

A new component, the microprocessor, has appeared on the electronics market for several years. He contains a computer control and arithmetic unit on a single semiconductor chip under association several thousand components. In the arithmetic unit of the microprocessor, arithmetic and logical Operations performed; the control unit only ensures that the commands entered.

The microprocessor represents the heart of a microcomputer, depending on the task at hand in connection with the microprocessor a more or less large number of further highly integrated Components are used because many microprocessors do not have the required clock with is integrated in the module, the clock power supply is implemented by an external component Another essential functional unit of the microcomputer is the system memory, which is mostly divided is in a program memory, in which the for the respective purpose of the microcomputer required user program, i.e. protected against power failure, is included as a memory are used in cases of read-only memories with random access (ROM). The other part of system memory is the data repository that stores information that is constantly changing. For this use case read / write memories with random access (RAM) are used

Further components for the construction of the microcomputer are the input and output stones, over which the Microcomputer is connected to the environment The system memory (s) and the input and output units of the microcomputer are connected to the microprocessor on the one hand via a bidirectional data bus, hereinafter referred to as data bus, and on the other hand via an address bus (address bus) tied together. Data can optionally be entered or output via the data collector line. to special time slots in which it is ensured that no data is yet available on the data bus are, the so-called status information is also sent to the status memory by the microprocessor also output via the data bus, with this information at later times serve for tax purposes. These and other well-known technical features of microprocessors are described in the company publication of INTEL CORPORATION under the designation »From CPU to software «, no. MCS-064-474 / 25K. 1974.

To carry out a software test on an application-specific microcomputer, the Numerous control signals for influencing the program flow are available to the user. For evaluation the various program states, e.g. B. from an externally induced program stop, is the Knowledge of the information contained in the internal registers of the microprocessor is essential because this information contains important data and markings that influence the program run. However, these internal registers of the microprocessor cannot easily be marked externally.

Now, however, the information in the internal registers of the microprocessor is on the data bus when executing certain commands during certain operating cycles; However, an assessment of this information is not enough, because it depends on chance whether in a period considered really all internal registers of the microprocessor <m under the desired test to be considered. In other words, with such a procedure, completeness of the test is not guaranteed; Otherwise, repeated addressing of the same internal registers would put an additional burden on the test due to unnecessary typing.

In order to become independent of the respective user program for a desired software test, it would be conceivable to use a subroutine which, when called, would record all internal registers of the microprocessor and in this way would ensure cue completeness of the register test. That Said subroutine would have to be activated from outside by an INTERRUPT, which is otherwise for this function would have to be reserved.

The disadvantage of this method can be seen in the fact that the functions are impaired for the user of the relevant microcomputer occurs, which means that the software test implemented in this way does not for this reason seems suitable

From DL-PS 1 07 9% is a circuit arrangement for data processing systems for displaying and Saving the content of internal control registers in data processing systems known that with a Interrupt control are equipped. This arrangement also has the disadvantage mentioned above.

The invention is based on the object of a test circuit for a microcomputer of the initially called type that allows the information of the internal registers of the microprocessor for external purposes, e.g. B. to provide an advertisement, with none Modification of the user program system intended for the microcomputer and no impairment the functioning of the microcomputer itself should occur. Furthermore, the internal registers of the Microprocessor have the same information content before and after the execution of the test.

According to the invention, the object is achieved by the features specified in the characterizing part of claim 1 solved

With the aid of this test circuit according to the invention, it is advantageously possible without impairment the functions of the microcomputer to address the internal registers of the microprocessor by command, whereby a special program can be provided for the register reading function, which is not included in the System memory of the microcomputer is contained, but in the register reading program memory of the test circuit.

When entering external commands as part of a software test in the regular program sequence of the microcomputer, the current instruction count of the microprocessor must be saved and changed will. However, since the command counter of the microprocessor cannot be controlled directly from the outside can, the command counter reading can advantageously either with the help of a non-maskable or interrupt request with the highest priority or by looping in a CALL command. In In both cases, the command counter of the microprocessor is automatically transferred to a storage bin, where any change can be made. In this way it can for one desired software test starting from the test circuit in the microcomputer a special one Program can be started or continued at any address.

Advantageous further developments of the invention are characterized in the subclaims

An embodiment of the invention is shown in the drawing and will be described in more detail below explained

In order to make the drawing clearer, there are only a few for the microcomputer essential assemblies are shown. No reference is made to a special microcomputer or a special user program, since the invention is not limited to a certain microcomputer system from one manufacturer or another.

A basic component of the microcomputer is the microprocessor CPU itself, to which an external clock generator TG is connected.This clock generator generates, among other things, the two control clocks Φ 1 and Φ Z.A system memory SSR, an input unit, is connected to the bidirectional data bus line DS and the address bus line AS of the microprocessor CPU ET and an output unit AT connected. The system memory SSR is used to hold programs and data and, depending on the application of the microcomputer, can be composed of several, quite different memories. The same applies mutatis mutandis to the input unit ET, which receives information about a process to be controlled by the microcomputer via input lines EG; several different input units can therefore be provided. Thus, depending on the structure of the microcomputer, a plurality of output units can also be provided, which output the information for process control that the microcomputer has elaborated via output lines AG.

Another essential component of the microcomputer is a status memory ZR, which is also connected to the data bus DS of the microprocessor CPU . The status memory ZR has the task of temporarily storing the status information present on the data bus DS at the beginning of each cycle. The status memory ZR is also connected to the clock generator TG for taking over the control clock Φ 1 and also to a control signal output A 1 CPU of the microprocessor CPUt-wt taking over a synchronization signal SYNC . The logic circuit VSG connected downstream of the status memory ZR consists in practice in a known manner of a number v «n

Linking elements which have the task of linking the status information temporarily stored in the status memory ZR with control signals DBIN or WR , which are output via the outputs A 2CPU or A 3CPU of the microprocessor CPU . The control signals formed in the logic circuit VSG IOW, IOR, MEMR and MEMW mi write meaning "output unit" read "input unit", "memory read" and write "memory" are the outputs Ai to A 4 of the logic circuit VSG to this Outputs assigned switching amplifiers SCRi to SCR 4 , which are part of the test circuit. As will be explained in more detail below, these switching amplifiers have the task of not allowing any of the supplied control signals to pass at a certain point in time, so that the system memory SSR, the input unit ET or the output unit AT cannot be activated. In this state, no data transfer from or to these facilities is possible.

To block the switching amplifiers SCR 1 to SCR 4 , a common blocking signal EXPR from a device UR 1 to be explained in more detail in the test circuit is used. The test circuit for the purpose described in its essential components microcomputer further includes an operational cycle counter MR, in which the dynamic increment input EiMR with the control signal output A ICPU of the microprocessor CPU is connected to the outputs prior to each operation cycle, the synchronization signal SYNC, the operational cycle counter MR has a control input E 2MR to which a related control signal is given to activate the counter. Without this control signal, the operation cycle counter MR is switched off, so that the supplied synchronization signals SYNC cannot advance the operation cycle counter from its basic position.

At the operation cycle counter MR, a first converter UR 1 in the form of a programmable read-only memory chip (ROM) is connected, which has the task of generating as a function of the counter position of the operation cycle counter MR special control signals via the outputs AGX, AG2 and AG3 to downstream Devices are issued. Of these special control signals, the blocking signal EXPR has already been mentioned, which among other things is used to block the switching amplifier SCR 1 to SCR 4. For this purpose, the blocking inputs of these switching amplifiers are connected to the output AG 1 of the converter URi . The control inputs ERLSR and EBR of a register reading program memory RLSR and a bidirectional bus driver BR are also connected to this output. With the operation cycle counter MR, a second converter UR 2 is still connected, which addresses the register read program memory RLSR depending on the count of the operation cycle counter MR The output of a register read program via the mentioned Sammelleltungstreiber BR on the data bus DS, when the special locking signal EXPR is present, in which case it is guaranteed that neither the system memory SSR nor the input or output unit £ 77.4 ^ can receive or deliver information.

An exemplary embodiment of a register reading program which is contained in the register reading program memory RLSR and which applies to microcomputers based on the SABtMO system is given below

RST <P

XTHL

DCXH

DCXH

XTHL

PUSHH

PUSHD

PUSHB

PUSHPSW

POPPSW

POPB

POPD

POPH

Disable interrupt
Save command counter

Correction of the command counter

Register contents in
Deposit storage

Outsource storage

Enable interrupt
Reload command counter

Another essential component of the test circuit is a memory for register contents SR, which works in conjunction with an address counter AR and is connected by the bus driver BR to the data bus DS for receiving information from internal registers of the microprocessor CPU The memory for register contents SR can be designed as read-write memory with random access (RAM).

To start the test circuit, a key contact TT is provided which, in conjunction with a resistor Ä and a non-element NG, controls an AND element UD 1 in such a way that only when the key contact TT is closed, i.e. actuated, the key contact TT is fed to a logic 1 via the non-element TVG. On the other hand, the AND element UD 1 is connected to that output A iZR of the state memory ZR , which outputs the temporarily stored state information Mi. In this case, the microprocessor CPU states that the current cycle is the read cycle of the first command byte to the AND element UD i is connected to its dynamic control input EMKD, a monostable flip- flop MKD , which controls a bistable flip- flop BKD via its set input S. The reset input R of the bistable flip-flop BKD is connected to the output AG 3 of the first converter UR 1. On the output side, the reset input of the address counter AR is also connected to the monostable multivibrator MKD. As a result, when the button contact 7Tim AR is pressed, a preset basic setting is forced. The incremental input FAR of the address counter AR is connected to the output of a further AND element UD 2 . One input of the AND element UD 2 is connected to the output AG 2 of the first conversion UR i and the second input is connected to the output A4 of the logic circuit VSG. This ensures that the control signal MEMW of the logic circuit VSG is given as an incremental signal to the address counter AR at a given time with the aid of the control signal emitted via the output .AG 2 of the first converter URi. Since the output of the AND element UD 2 is also connected to the memory for register contents SÄ, the output signal of the AND element UD 2 in the aforementioned memory SR serves as a write signal in which the information transmitted by the collective line driver MR is below that indicated by the address counter AR Address can be saved.

The output of the bistable flip-flop BKD is with

connected to the input E 2MR of the operation cycle counter MR and to an input EUR 1 of the first converter UR 1. This ensures that both the operation cycle counter MR and the first converter UR 1 are only activated when the bistable flip-flop ßATD is set.

The mode of operation of the test circuit described in its structure in connection with the microcomputer is the following:

When the button contact TT is actuated, the monostable flip-flop MKD is moved into the unstable position if the status information AfI "read operation code" is present. The completed actuation of the key contact 7T is thus stored for a predetermined period of time. When the monostable flip-flop MKD is switched, the bistable flip-flop BKD is set and thus the operation cycle counter MR is enabled for counting the individual synchronization signals SVWC. Furthermore, the first converter UR 1 evaluates the basic operating cycle counter position on the basis of its release. As a result of the function of the first converter UR 1, what is subsequently achieved is that the program of the microcomputer in the system memory SSR is switched ineffective at predetermined times. For this purpose, the first converter UR 1 outputs the blocking signal EXPR via the output AG 1, namely "read operation code" during each operation cycle. The switching amplifiers SCR 1 to SCR 4 are blocked with the aforementioned blocking signal EXPR , so that the microprocessor CPU is prevented from accessing the system memory SSR. In addition, the blocking signal EXPR switches the operation code of the commands of the register reading program contained in the register reading program memory RLSR via the bus driver BR , which is also activated by the blocking signal EXPR, to the data bus DS. With such a command supply, the register content of the microprocessor CPU 'is on the data bus DS during a specific operating cycle. In order to have this register content available for test purposes independently of the further work flow in the microcomputer, the first converter URi operated by the operation cycle counter MR switches the AND element UD 2 in conjunction with the control signal « MEMW effective for outputting the information required for the memory of the register contents SR Write signal. The address counter AR is then incremented. The new address set in this way selects a new memory line in the memory for register contents SR for the next register contents of the microprocessor CPU to be stored.

After all the register contents of the microprocessor CPU have been stored, for which the converter UR 2 supplies the necessary control information for the register reading program memory RLSR , the control signal for resetting the bistable flip-flop BKD is output from the first converter URX via the output Ad. In this switching position of the bistable flip-flop BKD , the operation cycle counter MR is again set in its inactive initial position MR and the converter UR 1 is switched off.

The first converter UR 11 then blocks the output of the blocking signal EXPR, so that the register reading program memory RLSR and the bus driver BR are switched off. In the absence of the EXPR locking signal, the SCR ! until SCR 4 is reactivated so that normal operation of the microcomputer can be resumed.

The information from the microprocessor collected in the memory for register contents SR is available for test purposes; the evaluation of this information is not the subject of the present invention and is therefore not dealt with further.

The use of the test circuit with the operation cycle counter MR, the two converters UR 1, UR 2 in connection with the register reading program memory RLSR and the memory for register contents SR advantageously allows the use of a register reading program for test purposes, which is independent of the format of the commands used.

In an advantageous embodiment of the inventive concept, the test circuit also enables the "write register function", by after saving the register contents in the stack (PUSH commands) this stack memory area can be specifically overwritten and thus when restoring to the Register to get there changed content.

1 sheet of drawings

Claims (4)

Patent claims: 1. Test circuit for a microcomputer, which essentially consists of a microprocessor, to whose data bus a system memory for programs and data as well as input and output units are connected, which are activated by addresses and separate control signals carried over an address bus, as well as with one of the State memory for status information located on the data bus, characterized in that an operation ^{cycle counter <5} (MR ) which can be incremented by synchronization signals (SYNCJ of the microprocessor (CPU) and two downstream converters (UR 1, UR 2) is provided, the first converter (UR 1) having several having outputs (AGi, AG2, AG '3) for the other control signals, of which one output (AG t \ of after the Testschal- tang starting operating action during each operation cycle "operation code iesen" a blocking signal (EXPR) outputs, in this test case a register reading program stored in the test circuit ter bypassing the system memory (SSR) in the data bus, and is connected to blocking inputs of switching amplifiers (SCRX to SCR 4), which in non-test mode are necessary for activating the system memory (SSR) and the input and output units (ET, AT) control signals (IOW,? OR, MEMR, MEMW) pass, that a register read program contained register read program memory (RLSR) is connected to the second converter (UR 2) to the effective switching of the output (AG 1) for the lock signal (EXPR) of first converter (UR 1) and the output side is indirectly connected to the data bus (DS) , to which a memory (SR) controllable by an assigned address counter (AR ) for receiving information from the internal registers of the microprocessor (CPU) is also connected indirectly 2. Test circuit according to claim 1, characterized in that to activate the operation cycle counter (MR) a control input (E 2MR) of this counter is connected to the output of a trigger element (BKD) , the set input (S) through an AND element (UD 1 ) is controllable, of which one input can be switched by a button contact (TT) and the second input is connected to that output (A IZR) of the state memory (ZR) that outputs the state information (M 1) that says that the current Cycle is the read cycle of a first instruction byte and that the reset input (R) of the flip-flop (BKD) is connected to an output (AG 3) of the first converter (UR 1) which characterizes the end of the register reading program 3. Test circuit according to claim 1, characterized in that an AND element (UD 2) is connected to the incremental input (FAR) of the address counter (AR) , of which an input with the output (AG2 ) serving to activate the address counter (AR) ) of the first converter (UR 1) and the other input is connected to that output (A 4) of a logic circuit (VSG) connected downstream of the status memory (ZR ), which sends the control signal "write memory" (MEMW) from & bL 4. Test circuit according to claim 1, characterized in that the register reading program memory (RLSR) and the memory (SR) for the information from the registers of the microprocessor (CPU) with the data bus (DS) via a bus driver (BR) are connected by the a control input (EBR) is connected to that output (AGi) of the first converter (URi) which carries the blocking signal (EXPR)