DE2651449A1 - PROCESS FOR MANUFACTURING COMPLEMENTARY TRANSISTORS IN INTEGRATED SEMICONDUCTOR TECHNOLOGY - Google Patents
PROCESS FOR MANUFACTURING COMPLEMENTARY TRANSISTORS IN INTEGRATED SEMICONDUCTOR TECHNOLOGYInfo
- Publication number
- DE2651449A1 DE2651449A1 DE19762651449 DE2651449A DE2651449A1 DE 2651449 A1 DE2651449 A1 DE 2651449A1 DE 19762651449 DE19762651449 DE 19762651449 DE 2651449 A DE2651449 A DE 2651449A DE 2651449 A1 DE2651449 A1 DE 2651449A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0821—Combination of lateral and vertical transistors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/2205—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8228—Complementary devices, e.g. complementary transistors
- H01L21/82285—Complementary vertical transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Description
Amtliches Aktenzeichen:Official file number:
NeuanmeldungNew registration
Aktenzeichen der Anmelderin: FI 975 028Applicant's file number: FI 975 028
Verfahren zur Herstellung komplementärer Transistoren in integrierter Halbleitertechnik Process for the production of complementary transistors in integrated semiconductor technology
Verfahren zum Herstellen vertikaler und komplementärer lateraler Transistoren in integrierter Halbleitertechnik sind bereits mehrfach vorgeschlagen worden. Der Einsatz der dabei entstehenden Strukturen ist mit einigen Vorteilen verbunden. Die vertikalen, bipolaren Transistoren und die dazu komplementären lateralen, bipolaren Transistoren werden dabei gleichzeitig hergestellt. Zur Erhöhung der Funktionstuchtigkeit der lateralen Transistoren wurden Vorkehrungen getroffen, durch die die Emitterinjektion längs des horizontalen Teiles des Emitterüberganges im Vergleich zur Emitterinjektion längs der vertikalen Teile des Emitterüberganges reduziert wird. Mit anderen Worten, die Injektion von Ladungsträgern durch den Emitter wird selektiv im Flächenbereich zwischen Emitter und Kollektor des lateralen Transistors erhöht.Methods for producing vertical and complementary lateral transistors in integrated semiconductor technology are already multiple has been proposed. The use of the resulting structures has a number of advantages. The vertical, Bipolar transistors and the complementary lateral, bipolar transistors are produced at the same time. To increase the functionality of the lateral transistors Precautions were taken to compare the emitter injection along the horizontal part of the emitter junction for emitter injection is reduced along the vertical parts of the emitter junction. In other words, the injection of Charge carriers through the emitter is selectively increased in the area between the emitter and collector of the lateral transistor.
Ein derartiges Verfahren ist in der Zeitschrift "IEEE Transactions : on Electron Devices", Juli 1967, auf den Seiten 381 bis 385, unter dem Titel "A High Performance Lateral Geometry Transistor For Complementary Integrated Circuits" von David F. Hilbiber beschrieben. Die vom horizontalen Teil des Emitterüberganges des lateralen '■■_ Transistors injizierte Ladungsträgerdichte wird in dem beschrie- j benen Verfahren dadurch reduziert, daß eine doppelte Ausdiffusion ■Such a method is described in the journal "IEEE Transactions: on Electron Devices", July 1967, on pages 381 to 385, under the title "A High Performance Lateral Geometry Transistor For Complementary Integrated Circuits" by David F. Hilbiber. The injected from the horizontal part of the emitter junction of the lateral '■■ _ transistor charge carrier density is reduced in the described method j surrounded by the fact that a double-diffusion ■
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^ ζ* ^m ^ ζ * ^ m
von Störstellen des N-Leitfähigkeitstyps aus einer zusammengesetzten, vergrabenen Zone innerhalb eines Substrats in eine darauf aufge- ι wachsene Epitaxieschicht erfolgt. Als Störstellen für die zusam- ! mengesetzte vergrabene Schicht werden dabei Phosphor und Antimon j verwendet. Der Phosphor diffundiert mit dem Antimon aus und bildet, dabei eine N -dotierte Stufe innerhalb einer N-Wanne. Die N+-dotie^- te Stufe liegt unterhalb des Emitters des lateralen Transistors. j Zusammengefaßt kann man also feststellen, der horizontale (unterst^) Teil des EmitterÜberganges des lateralen Transistors stößt an eine Basiszone (N -Stufe), die höher dotiert ist als die durch die N-Epitaxieschicht verkörperte Basiszone, die an die vertikalen (obersten) Teile des Emitterüberganges angrenzt. Die Injektionswirksamkeit des Emitters verhält sich umgekehrt zur Dotierungskonzentration der angrenzenden Basiszone, D,h, also, daß die Ladungsträgerinjektion selektiv entlang der Fläche des lateralen Transistors erhöht wird, was gleichbedeutend ist mit einer Erhöhung des Verstärkungsfaktors des lateralen Transistors,of impurities of the N conductivity type from a composite, buried zone within a substrate into an epitaxial layer grown thereon. As disruptions for the together! The second buried layer uses phosphorus and antimony. The phosphorus diffuses out with the antimony and forms an N -doped step within an N-tub. The N + -dotie ^ - th stage is below the emitter of the lateral transistor. In summary, one can determine that the horizontal (bottom ^) part of the emitter junction of the lateral transistor meets a base zone (N stage) that is more heavily doped than the base zone embodied by the N epitaxial layer, which is attached to the vertical (top) Parts of the emitter junction are adjacent. The injection efficiency of the emitter is inversely related to the doping concentration of the adjacent base zone, D, h, i.e. the charge carrier injection is selectively increased along the surface of the lateral transistor, which is equivalent to an increase in the gain factor of the lateral transistor,
Es ist die Erfindung zugrundeliegende Aufgabe, ein Verfahren anzugeben, durch das die verbesserten Eigenschaften des lateralen Transistors erreicht werden, ohne daß zusätzliche Verfahrensschritte nötig wären, die nicht schon bei der Herstellung komplementärer Transistoren erforderlich wären. Außerdem ist anzustreben, gleichzeitig den vertikalen Teil des Emitterüberganges des lateralen Transistors auszudehnen, wodurch eine weitere Erhöhung des Verstärkungsfaktors dieses Transistors erzielt werden kann.The object on which the invention is based is to specify a method by means of which the improved properties of the lateral transistor are achieved without the need for additional process steps that are not already complementary in the production Transistors would be required. In addition, the aim is to at the same time to expand the vertical part of the emitter junction of the lateral transistor, thereby further increasing the Gain factor of this transistor can be achieved.
Die Lösung dieser Aufgabe ist in den Ansprüchen niedergelegt. |The solution to this problem is laid down in the claims. |
Die Erfindung wird im folgenden anhand der Zeichnung näher er- . läutert.The invention is explained in more detail below with reference to the drawing. purifies.
Es zeigen:Show it:
Fign. 1A bis 1F vereinfachte Schnittansichten nach dem erfindungs-fFigs. 1A to 1F simplified sectional views according to the invention-f
gemäßen Verfahren hergestellter komplementärer J FI 975 028Complementary J FI 975 028 produced according to the method
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: wm ^a *™: wm ^ a * ™
Transistoren in aufeinanderfolgenden Herstellungsstufen, Transistors in successive manufacturing stages,
Fig. 2 Störstellenprofile, aufgenommen entlang desFig. 2 impurity profiles, recorded along the
vertikalen Schnittes 2-2 der Fig. 1D undvertical section 2-2 of FIGS. 1D and
Fig. 3 Störstellenprofile, aufgenommen entlang desFig. 3 impurity profiles, recorded along the
vertikalen Schnittes 3-3 der Fig. 1E.vertical section 3-3 of Fig. 1E.
Zunächst sei die Fig. 1A betrachtet. In ein P-Substrat 3 mitLet us first consider FIG. 1A. In a P substrate 3 with
15 3 + einer Störstellenkonzentration von 10 Atome/cm sind N -Zonen 1 und 2 einduffundiert. Als Störstellenmaterial dient dabei vorzugsweise Arsen, dessen Ausdiffusion während nachfolgender Verfahrensschritte begrenzt ist, Über den Zonen 1 und 2 sollen ein vertikaler N3?N-Tra.nsistQr und ein lateraler PNP-Transistor verwirklicht werden. Selbstverständlich können weitere N -Zonen (nicht dargestellt) gleichzeitig in das Substrat 3 eingebracht werden, über denen dann weitere NPN- und PNP-Transistoren herstellbar sind. Nach dem Einbringen der hochdotierten Zonen wird das Substrat 3 einem Oxidationsprozeß ausgesetzt f bei dem eine Siliciumdioxidschicht 4 entsteht. In dieser Siliciumdioxidschicht 4 werden Diffusionsfenster 5f 6 und 7 freigelegtf die die Stellen der einzubringenden Isolationszonen definieren. Ein weiteres Fenster 8 definiert den Ort des Emitters des lateralen PNP-Transistors. Wie in Fig. 1B dargestellt, werden im Bereich der Maskenfenster 5 bis 8 P -dotierte Zonen eingebracht. Die Oberflächenstörstellenkonzentrationen der N - bzw. P -Zonen betragen beispielsweise 4 χ 1015 3 + an impurity concentration of 10 atoms / cm, N zones 1 and 2 are infused. Arsenic is preferably used as the impurity material, the out-diffusion of which is limited during the subsequent process steps. A vertical N3-N-Tra.nsistQr and a lateral PNP transistor are to be implemented over zones 1 and 2. Of course, further N zones (not shown) can be introduced into the substrate 3 at the same time, via which further NPN and PNP transistors can then be produced. After the introduction of highly doped regions, the substrate is subjected to 3 f an oxidation process occurs in which a layer of silicon dioxide. 4 In this silicon dioxide layer 4 diffusion windows 5 f 6 and 7 are exposed f which define the locations of the insulation zones to be introduced. Another window 8 defines the location of the emitter of the lateral PNP transistor. As shown in FIG. 1B, 5 to 8 P -doped zones are introduced in the region of the mask windows. The surface impurity concentrations of the N or P zones are, for example, 4 × 10
3 19 3 + +3 19 3 + +
Atome/cm bzw. 7 χ 10 Atome/cm , Die Tiefen der N - bzw. P -Zonen betragen etwa 1,3 bzw. 1,15 um. Als Störstellenmaterial für die P -Zonen dient vorzugsweise Bor.Atoms / cm or 7 χ 10 atoms / cm, the depths of the N and P zones are about 1.3 and 1.15 µm, respectively. As an impurity material for the P zones are preferably used for boron.
Die Siliciumdioxidschicht 4 wird entfernt. Wie in Fig. 1C dargestellt, wird auf das Substrat 3 eine N~"-Epitaxieschicht 9 aufgebracht, die eine Störstellenkonzentration von 10 Atome/cm aufweist. Auf die Epitaxieschicht 9 wird durch Oxidation eine Siliciumdioxidschicht 10 aufgebracht. Die Siliciumdioxidschicht 10 wirdThe silicon dioxide layer 4 is removed. As shown in Fig. 1C, an N ~ "epitaxial layer 9 is applied to the substrate 3, which has an impurity concentration of 10 atoms / cm. A silicon dioxide layer is deposited on the epitaxial layer 9 by oxidation 10 applied. The silicon dioxide layer 10 becomes
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dann mit einer Siliciumnitridschicht 11 abgedeckt. In den Bereichen 12 bis 16 werden in den Schichten 10 und 11 Fenster freigelegt. In den Bereichen dieser Fenster werden dann durch Oxidation dielektrische Isolationszonen erzeugt, die bis zu den P -Zonen 5, 6 und 7 hinabreichen. Die Siliciumnitridschicht 11 wird dann entfernt, so daß sich die in Fig. 1B dargestellte Struktur ergibt. Dieelektrische Isolationszonen werden bevorzugt angewendet. Anstelle dieser dielektrischen·Isolationszonen können sich jedoch auch die P -Zonen 5, 6 und 7 bis an die Oberfläche der Epitaxieschicht 9 erstreckt werden, wobei dann die Siliciumnitridschicht 11 nicht benötigt wird.then covered with a silicon nitride layer 11. In the fields of 12 to 16 windows are exposed in layers 10 and 11. The areas of these windows are then due to oxidation creates dielectric isolation zones that extend up to the P zones 5, 6 and 7 reach down. The silicon nitride layer 11 is then removed so that the structure shown in FIG. 1B results. The electrical isolation zones are preferably used. Instead of Of these dielectric isolation zones, however, the P zones 5, 6 and 7 can also extend up to the surface of the epitaxial layer 9 can be extended, in which case the silicon nitride layer 11 is not required.
Die Störstellenprofile entlang der Schnittlinie 2-2 der Fig. 1D sind in Fig, 2 aufgezeichnet. Die Kurve 17 der Fig, 2 repräsentiert die Arsen-dotierte vergrabene Zone 2, Die Kurve 18 gibt die Bor-dotierte Zone 8 wieder und zwar nach deren Ausdiffusion in die Epitaxieschicht 9 während der Hochtemperaturprozesse, die im Zusammenhang mit der Herstellung der Strukturen nach Fig. 1C und 1D anzuwenden sind. Es ist festzustellen, daß die Bor-dotierte Zone 8 weiter in die Epitaxieschicht 9 ausdiffundiert als die Arsen-dotierte Zone 2, obwohl die Borkonzentration (Kurve 18) geringer ist als die Arsen-Konzentration (Kurve 17). Diese Tatsache ergibt sich aus dem höheren Diffusionskoeffizienten von Bor.The impurity profiles along section line 2-2 of Fig. 1D are recorded in FIG. The curve 17 in FIG. 2 represents the arsenic-doped buried zone 2, the curve 18 reproduces the boron-doped zone 8 after it has diffused out into the epitaxial layer 9 during the high-temperature processes, which are to be used in connection with the production of the structures according to FIGS. 1C and 1D. It should be noted that the boron-doped zone 8 diffuses further into the epitaxial layer 9 than the arsenic-doped zone 2, although the boron concentration (Curve 18) is lower than the arsenic concentration (curve 17). This fact results from the higher diffusion coefficient of boron.
Wie in Fig. 1E dargestellt, werden in der SiIiciumdioxidschicht 10 in den Bereichen 19 und 20 Fenster freigelegt, durch die eine N -Kollektorkontaktzone 19 des NPN-Transistors und eine Basiskontaktzone 20 des PNP-Transistors eingebracht werden. Nach erneuter Reoxidation v/erden Fenster in den Bereichen 21 bis 24 freigelegt, über die die P+-dotierten Zonen, nämlich die Basis 21 des NPN-Transistors und die Kollektoren 22 und 24 und der Emitter 23 des lateralen PNP-Transistors eingebracht werden. Es zeigt sich, daß der Emitter 23 in die ausdiffundierte Zone 8 übergeht. Auf diese Weise erhält man einen tiefenmäßig ausgedehnten Emitter,As shown in FIG. 1E, windows are exposed in the silicon dioxide layer 10 in the regions 19 and 20, through which an N collector contact zone 19 of the NPN transistor and a base contact zone 20 of the PNP transistor are introduced. After renewed reoxidation, windows in the areas 21 to 24 are exposed, through which the P + -doped zones, namely the base 21 of the NPN transistor and the collectors 22 and 24 and the emitter 23 of the lateral PNP transistor are introduced. It can be seen that the emitter 23 merges into the out-diffused zone 8. In this way you get a deeply extended emitter,
FI 975 028FI 975 028
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-Sf--Sf- «■ - - ■«■ - - ■
der von der Oberfläche der Epitaxieschicht 9 bis zu der vergrabenen N -Zone 2 reicht. Die Störstellenprofile entlang der ; Schnittlinie 3-3 der Fig. 1E sind durch die Kurven in Fig. 3 ; wiedergegeben. \ which extends from the surface of the epitaxial layer 9 to the buried N zone 2. The impurity profiles along the; Section line 3-3 of Fig. 1E are through the curves in Fig. 3; reproduced. \
In Fig. 3 entsprechen die Kurven 25, 27 und 26 den Störstellen- ; profilen des einduffundierten Emitterbereiches 23, des ausdiffundierten Emitterbereiches 8 und der vergrabenen Basiszone 2 des lateralen PNP-Transistors. Es zeigt sich, daß der unterste, : horizontale Teil des Emitterüberganges in der Grenzschicht zwi- ; sehen Emitter 8 und vergrabener Basiszone 2 verläuft, nämlich ;In Fig. 3, the curves 25, 27 and 26 correspond to the impurity; profiles of the diffused emitter region 23, the diffused out Emitter region 8 and the buried base zone 2 of the lateral PNP transistor. It turns out that the lowest: horizontal part of the emitter junction in the boundary layer between; see emitter 8 and buried base zone 2 runs, namely;
1 R dort, wo die Störstellenkonzentration der Zone 2 etwa bei 2 χ 10 i1 R where the impurity concentration of zone 2 is around 2 χ 10 i
3 '3 '
Atome/cm liegt. Dies ergibt sich aus dem Schnittpunkt der Kurven 27 und 26 in Fig, 3, Im vertikal verlaufenden Teil des Emitterüberganges beträgt die Störstellenkonzentration der Basis f die dort durch die Epitaxieschicht gebildet wird, nur etwa 2 χ 10 Atome/cm { ist also um 2 Größenordnungen geringer. Dies ergibt sich aus dem horizontalen Teil der Kurve 26,Atoms / cm. This results from the intersection of curves 27 and 26 in Fig. 3. In the vertically running part of the emitter junction, the impurity concentration of the base f, which is formed there by the epitaxial layer, is only about 2 × 10 atoms / cm { is therefore around 2 orders of magnitude less. This results from the horizontal part of curve 26,
Die Kurven 25 und 26 repräsentieren auch die Störstellenprofile der Basis 21 und der den Kollektor bildenden Zonen 1 und 9 des vertikalen NPN-Transistors. Die Kurve 27 zeigt die Störstellenkonzentration der P+-Isolationszonen 5, 6 und 7. Der verbesserte laterale PNP-Transistor läßt sich also verwirklichen, ohne daß ein zusätzlicher Prozeßschritt zu den ohnehin zur Herstellung des vertikalen NPN-Transistor erforderlichen Prozeßschritten in das Verfahren eingefügt werden muß. Es ist lediglich ein besonderes Maskenfenster zum Eindringen der P -Zone 8 vorzusehen. Das Eindringen selbst erfolgt gleichzeitig mit dem Herstellen der Isolationszonen 5, 6 und 7, wie es in Verbindung mit Fig. 1B beschrieben ist.The curves 25 and 26 also represent the impurity profiles of the base 21 and the collector-forming zones 1 and 9 of the vertical NPN transistor. The curve 27 shows the concentration of impurities in the P + insulation zones 5, 6 and 7. The improved lateral PNP transistor can thus be implemented without adding an additional process step to the process steps required anyway for manufacturing the vertical NPN transistor got to. All that is required is a special mask window for the P zone 8 to penetrate. The penetration itself takes place simultaneously with the production of the isolation zones 5, 6 and 7, as is described in connection with FIG. 1B.
Die beiden komplementären Transistoren werden in üblicher Weise vervollständigt. Ein Emitter 28 wird in die Basis 21 des NPN-Transistors einduffundiert. Dabei wird vorzugsweise die gleiche N -Duffusion angewendet, die zur Erhöhung der Störstellenkonzen-The two complementary transistors are used in the usual way completed. An emitter 28 is diffused into the base 21 of the NPN transistor. It is preferably the same N -duffusion used to increase the impurity concentration
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trationszone der Kollektorkontaktzone 19 des NPN-Transistors im Bereich des Kontaktfensters 29 und der Basiskontaktzone 35 des PNP-Transistors im Bereich des Kontaktfensters 35 angewendet wird. Schließlich werden über den P-dotierten Zonen 31, 32, 33 und 34 Kontaktfenster geöffnet, so daß sich die in Fig. 1F dargestellte Struktur ergibt.trationszone of the collector contact zone 19 of the NPN transistor in the Area of the contact window 29 and the base contact zone 35 of the PNP transistor in the area of the contact window 35 is applied. Finally, over the P-doped zones 31, 32, 33 and 34 Contact window opened, so that the structure shown in Fig. 1F results.
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Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US63496475A | 1975-11-24 | 1975-11-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE2651449A1 true DE2651449A1 (en) | 1977-05-26 |
Family
ID=24545858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19762651449 Pending DE2651449A1 (en) | 1975-11-24 | 1976-11-11 | PROCESS FOR MANUFACTURING COMPLEMENTARY TRANSISTORS IN INTEGRATED SEMICONDUCTOR TECHNOLOGY |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5264882A (en) |
| CA (1) | CA1053376A (en) |
| DE (1) | DE2651449A1 (en) |
| FR (1) | FR2347777A1 (en) |
| IT (1) | IT1070023B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0005728A1 (en) * | 1978-05-25 | 1979-12-12 | International Business Machines Corporation | Method for making a lateral PNP or NPN transistor with a high gain and transistor so produced |
| FR2457564A1 (en) * | 1979-05-23 | 1980-12-19 | Thomson Csf | Bipolar integrated circuit pnp transistor - has p-type substrate with p-implantation zones and n-type epitaxial layer |
| EP0540443A2 (en) * | 1991-10-31 | 1993-05-05 | International Business Machines Corporation | Complementary subcollectors with silicon epitaxial layers |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4339767A (en) * | 1980-05-05 | 1982-07-13 | International Business Machines Corporation | High performance PNP and NPN transistor structure |
-
1976
- 1976-09-17 IT IT2730876A patent/IT1070023B/en active
- 1976-09-22 FR FR7629494A patent/FR2347777A1/en not_active Withdrawn
- 1976-10-27 JP JP51128423A patent/JPS5264882A/en active Pending
- 1976-11-11 DE DE19762651449 patent/DE2651449A1/en active Pending
- 1976-11-24 CA CA266,527A patent/CA1053376A/en not_active Expired
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0005728A1 (en) * | 1978-05-25 | 1979-12-12 | International Business Machines Corporation | Method for making a lateral PNP or NPN transistor with a high gain and transistor so produced |
| FR2457564A1 (en) * | 1979-05-23 | 1980-12-19 | Thomson Csf | Bipolar integrated circuit pnp transistor - has p-type substrate with p-implantation zones and n-type epitaxial layer |
| EP0540443A2 (en) * | 1991-10-31 | 1993-05-05 | International Business Machines Corporation | Complementary subcollectors with silicon epitaxial layers |
| EP0540443A3 (en) * | 1991-10-31 | 1996-09-25 | Ibm | Complementary subcollectors with silicon epitaxial layers |
Also Published As
| Publication number | Publication date |
|---|---|
| CA1053376A (en) | 1979-04-24 |
| JPS5264882A (en) | 1977-05-28 |
| IT1070023B (en) | 1985-03-25 |
| FR2347777A1 (en) | 1977-11-04 |
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