DE2632447A1 - CMOS SEMICONDUCTOR DEVICE - Google Patents

Description

PATENT LAWYERS

HENKEL, KERN, FEILER & HÄNZEL

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TELEGRAMS: ELLIPSOID MUNICH

2632U7

Tokyo Shibaura Electric Co./ Ltd.,
Kawasaki-shi, Japan

1 July 9, 1976

CMOS semiconductor device

The invention relates to a device hereinafter referred to as a CMOS device designated complementary MOSFET semiconductor device in which the actuation or activation of parasitic bipolar Transistors is suppressed.

There are already numerous, formed by CMOS elements Circuits known for which a CMOS converter circuit is a typical example, which is known by a ρ-channel MOS transistor and an n-channel MOS transistor are formed will. The threshold voltage of one of these MOS transistors is opposite to that of the other MOS transistor Characteristic or curve. For this reason, only one of the two MOS transistors is generally dependent switched through by an input information. Consequently

—2 -

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flows, with the exception of the transition period of the input information pulse, no power from the power supply of the CMOS converter circuit so that almost no working current is consumed is, except that during the transition period of the pulse, both MOS transistors are briefly turned on at the same time are, so that only a brief transient current flows, a stray current occurs at the pn junction and a current flow due to charging or discharging of a storage capacitor at the output terminal of the CMOS converter circuit is.

If, on the other hand, an interfering signal is aperiodic or pulsed Is applied to the output or input of such a CMOS circuit, an abnormally large direct current of a multiple flows from 10 mA to a few hundred mA between positive and negative power supply or terminal of the CMOS circuit. Even after the interfering signal has ended, regular flow of such an abnormal current can be observed. This regular flow of the abnormally large current leads intermittently causes the CMOS circuit connection to melt through and is therefore interrupted. The pulse corresponding to this interference signal has both polarities, namely both positive as well as negative, and it causes an abnormally large current to develop. To prevent this abnormal current one must either the power supply voltage is reduced below a predetermined value or the CMOS circuit from the power source be separated.

The object of the invention is thus to create a CMOS semiconductor device, in which the creation and thus the flow of an abnormally large current as a result of interference pulses is prevented.

In the case of this CMOS semiconductor device, the circuit connection should also be used when an interference pulse is applied before a through-

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melt and thus be protected from an interruption.

In addition, this CMOS semiconductor device should be capable of even when an interference signal pulse with a low Power consumption to continue working.

This object is characterized by what is stated in the claims Measures resolved.

The invention provides a complementary MOSPET or CMOS semiconductor device created, which a semiconductor substrate of a conductive type, a drain or formed in the substrate. Protective layer of the opposite conductivity type, a first MOS transistor of one channel type formed in the substrate and a second MOS transistor of the opposite channel type provided in the protective layer, the source electrode of the first MOS transistor at the same potential as the substrate and / or the source electrode of the second MOS transistor is at the same potential as the protective layer, so that actuation of a parasitic bipolar Transistor whose base is formed by the substrate and / or a parasitic bipolar transistor whose base formed by the protective layer is suppressed. The actuation of the relevant bipolar transistor can thereby be suppressed that the distance from the edge of at least one contact hole on the surface of a substrate or in the Protective layer formed contact area to a boundary edge between substrate and protective layer is controlled accordingly. The invention is to CMOS semiconductor devices applicable where the (current amplification factor) product of the parasitic bipolar transistors is greater than 1.

The following are preferred embodiments of the invention explained in more detail with reference to the accompanying drawing. Show it:

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Fig. 1: a circuit diagram of one formed from CMOS elements Converter,

FIG. 2: a sectional side view of an embodiment of FIG Semiconductor device for explaining the invention,

Fig. 5: an equivalent circuit diagram of a thyristor circuit in the form of a CMOS semiconductor circuit device,

4: a graphic representation of the dependency of the current amplification factor of a transverse transistor with its base-forming η-substrate from its base width,

Fig. 5! a graphical representation of the dependence of the current gain factor of a vertical transistor, the base of which is formed by a p-type protective layer, of its base width,

6: a graphic representation of the dependency of the area in which a "latch up" takes place, from the base width of both a parasitic transverse transistor and a parasitic vertical transistor as well as the location of a contact hole,

FIG. 1 a plan view to illustrate an arrangement diagram of a semiconductor device according to the invention for showing the position of a contact hole, FIG.

Fig. 8 is a graph showing the relationship between the location of a contact hole and the minimum source voltage and an input signal voltage for generating an abnormal current,

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Pig. 9ί is a graph showing the relationship between the base width of a cross transistor whose
Base is formed by an η substrate, and a / minimum source voltage and an input signal voltage for generating abnormal current and

Fig. 10 and 11: Top views to illustrate various Arrangement diagrams of the semiconductor device according to the invention.

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The CMOS converter circuit illustrated in FIG. 1 consists of a p-channel MOS transistor Q ₁ and an n-channel MOS transistor Q _2. The source of the MOS transistor Q- is connected to a positive -Current terminal V _{nn is} connected, while its drain electrode is connected to the _{output terminal in common with the drain electrode of the MOS transistor Q 0} . The source electrode of the MOS transistor Q ₂ is connected to the negative or minus current terminal ν _σα . The gate electrodes of the MOS transistors Q ₁ and Q- are coupled together so that they form the input terminal of the CMOS converter circuit.

Fig. 2 illustrates an embodiment of the invention Semiconductor device in which the CMOS converter circuit according to FIG. 1 is in a semiconductor wafer is trained. The embodiment of FIG. 1 is used an n-type silicon substrate 1 with an n-type impurity such as phosphorus, which is in a concentration of about 1 χ 10 atoms / cm is doped. From the surface of the n-type silicon substrate 1, a p-type impurity, e.g. Boron, diffused into a part of the substrate 1 in a concentration of about 2 10 atoms / cm, whereby a p-type protection layer (well layer) 2 is formed.

19 Furthermore, boron has diffused in a concentration of about 10 atoms / cm into the n-substrate 1, the p-protective layer 2 and the transition or barrier layer edges between substrate 1 and protective layer 2, whereby a P -source- Electrode area 3 and a P drain electrode area 4 are formed, which have a p-MOS transistor Q ₁ , a coupling area ^V §7P conductive type in the p-protective layer and P protective rings 5 in the transition edges between n- · substrate 1 and form p-type protection layer 2. Likewise is

20th

Phosphorus diffuses into the p-protective layer 2 and the η-substrate I in a concentration of about 10 atoms / cm,

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so that an N source electrode region 7 and an N drain electrode region 8 are formed at the same time, which represent an η-channel MOS transistor Q ₂ in the protective layer 2 and a coupling region 9 of the N conductive type in the n substrate 1 . With this construction, a field silicon oxide layer is formed on the entire surface of the substrate 1.

In order to form the gate electrode regions of the MOS transistors Q 1 and Q ₂ , the substrate 1 is then subjected to photoetching, through which holes are formed in the field oxide film 10. On the bottoms of these holes, gate oxide films 11 and 12 having a thickness of 1,500 pounds are formed by oxidizing the holes at a high temperature. To produce the circuit connection according to FIG. 1, contact bores of a predetermined size are then made in the silicon oxide film 10, and a conductive layer / for example aluminum is vapor-deposited onto the entire surface of the substrate 1. The conductive layer is then cut in a predetermined pattern so that the P -type drain electrode region 4 and the N -drain electrode region 8 are connected to one another and the gate regions (or oxide films) 11 and 12 are connected to one another. The drain electrode regions 4 and 8 form an output terminal, while the gate electrode regions 11 and 12 form an input terminal. At the same time, the conductive P coupling area 6 and the conductive N coupling area 9 are connected to the negative power supply V _ss (ground) and to the positive power supply V, respectively. Further, if necessary, a silicon oxide film other than desired portions may be formed on the entire surface of the aluminum conductive film by chemical epitaxial growth in order to protect the latter and improve the reliability of the semiconductor device. Although not shown in Fig. 2, a blocking element (stopper) can be provided between the MOS transistors Q- and Q _2.

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When a pulse-shaped noise signal is applied to the output or input of the semiconductor device constructed as described above and functioning as a CMOS converter circuit, an abnormal current of 10 to 100 mA flows. According to the present invention, this phenomenon has been closely observed and examined. These investigations led to the result that when an interference current pulse is applied to the semiconductor device, a special thyristor circuit is formed therein, as shown in FIG. 2 by the dashed lines. More specifically, four kinds of parasitic bipolar transistors are thereby formed in the semiconductor substrate 1. _{In this case, a p n} p transverse transistor Tr .. is formed especially in the direction parallel to the surface of the substrate, the emitter, base and collector of which is the source region 3 of the p-MOS transistor Q, the n-semiconductor substrate 1 or the p- Represent protective layer 2. An npn vertical transistor Tr «is formed perpendicular to the surface of the substrate 1, the emitter, base and collector of which through the N-SOURCE region 7 of the η-MOS transistor Q ₂ , the p-protective layer 2 or the n-semiconductor substrate 1 can be formed. A pnp transverse transistor Tr. ,, whose emitter, base and collector is formed from the P -Dfain region 4 of the p-channel MOS transistor Q ₁ , the n-semiconductor substrate 1 and the p-protective layer, respectively, is also created parallel to the surface of the substrate 1 2 exist. Finally, an npn vertical transistor Tr. Is formed perpendicular to the surface of the substrate 1, the emitter, base and collector of which through the N drain region 8 of the η MOS transistor Q, the p protective layer 2 or the η semiconductor Substrate 1 are formed.

In the semiconductor device according to FIG. 2, the collectors of the transverse transistors Tr ₁ and Tr ₃ and the bases of the vertical _{transistors Tr 2} and Tr are jointly formed by the p-type protective layer 2. These electrodes are therefore each connected to one another and to the negative power supply V _ao (ground) via a resistor

over ₊ ■

IL ₃ ,, and the conductive P coupling area 6, the

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both are formed in the p-type protective layer 2. On the other hand, the bases of the transverse transistors Tr ₁ and Tr, and the collectors of the vertical transistors Tr and

^ formed jointly by the semiconductor substrate 1. These electrodes are therefore interconnected and connected to the positive power supply V, specifically via a resistor R _n and the conductive N coupling region 9, both of which are fixed in the semiconductor substrate 1. Furthermore, the emitters of the transistors Tr 1 and Tr _{1 are} connected to the output terminal OUTPUT and the emitters of the transistors Tr _{1 and Tr 0 are} connected to the positive power supply V _DD and the negative power supply V _qc , respectively.

Due to the described connection of the transverse and vertical transistors leaves it in the CMOS circuit device According to FIG. 2, as indicated by the dashed lines in FIG., the thyristor circuit formed by the equivalent circuit diagram according to FIG. 3. Referring to Fig. 3, the following shows the operation of the in the CMOS circuit 2 formed thyristor explained. In the following, "oc" means a current amplification factor, that is, one for bipolar transistors in general Specification of the ratio of collector current to emitter current expression used, "ß" a current amplification factor, i.e. the ratio of the collector current to the base current (ß-T ^ 5-) f and "I" the current or the amperage. As Addenda used letters "e", "b" and "c" refer to on emitter, base or collector. Also serve attached Numbers to designate the transistors concerned. Furthermore, the letter "r" denotes the internal or intrinsic resistance each transistor designated.

If, according to FIG. 3, as indicated by the solid arrow, a positive interference current pulse I ^ is applied to the output terminal, a current corresponding to © * flows in the collector of transistor Tr _3. χ I.. This current cc ₃ x I _in then flows

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on the acting as a bypass resistor R_ ^P ~ protective layer, n is 2. When the voltage across this resistor, the threshold voltage V exceeds ₂ between the base and emitter of the transistor Tr _2, the transistor Tr through, so that the base current I ₂ through its base flows. The resistance R _pwell in the p-type protective layer is significantly greater than the inherent resistance rbe2 between the base and emitter of the transistor Tr-. For this reason, the collector current cc ₃ x I- of the transistor Tr ₃ hardly flows through the resistor R ,,. Consequently, the base current I. _{2 of} the transistor Tr _{2 is} almost equal to the collector current OL ₃ x ¹ ^ _{n of} the transistor Tr ₃ , namely

^(R Pwell ^ ^rbe2)

If the collector current I _{n of} the transistor Tr ₀ as a driver.

CD. Z

current acts and the voltage at both terminals of the resistor R ^ _u - of the substrate rises to the threshold voltage V _be1 between the base and emitter of the transistor Tr ^, the transistor Tr. is switched on in a similar manner, as a result of which a base current I, .. flows over the base of the transistor Tr ^. The base current I, .. is almost equal to the collector current I _{c2 of} the transistor Tr, since the resistance of R ₁ ^ ₃₁₁ J _{3 is} considerably greater than the inherent resistance rbe1 between the base and emitter of the transistor Tr .., ie

¹ ^ - ¹ C ₂ ^(R Nsub » ^rbe1 > ⁽³⁾

¹ Cl ⁼ Pi ^X b1 ⁼ ^ ³ I ¹ C ₂ = Pi ^ß ₂ ^ ₃ I _1n .... '. (4)

When the MOS transistors Tr. And TR turn on, the current flows between the positive power supply V ₅₃₀ and ground via these transistors Tr and Tr ₃ . In other words, when a glitch is applied to the CMOS converter circuit, an abnormal current flows between the positive power source V and ground via the semiconductor substrate 1 and the p-type protective layer 2.

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To maintain a current flow between the positive power supply V _ß and ground even after the application of the interference signal has ended, it is necessary that the _{loop circuit or circuit loop formed by the transistors Tr and Tr 2} perform a (positive) feedback. This is only achieved if the base current I, 2 of the transistor Tr ₂ , which is first turned on when the interference pulse is applied, is made equal to or smaller than the collector current I- of the transistor Tr-, which turns on after the transistor Tr ₂ . This means:

I _b2 <I _c1 ....... (5)

From this follows b2 ° * ~ 3 in = '1' 2 ° ^ 3 in

Therefore:

1 <"P ₁ P ₂ (6)

It can be seen from formula (6) that when the product of the current amplification factors βJ and β_ of the transistors Tr ^ and Tr _{2 is} equal to or greater than 1, an abnormal current continues to flow between the positive power supply V _D and the ground of the CMOS converter circuit .

As long as the product of β- and β is greater than 1, in the loop circuit _{including the transistors Tr- and Tr 2,} the base current I, ~ i- ^{n of} a specific cyclic period is greater than the base current I, ₂ in the previous cycle. The more often the current flows cyclically or periodically in the loop circuit, the greater the current between the power supply V and ground. However, the current does not increase indefinitely. The current amplification factor β of a transistor is namely a function of the current and its value increases with the current. However, it becomes smaller again as soon as it has reached a maximum value β max. Because of this, will

the abnormal flow of current between positive power supplies

609883/0993.

V _DD and ground of the CMOS converter circuit finally held at a certain point or value / ie at an equilibrium or adjustment point between the increase in current caused by the loop circuit and the decrease in the current intensity caused by the reduction in the current amplification factor. Usually, the abnormal current reaches a certain value, which is determined when the two conditions below are satisfied:

a. I _b2 (n-1) = Ij ₃₂ (Xi)

b. P ₁ Cn) -P ₂ Cn)> 1,

where "n" indicates the number of periods during which the "abnormal current flows in the loop circuit.

The size of a transistor is not a primary factor in the possibility of abnormal current flow. If however, the current amplification factor β of the transistor based on the size of the transistor (strictly speaking of the drain area) is measured as a parameter, it can be found that there is a correlation between the size of the transistor and the current value at which the abnormal current is finally maintained. Through this it is shown that the larger the drain region of the transistor, the larger the abnormal current.

For the application of a negative interference pulse to the output of the CMOS converter circuit according to FIG. 3, as indicated by the dashed arrow line between the positive power supply V _DD and the output terminal OUTPUT, the same applies as for the application of a positive interference pulse to the output terminal - the following formulas:

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^J b1
¹ CI

- ¹ Ci ^(R Pwell » ^{rbe2) and}

For maintaining a / normal current in the CMOS converter circuit in the case of applying a negative Interfering signal must - as with the positive interfering signal - meet the following condition:

1 <B ₁ P ₂ ....... (6)

Thus, it can be said that it is sufficient to prevent the formation of an abnormal current and the constant flow of this' abnormal current in a Thyristorschaltüng of the type shown in FIG. 2 and 3, β is the product of the current amplification factors ,, and ß ₂ of transistors Tr and ¹ to keep Er ₂ at a value below 1. In general, it can be said that in order to prevent the generation of an abnormal current and a constant current flow in a CMOS converter due to the operation of a thyristor circuit, it is sufficient to use the product of the current amplification factors β of a transverse transistor which is practically parallel to the surface

60 9883/0 99 3

c2 / ^J 2-b2 f ^ H'bi Y ^ l * - 4 · ¹ · in j

To maintain the flow of current in the through the.

Transistors Tr- and Tr ₂ formed circuit it is ■ <- required that the collector current I _{2 of} the transistor

Tr ₂ , which is switched _{through after the transistor Tr 1} , |

is greater than the base current I, - of the transistor Tr ₁ - \

This means:! J "

of the semiconductor substrate, and one perpendicular to keep the vertical transistor lying on the surface of the semiconductor substrate at a value of less than 1. ·

According to the invention it has been found that for the practical fulfillment of this requirement, the following Measures can be applied:

1. Enlargement of the base width of the transverse or vertical transistor or both transistors.

2. Carrying out a heat treatment of the semiconductor substrate during the manufacturing process, thereby increasing the service life to shorten the charge carriers in the substrate.

3. Shortening the service life of the charge carriers in the semiconductor wafer, from which the substrate is made.

4. Doping the semiconductor substrate with gold.

Four embodiments of the invention are detailed below where the above measures from '1 to 4 have been applied.

Embodiment 1

In the graph of FIG. 4, the current amplification factor β ... of the transverse transistor Tr _{1 is} plotted on the ordinate. The base width Wj (u) of the transverse transistor Tr ₁ , ie the distance between the edge of the p-protective layer 2 and the edge of the source region 4 of the p-MOS transistor Q ₁ , which is in a other portion of the semiconductor substrate 1 than the protective layer 2 is formed. The graphic representation

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position shows that the current amplification factor ß., with increasing base width W * becomes smaller. The length of each vertical line in FIG. 4 indicates the area in which the current amplification _{factor P 1} varies depending on the respective semiconductor wafers and the relevant positions on the same wafer on which this factor is measured, given the same base width Wo.

of, In the graphic representation / Fig. 5, the current gain factor p _{2 of} the vertical transistor Tr is plotted logarithmically on the ordinate, while the base width W (u) of the vertical _{transistor Tr 2 is} plotted on the abscissa, namely the thickness of the p protective layer 2 minus the thickness of the source Beireichs 7 of the formed in the protective layer 2 η MOS transistor Q ₂ - This plot shows that the Stromverstärkungsfaktor.p ₂ with increasing base width W abnimmt.?Fig. 5 gives the length of the individual vertical lines the area in which the current amplification factor ß "varies depending on the individual disks or plates and the factor measurement position on one and the same plate, even if the base width W remains the same. In addition, the lengths of the vertical lines show the variation of the current amplification factor ß ₂ if the doping amount of foreign atom is regulated in such a way that the foreign atom concentration at different settling times, i.e. times during which the disk or the plate is subjected to a heat treatment, of 20 Hours, 40 hours and 60 hours is the same in each case, while a change in the base width W of the vertical transistor Tr _{2 is} caused. Since the base width W of the vertical transistor Tr ₂ largely depends on the thickness of the protective layer 2, it is influenced by changing the setting time.

The relationship between the base width and the current gain 'factor of the transverse or vertical transistor is different, because the current gain _{factor P 1} and β ₉ depending on the Hem for the

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Manufacturing methods used to manufacture the semiconductor device varies. As a result, straight lines A and B indicating the results of various tests A and B on different semiconductor devices are inclined at different angles as shown in FIGS. 4 and 5. As shown in Fig. 5, no current gain of the vertical transistor Tr ₂ other than that indicated by the line B could be measured.

In the graph of FIG. 6, the base width W of the vertical _{transistor Tr 2 is} plotted on the abscissa and the base width Wq of the transverse transistor Tr 2 is plotted on the ordinate. In this embodiment, the p-type protective layer was formed by diffusing, for example, boron into the semiconductor substrate. Its thickness was 12.5 μm for 60 hours of heat treatment or setting of the plate at 1200 ° C., 10.2 μm for 40 hours of heat treatment at the same temperature and 7.2 μm for 20 hours of heat treatment at the same temperature. The product of the current amplification factors β ... and β- was 8.1 in a CMOS converter circuit in which the base widths W ^ and W of transverse and vertical transistors Tr ₁ and Tr "are indicated by point a) in FIG. 6 indicated values. This product was 4.8 and 1.0 for a CMOS converter circuit, respectively. in which the basic widths W, and W had the values given by points b) and c) or by points d), e) and f). In every CMOS converter _{circuit in which the basic widths Wq and W v have} values above a straight line connecting points d), e) and ff ⁿ , the product of ß .. and ß _{2 is} less than 1. In such a circuit therefore, no abnormally large current flow could be detected. On the other hand, such an abnormal current flow was found in CMOS converter circuits in which the base widths Wj and W of transverse and vertical transistors Tr. This means that the so-called "latching" phenomenon was observed in these CMOS converter circuits.

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Based on the considerations explained above, it was found according to the invention that the occurrence and persistence of the abnormal current flow can also be suppressed when the product of the current gain factors B ₁ , ß _{p is} greater than 1, namely when the base widths ¥ », W of the parasitic bipolar Transistors are so narrow that they lie in the area below the solid line in FIG. 6 denoted _{by β, β 2 = 1.} In other words, according to the present invention, it has been found that the occurrence or non-occurrence of the abnormal current depends on the area and position of a contact hole formed in the surface of a contact area for connecting the semiconductor substrate and the protective layer to a power supply.

In the CMOS converter circuit shown in FIG. 2, there is a power supply. V _{DD is} connected to an n-semiconductor substrate 1 ^{via an N +} contact region 9 at the same potential. A power supply or terminal V_ _s (ground) is connected via a P ⁺ contact area 6 to a P protective layer area 2 at the same potential. The two contact areas 9 and 6 are for the production of an ohmic contact between the power supply V ^ ₇ ,, Y _ao and the substrate or the protective

DL) oc>

layer required.

If the CMOS circuit is supplied with a trigger signal by an external interference signal, a current by no means flows via the power supplies V ~ _D , V ^ g through the n-substrate 1 and the p-protective layer 2 before a part of the thyristor circuit according to FIG. 3 forming parasitic bipolar transistor in the substrate 1 or in the protective layer 2 is actuated. Only when a potential difference due to the product of the current and the resistance of the semiconductor substrate 1 or the protective layer 2, ie a level of the voltage applied across the base and emitter of a bipolar transistor, a

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reaches a sufficiently high value for the actuation of the bipolar transistor, namely a threshold voltage level between the base and emitter of the bipolar transistor, the parasitic bipolar transistor, the base of which is formed by the n-semiconductor substrate 1 or the p-protective layer 2, is activated, see above that it forms a thyristor circuit connection as shown in FIG. Even if an interference signal is applied to the CMOS circuit and if the voltage generated by the product of the multiplication of the current _{flowing through the power supplies V 7} ^ _7. , Ν " _{σσ by the resistance FL.. Of} the n-type semiconductor substrate 1 or the resistor ■ ^ Pwell ^ ^er P-protective layer 2 is defined, does not reach the level of the threshold voltage across the base and emitter of the bipolar transistor, the bipolar transistor is not activated and thus the thyristor circuit is not operated, which leads to it being quite it is unlikely that an abnormal current flow will last longer, even if a certain amount of current can briefly flow through the CMOS circuit. it is necessary to reduce the resistance R s _Nsub ^de η substrate or the resistor R ",, of the p-protective layer to the Potentialu The difference between the two terminals of these resistors is to reduce itself to a value lower than that of the threshold voltage across the base and emitter of the biplar transistor, whereby the continued flow of the abnormal current is suppressed or stopped.

The resistors FL. . and R ^ ,, each have a maximum value over a distance extending from the contact holes in the surface of the N ⁺ contact region 9 and the P ⁺ contact region 6 to the boundary edge between the p-type protective layer 2 and the n-type substrate 1 extends. For extensive reduction

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these resistors R _Nsub> ^R pwell ^em P ^fie keeps ^it is, therefore, the distance from the edge of the contact hole of the N ⁺ contact region 9'zur p-protective layer 2 and the distance from the edge or the edge of the contact hole of the P ⁺ contact region 6 to the n-semiconductor substrate 1 or one of these two routes. To suppress the sustained abnormal current flow, it is advantageous to reduce the distance between the edge of the contact hole of the N ⁺ contact area 9 and / or the P ⁺ contact area 6 and the boundary edge between the p-protective layer 2 and the n-semiconductor substrate 1 in order to- 'the voltage appearing across the resistors Rvr _sub or Rp ^ ₆ η-i,

namely the voltage across the base / and emitter of the parasitic bipolar transistor, the base of which is formed by the protective layer or the semiconductor substrate 1, to a value below that of the threshold voltage across the base and emitter to decrease.

7 shows the arrangement diagram of a CMOS circuit. the sections of this circuit corresponding to the respective sections or regions of the semiconductor substrate according to FIG. 2 are denoted by the same symbols as in Fig. 2, so that their explanation can be dispensed with.

Positions and areas of the contact holes A, B, C, D, E are shown in FIG. 7 and listed in Table 1 below.

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TABLE 1

Location of the contact hole

Extension of the contact hole

Distance of the contact hole from the semiconductor substrate or from the protective layer

area

Contact resistance

Middle of a transverse edge

the furthest

/ U ^c

Completely across the transverse edge up to two at right angles to it
Side edges wide

2.7OO / rev

<5

Full along one transverse edge and across half the length of each of the two perpendicular side edges a little closer

6,787

<5

OO OO OO U) O CO

Full along the
one transverse edge and over 35/4 of the total length of the two perpendicular side edges

closer

<5

Completely along one transverse edge and practically over the entire length closest to the two perpendicular side edges

1O.OOOyU ^C

<5

As is apparent from Fig. ¹ J and the table above, the formed on one of MOS transistors Q _1, Q ₂ Contact holes A closer to E in this order continuously to the η-HaIbleitersubstrat or p-protective layer 2 on which or forms the other of the two MOS transistors Q ₁ and Q ₂ , whereby the specific resistance of each resistor ^R Nsub ' ^R Pwell ^ents P ^{recnend is} reduced. In addition, since the contact holes A to E have continuously enlarged areas in the specified order, the contact resistances of these contact holes A to E also become progressively smaller. As a result, it can be expected that the abnormal flow of current in the order of the contact holes A to E is more and more difficult to occur. The results of tests carried out in this regard are shown in FIG. In FIG. 8, the positions of the contact holes are plotted on the abscissa, while the input signal voltage and the minimum levels V _cc -, J _{n of} the power supply voltage at which an abnormal current is generated are plotted on the ordinate. When an abnormal input signal with a maximum current of 500 mA was applied to the CMOS circuit due to an external noise, it was found that the occurrence of this abnormal current in the order of the contact holes A to E gradually decreased. Furthermore, it was found that a minimum level V _{DD Μ} γ _{Ν of} the power supply voltage, at which an abnormal current occurs, depends on the type of formation of the contact holes and increased continuously in the order in which a by adding the resistance ^R _Nsu iy ^R Pwell ^{value obtained for a} contact resistance becomes progressively smaller, ie in the order of the contact holes A to E. It was also found that in the case in which the product of the current amplification factors ß .., ßp of the two transistors is greater than 1, an attempt to reduce the current gain factor B _{2 of} the vertical transistor Tr ₂ by forming a

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p-protective layer with a layer depth χ. when making

j of the contact holes A, B, C still no suppression of the abnormal current allows. However, when the contact holes are formed in the same manner as the contact holes D, E the arrangement was a p-type protection layer of greater depth for the prevention of the occurrence of an abnormal one

shown,

Current effective. As in Fig. 5 ^{/ type} . In Fig. 8, a solid line, a dashed line and two dash-dotted lines in the manufacture of a semiconductor wafer or a semiconductor wafer applied treatment or setting times of 20 hours, 40 hours and 6o hours. It can be seen from Fig. 8 that when the contact holes A, B, C are formed in the manner described in connection with Fig. 7, an abnormal current occurs regardless of the setting time when the product of the current amplification factors β., Βp of the bipolar transistors is greater is 1. When the contact hole D is arranged, an abnormal current occurs in a semiconductor device manufactured with 20-hour heat treatment when the base width W, of a transverse transistor Tr _{1 is} made 50 microns, while in a semiconductor device with 60-hour heat treatment was established, no abnormal current flow occurred.

In Fig. 9, the base width of a transverse transistor Tr _{1 is} plotted on the abscissa, while the size of an input signal current and a minimum level V- ~ _{MTW of} the power supply voltage for the development of an abnormal current are plotted on the ordinate.

Fig. 9 illustrates the occurrence or non-occurrence of the abnormal current in the contact hole D with the base width of a transverse transistor Tr being varied. When the base width W _{1 of} the transverse transistor is 70 microns, the abnormal current does not occur

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while at a base width W, of J> o microns, an abnormal current flow can actually be observed. With a base width W ₁ of 50 microns, the occurrence of the abnormal current flow depends on the type of die itself or the length of the heat treatment time. In the case of the contact hole D, therefore, a critical condition for the occurrence of an abnormal current flow is considered to be that the base width W- of the transverse transistor is 50 microns. Fig. 9 shows that at W ₁ = 50 microns, set time = 20 hours or depth x. the p-type protection layer = 8 microns, the occurrence or non-occurrence of abnormal current flow depends on the type of the semiconductor die. As a result, a heat treatment or setting time / of 20 hours becomes necessary

viewed. When heat treated for 20 hours, the base of a vertical _{transistor Tr 2 has a width W of 5.24 microns.} In the case of W-, = 5 ° microns and V / = 5 * 24 microns, a product of the current gain _{factors B 1} , βg- = 2.0 χ to ² χ 2.4 ο results from FIGS. 4 and 5 " ² = 4.8. It is therefore understood from Fig. 6 that, in the case of the contact hole D, a limit region determining the occurrence or non-occurrence of an abnormal current is at a position where the product of the current amplification factors β1, βp of the bipolar transistors is dem This means that an abnormal current flow can be suppressed with the contact hole D even in the area in which the product of β., Βp is greater than 1.

Further experiments showed that in the case of the contact hole E, a region in which the product of the current amplification factors β ..., β _{2 of} the bipolar transistors shown in FIG. 6 is 8.1 is a limit determining the presence or absence of an abnormal current represents. 3 in the continuous formation of a contact hole from D to E.

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the distance between the contact hole and the semiconductor substrate or the protective layer is further shortened, whereby the area of that portion of W ₁ , W _yJ in which no abnormal current is generated is increased accordingly, so that a CMOS semiconductor device with a larger product of the current gains can be protected from an abnormal current. Namely, depending on the manner in which a contact hole is formed, it is possible to prevent the occurrence of abnormal current even in the case that the product of the current amplification factors β., Βp of the bipolar transistors is greater than 1.

The following experimental formula was developed to get the Expressing relationship between a current gain and the base width of the parasitic transistor .:

Current amplification factor ß = Kexp (-aW) (1o)

wherein:

K, a = coefficients

W = base width of a parasitic bipolar transistor

mean.

In addition, according to the invention, a parameter S related to the manner of formation of a contact hole was used, whereby the following formula was experimentally established, which gives the relationship between the base width W-, a transverse transistor Tr. And the base width W of a vertical transistor Tr ₂ , at which an abnormal current is suppressed:

^ -a ν (id

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wherein:

' ^Κ ν =

Values of a coefficient K according to formula (1o) for transverse transistor Tr ₁ and vertical transistor

Tr, -

m, η = values of a coefficient a according to formula (1o)

with transverse and vertical transistor Tr ₁ resp.

mean.

In the following, the above formula (11) is explained with reference to FIG. 6. The base width W of the cross transistor Tr ₁ is plotted on the ordinate, while the base width of the vertical transistor Tr is plotted on the abscissa ₂ W. Formula (11) indicates an area above a straight line whose intersection with the ordinate (not shown in FIG. 6)

is expressed. A change in the position of a contact hole or the way it is formed leads to a variation of <JT. Therefore, if the formation of a contact hole is shifted from A to E, the line according to formula (11), which is the limit area for the occurrence of an abnormal current, shifts indicates, in the downward direction parallel to a line which represents a product of the current amplification factors B ₁ , B ^ =, so that an area widens above a line according to formula (11), namely an area in which transverse and vertical transistors have a base width in which an abnormal current is suppressed.

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Therefore, when a contact hole is formed so that it corresponds to the factor £ according to the above formula (11), the operation of a parasitic bipolar transistor in which the product of the current gains larger than 1 can be controlled so that the occurrence of the abnormal Electricity is prevented.

As mentioned, the generation of an abnormal current can be prevented by a distance from the edge or the edge of a contact hole in the N ⁺ contact region of the p-Kahal-MOS transistor to the collector of the transverse transistor Tr ₁ or to the p-type protective layer and a Distance from the P ⁺ contact area of the η-MOS transistor to the collector of the vertical transistor Tr or to the n-semiconductor substrate or each of these distances is determined so that at both terminals of the resistor R "., Or the resistor Rp ^^ i a potential difference below of the level of the level voltage across the base and emitter of the transverse transistors Tr., Tr and below the level of the threshold voltage across the base and emitter of the vertical transistors Tr ₂ , Tr ₂ . In this case, the threshold voltage is selected to be about 0.5V.

If, in addition, the P ⁺ source region 3 of the p-MOS transistor is designed so that it has the same potential as the n-semiconductor substrate 1, the emitter and base of a parasitic bipolar transverse transistor, the base of which is formed by the semiconductor substrate 1, applied voltage is reduced to 0, whereby it in no way _{rises above the threshold voltage V th} across the emitter and base, whereby the actuation or activation of the parasitic bipolar transverse transistor is suppressed, ie prevented. As a result, the thyristor circuit shown in FIG. J> can not be formed, so that the CMOS. ' Semiconductor device before the occurrence of an abnormal

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Current is protected. Further, when the N ⁺ source region 7 of the η-MOS transistor is designed with the same potential as the p-protection layer 2 of a parasitic bipolar lateral transistor through the emitter and base, the base of which is formed by the protective layer 2 falls applied I Voltage down to 0 so that it is the threshold voltage; over emitter and base does not exceed what

i the actuation or activation of the parasitic bipolar | Cross transistor is suppressed. As a result, abnormal current does not occur in the f CMOS semiconductor device. The elimination of the abnormal current is also achieved in the case when the product of the current amplification factor β of the transverse transistor Tr ₁ and the current amplification factor β p of the vertical transistor Tr _{2 is} greater than 1.

In order to give the P ⁺ source region J> the same potential as in the case of the n-type semiconductor substrate 1, the N ⁺ contact region 9 is interconnected with this source region 5 and the power supply, while a contact hole can ^{furthermore be formed in the N + contact region 9,} which - as by Pig's scheme. Io and 11 shown - source, gate and drain electrodes of the p-channel MOS transistor over the entire surface of the n-type semiconductor substrate 1 encloses.

^{In order to give the N +} source region J the same potential as the p-type protective layer 2 in a similar manner ^{, the P +} contact region 6 is ^{interconnected with the N +} source region 7 and the power supply Vg _S , and in the P ⁺ contact region 6 can a contact hole can be formed which, as shown in FIGS. 1o and 1V, encloses the source, gate and drain electrodes of the n-channel MOS transistor over the entire surface of the p-protective layer. The parts in FIGS. 1o and 11 corresponding to the parts of FIGS. 2 and 7 are given the same reference

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numerals, so that a more detailed description of the schemes according to FIGS. 1o and 11 can be dispensed with. The means by which the P -source region J> of the p-MOS transistor is given the same potential as the n-semiconductor substrate 1 and the N -source region 7 of the n-MOS transistor is given the same potential as the p -Protective layer 2, can be applied at the same time, while optionally only one of these measures can be taken at a time.

The aforementioned means by which the relevant source areas the same potential is given as the semiconductor substrate or the protective layer, can continue with means for controlling a distance between the relevant contact holes and the semiconductor substrate or the p-type protective layer be combined.

The invention is not just limited to a CMOS converter circuit,

on
but also / numerous other embodiments of CMOS circuits, including a thyristor circuit. As can be seen, the CMOS device can be formed by disposing an η protective layer in the p-type semiconductor substrate.

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Claims (1)

Claims Complementary MOSFET or CMOS semiconductor device with a first area of one conduction type, a second area of the opposite conduction type formed in the first area, a first MOS transistor of one channel type provided in the first area and a second MOS transistor provided in the second area of the opposite channel type, characterized in that the source electrode of at least one of the two MOS transistors (QI, Q ₂ ) is designed so that it has the same potential as the region (1 or 2) in which at least one of the two MOS transistors' (Q .., Qp) is provided. 2. Apparatus according to claim 1, characterized in that the first area is a semiconductor substrate, that the second area is a protective layer (well layer) and that the source electrode of the first MOS transistor is the same Has potential like the substrate. 5. Apparatus according to claim 2, characterized in that a product of a current gain factor of a parasitic bipolar transistor whose base is represented by the Substrate is formed, and the current amplification factor of a parasitic bipolar transistor, the base of which is formed by the protective layer, is greater than 1. k. Device according to Claim 2, characterized in that a device formed in the substrate and connected to the source electrode 809 883/099 3 of the first MOS transistor and a power supply interconnected first contact area and one formed on the surface of the contact area first contact hole source, gate and drain electrode of the first MOS transistor over the entire area of the Enclose the substrate away. 5. Apparatus according to claim 1, characterized in that the first region is a semiconductor substrate and the second Area is a protective layer (well layer) and that the 'source electrode of the second MOS transistor is the same Has potential like the protective layer. 6. Apparatus according to claim 5 * characterized in that a product of the current amplification factor of a parasitic bipolar transistor whose base is represented by the Substrate is formed, and the current amplification factor of a parasitic bipolar transistor, the base of which is formed by the protective layer, "is more than 1. 7. Device according to claim 2, characterized in that a / substrate formed and with the source electrode of the second MOS transistor and a power supply interconnected first contact area and a the surface of this contact region formed second contact hole source, gate and drain electrode of the enclose second MOS transistor over the entire area of the protective layer. 8. The device according to claim 1, characterized in that a first and a second area in the first and second area Contact area formed and jointly to the source 609883/0993 Electrodes of the first and the second MOS transistor are connected that on the surface of the concerned Contact areas a first and a second contact hole are provided and that the distance from the edge of at least one of these contact holes to the border edge between the first and the second area is set so that the activation or actuation of at least one of the two parasitic bipolar transistors, the base of which is formed by the first area or the second area, suppressed will. 609883/0993