DE2631916B2 - Differential amplifier built on a semiconductor chip with MOS field effect transistors - Google Patents

Description

a) a second current source transistor constructed similarly to the first current source transistor (Li) (Li '),

b) a third amplifier transistor constructed similarly to the first amplifier transistor (Mi) (M, ') and

c) a third load resistor (Λ / ι ') constructed similarly to the first load resistor (/ Vi) ^Jn,

and characterized by the following electrical connections:

d) Control input of the second power source transi- ^! 'stors (Li') with the output of the third amplifier transistor ( M-, '),

e) Gates of the third amplifier transistor to ground and

f) Output of the third amplifier transistor (M ₁ ') ⁴ "to the control input of the first current source transistor (Li).

2. Differential amplifier according to claim 1, characterized by an amplifier (K) having a gain factor k 4 ^r > between the output of the third amplifier transistor (Mi ') and the control input of the second current source transistor (L ₁ ') (Figs. 2,3) .

3. Differential amplifier according to claim 1 or 2,><> characterized in that the first current source transistor (Li) and the similarly constructed second current source transistor (Li ') are formed from MOS transistors, which by the control bias applied to their gates (Up ₀ ) are controllable. r>

4. Differential amplifier according to one of claims 1-3, characterized in that the first and third load resistors (N ₁ , N \ ') are MOS transistors which work in the ohmic range.

5. Differential amplifier according to claim 4, characterized by a series connection of the second current source transistor (L /) with the third amplifier transistor (Mi ') and with the third load resistor (N]') between the first and second DC power supply line (At, A ₂ ), where the M gate of the third amplifier transistor (Mi ') to ground and its output to the gate of the second and where the control bias (Up ₀ I) at the output of the third amplifier transistor (Mi') to the gate of the first current source transistor (Li) is applied

6. Differential amplifier according to claim 4, characterized by a series connection of the second current source transistor (Li '), which is connected in parallel to the third amplifier transistor (Mi'), with the third load resistor (Ni ') between the first and second DC power supply line (Λι, A ₂ ), the common output of the second current source transistor (Li ') and the third amplifier transistor (Mi') being connected to the gate of the second current source transistor (Li '), and the control bias voltage (Up ₀ I) at the output of the second current source transistor (L /) is applied to the gate of the first current source transistor (Li) of the differential amplifier

7. Differential amplifier according to one of claims 1-6, characterized in that the gates and sinks of the first and third load resistors (Nu / Vi ') are at the same potential and are connected to the first direct current supply line (Ai).

8. Differential amplifier according to one of claims 1-7, characterized in that it works with common-mode negative feedback and that the sinks (5 ,, S ₂ ) of the first and second are located between the first and second direct current supply lines (Au A2) MOS amplifier transistor (Mi, M2) via the first or second load resistor (Ni, N2) are connected to the first DC power supply line (Λι) and that the inputs of an adder to the sinks (Si, S ₂ ) of the amplifier transistors (Mi, M ₂ ) are connected, a current source transistor (M5) and the output of the adder between the common sources of the amplifier transistors (Mi, M ₂ ) and the second DC power supply line (A ₂ ) are connected in series (Fig. 6).

9. Differential amplifier according to claim 8, characterized in that the first and second load resistance (Ni, N ₂ ) are operated in the ohmic range MOS transistors, of which are connected: the gates and sinks galvanically to the first DC power supply line (A ₁ ) and the Sources to the corresponding sinks (Su S ₂ ) of the first and second amplifier transistor (Mi, M ₂ ).

10. Differential amplifier according to claim 8 or 9, characterized in that the adder has two parallel-connected MOS adding transistors (M _b , Mt) , of which are connected: the gates to the sinks (Si, S ₂ ) of the amplifier transistors (Mi, M ₂ ), the sinks to the source of the current source transistor (M ₅ ) and the sources galvanically to the second DC power supply line (A2).

i ') connected

The invention relates to a differential amplifier built on a semiconductor chip with MOS field effect transistors with compensation of the voltage fluctuations at the output of the amplification in common mode according to the preamble of claim I.

Differential amplifiers of this type are common. In practice, however, it is not possible to determine the quality or Quality of each individual component of the so formed

are to check the integrated MQS test, as the dimensions

Integrated circuit solutions are very small and these are mass-produced. A differential amplifier has two input voltages fed, the difference of which is to be amplified The difference is represented by two amplified voltages at the two outputs of the differential amplifier

Technologically conditioned parameter fluctuations can lead to the amplifier transistors working outside their normal operating range, d. h, outside the linear part of the control characteristic. This results in an undesirable imbalance in the gain of the differential amplifier, i. h that Output voltage fluctuations occur in common mode.

It is the task of a compensation arrangement to avoid such an asymmetry in the gain of the differential amplifier mentioned at the beginning.

The object is achieved by the characterizing features of claim 1

The invention is further developed by the features of the subclaims.

While with differential amplifiers whose current sources have a bipolar transistor, the two is assigned to bipolar transistors, the bias voltage of which is controllable (compare IBM Technical Disclosure Bulletin, Vol. 6 (August 1963) No. 3, pp. 70/71; Electronics technician, Vol. 11 (1972) H. 5, pp. 221-228) are the gain factors in MOS transistors by geometric Parameters and, in contrast to bipolar transistors, depend only slightly on the current im Work area.

In the invention it is achieved that the amplifier transistors in the favorable part of the control characteristic can work, d. In other words, the operating point is on the one hand in the linear part of the control characteristic of each amplifying transistor, with offset voltages in addition are avoidable. In order to achieve this and a centering on a so-called "rest point" of the To achieve the control characteristic of the amplifier, the requirement is met that the sum of the output potentials is zero or constant at both amplifier transistors.

That means the polarization or control bias is constantly applied to the supply current source for the two matched amplifier transistors arranged in parallel, the supply current source generally also is formed by a MOS transistor, to whose gate the control bias is applied.

It is essential in the invention that a simulation of at least part of the differential amplifier is used, where components use! are the components of the to be compressed Differential amplifiers are as similar as possible, so that technologically-related parameter fluctuations of the Components of the differential amplifier to be compensated for the fluctuations in the correspond to similar components of the compensation arrangement or simulation. This creates a Change of the control bias of the supply current source of the differential amplifier and an automatic Readjustment of the working point of the amplifier components depending on the technological parameter fluctuations achieved in such a way that as desired the sum of the output voltages zero or one is a predetermined constant value. The value of the! Muedanz des StrorpCiueNentransistorx. Which is controllable.

is connected to a steaer input of the supply current source applied control bias determined whereby the current flowing to two between the Spe-sesiromquelle and a DC voltage source Amplifier transistors connected in parallel divides The two currents flow through the amplifier transistors in two load resistors, preferably also formed by MOS transistors, their gates and Lowering at the same negative voltage of the

ίο DC voltage source, each between the Amplifier transistors and the DC voltage source are arranged The gates of the amplifier transistors of the differential amplifier are connected to signal sources whose voltages are to be amplified.

The components of the compensation arrangement (simulation) are chosen so that their dependency of the technologically conditioned parameter fluctuations are described by the same law can be.

2 «The compensation arrangement is therefore with respect to the most important components identical to the assigned differential amplifier, but with the compensation arrangement statically works and the gate of at least one amplifier transistor? is grounded.

2 "> The structure ensures that the control bias of various technological parameters is controlled so that these are in turn compensated so that the MOS amplifier transistors of the Differential amplifier a constant output voltage

! <) form the investment sum. In an advantageous embodiment the invention is the compensation arrangement (replica) together with a bilateral or differential amplifier with negative feedback is used in common mode. This differential amplifier has two

η DC voltages (z. B. - V and + V), which supply the amplifier with current, also two MOS amplifier transistors, the gates of which are each connected to a signal source, which emit the voltages to be amplified. Amplified voltages are generated at the drains of these amplifier transistors; the sinks are each connected to a load resistor to the positive DC voltage. These load resistors are, for example, MOS transistors that work in the ohmic range. The differential amplifier

4Ί also has a current source transistor, whose gate is connected to the control bias of the compensation arrangement or simulation, and an adder, the inputs of which are each connected to a drain of the amplifier transistors. Of the

■ Ι «The current source transistor and the adder are in series connected, between the common sources of the MOS amplifier transistors and one Supply line of the DC voltage source. An advantageous embodiment of the adder is a parallel

"> ■"> circuit of two MOS transistors, their gates with one sink each of the amplifier transistors are connected.

The invention will now be explained in more detail with reference to the drawing. It shows

w) F i g. 1 the circuit diagram of a common differential amplifier, to which the polarization arrangement according to the invention is applied,

F i g. 2 shows the basic circuit of a first embodiment of the simulation according to the invention, the

h "> structure corresponds to the differential amplifier according to Fig. 1, Fig. 3 shows a second embodiment of the simulation according to the invention with only one branch of the Differential amplifier according to F i e. 1.

F i g. 4 and 5 further exemplary embodiments without an amplifier between the output of an amplifier transistor and the gate of a current source transistor of the replica of FIG. 3, where F i g. 5 a preferred embodiment shows

F i g. 6 a differential amplifier, which is preferably used together with the simulation,

F i g. 7 shows an equivalent circuit of the preferred differential amplifier according to FIG. 6th

F i g. Figure 1 shows a differential amplifier of conventional construction to which the invention can be applied, as shown below. The amplifier has a current source represented by a first MOS transistor L \ , the source (source) of transistor L · being connected to a DC voltage + V and the drain (drain) to the sources of two amplifier transistors M \ and M ₂ . A control _bias voltage U po i , which determines the operating point of the amplifier transistors M \ and Mi , is applied to the gate of the first transistor L \ which feeds the amplifier transistors M \ and M _{2. The} amplifier transistors M \, M2 are connected via load resistors / Vi and N2 connected to a direct voltage - V. The load resistances N \, N ₂ are shown in FIG. 1 formed by MOS transistors that work in the ohmic range, and whose drains and gates are at the same potential - V. The two input voltages, the difference between which is to be formed, are applied to inputs E \ and Ei , which are connected to the gates of the amplifier transistors M \ and M2 . Output voltages Vs \ and Vs _{2 are} generated at outputs S \ and S _2.

F i g. 2 shows a basic circuit of the compensation arrangement according to the invention. This arrangement has the same components as the statically operated differential amplifier according to FIG. 1, the gates of a third and a fourth amplifier transistor M \ and M 2 being connected to ground. The outputs Si and 52 of the amplifiers: rtransistors M \, M ' ₂ are connected to an adder Σ which calculates the sum Vsi + Vs _2. This sum signal is fed into an amplifier K , the output of which is connected to the gate of a second current source transistor L \ , wherein the in the first current source transistor Li according to F i g. 1 fed in control bias Up ₀ I is applied to the gate of the transistor L \ . This arrangement is used to control or regulate the control bias voltage Up ₀ / depending on technological parameter fluctuations of the various transistors M, N, L, in order to ensure the constancy of the voltage sum at the output of the differential amplifier. To regulate the voltage Up ₀ / , a reference voltage is required, which is shown in FIG. 2 is represented by the negative voltage - V. The technological parameters such as the threshold voltages of the MOS transistors M \ and Mi (MI and M'2), the channel width of the MOS transistors and the geometric channel lengths of the MOS transistors fluctuate in the differential amplifier (Fig. 1) in the same way as in the Simulation (FIG. 2), which also applies to possible fluctuations in the voltage + V. More precisely, the transistor N \ in the arrangement according to FIG. 2 as well as in FIGS. 3, 4 and 5 represent a (third) load resistor operated in the ohmic range, the aspect ratio Z / L being less than one, with: Z = width of the charge carrier channel between sink and source, and L - geometric length of the MOS transistor channel. Like the transistor M, this transistor N \ is particularly sensitive to fluctuations ΔΖ \ ιηά AL in the channel width and length; it makes it possible to adjust the voltage U _po i as a function of these fluctuations in order to compensate for the concurrent fluctuations in the transistor N \.

The third amplifier transistor M \ is a MOS transistor, the gate of which is at ground (ie at the reference voltage zero V), and which allows the fluctuations of the DC voltage + V compared to the control bias voltage to be compensated. Finally, the second current wave transistor L \ , the channel width Z of which is important, is very sensitive to the threshold voltage Vs, which often fluctuates depending on the technology used. The second current source transistor L \ compensates for the fluctuations in the threshold voltage by readjusting the control bias voltage Upoi in accordance with these fluctuations in the threshold voltage Vs. It has been experimentally proven that the use of these three transistors in one of the four cases shown in FIG. ₂ , 3, 4 and 5 allow the fluctuations of the parameters + V, V 5, Z and L to be compensated.

The replica according to FIG. 2 is not optimal, since the relatively large number of transistors increases the number of causes of errors as well as the space requirement. Because of the interaction of the various components and because of the presence of the amplifier K , the arrangement also has a slow transient response. F i g. 3 shows a

$ 0 Arrangement that has only a single branch of the differential amplifier, ie the components M \ and N'i, which are as similar as possible to the transistors M \ (and M ₂ ) and TVi (and N ₂ ) of the differential amplifier. The component L \ is derived from L \ , taking into account that the current through L \ is only half as large as the current through L \ .

The embodiment according to FIG. 3 of the arrangement according to the invention dispenses with the two transistors M'2 and N ' ₂ , the technological parameter fluctuations of which run in the same sense as those of the transistors M \ and N \ , so that the two transistors M ₂ and / V _{2 are} redundant. The sink of the amplifier transistor M \ is connected via the amplifier K to the gate of the transistor Ζ.Ί, which is in the gate of the transistor Li of the differential amplifier according to F i g. 1 polarization voltage Up _{0 fed in}

F i g. 4 shows an arrangement without a differential amplifier K, the phase conditions between the output of the third amplifier transistor M \ and the gate of the second current source transistor L \ being met by the structure. The geometry of the transistors L \, M \ and N \ is identical to the geometry of the transistors according to FIG. The arrangement according to FIG. 4 works satisfactorily, although the circuit is not optimal, since the gate of the second current source transistor L \ is at high potential, whereby the sink-source voltage of the third amplifier transistor M \ is low and this works in the ohmic range instead of the amplifier range

An even better implementation, which is preferably used in the invention, is shown in FIG. 5, in which the transistors L \ and M \ are connected in parallel and are in series with the transistor N \ . The two DC voltages + \ and - V are connected to the series circuit. In this arrangement, the gate of the third amplifier transistor M \ is always ar ground, and the gate of the second current source transistor

stors L '\ is connected to the common output, ie to the sinks of the transistors L \ and M \ . In this circuit the transistor M \ works in amplifier mode, so that the circuit according to FIG. 5 delivers excellent results and generates an output control bias voltage Upoi which is suitable for regulating technological parameter fluctuations.

6 shows a differential amplifier with common-mode negative feedback, which is preferably used together with the polarization arrangement according to the invention. The differential amplifier has two MOS transistors Mi and M ₂ , the gates E] and E _{2 of} which are controlled by voltages or signals Vei and Vej emitted from signal sources (not shown), these voltages being connected to ground are related. The sinks Si and 52 of these transistors Mu M ₂ generate amplified voltages Vs \ and Vs ₂ , which are fed into the gates of transistors Me and Mj , which work as adding amplifier transistors of an adder Σ , and their sinks to produce a common mode -Coupling are connected to the source of a current source transistor Ms. The voltages applied to the transistors M ₆ and M ₁ connected in parallel influence the voltage applied between the gate and source of the current source transistor Mi and thus the current of the current source. The sources of the transistors Mt, and Mi are connected to a DC voltage line A ₂ , the potential of which is + VaidL The gate of the current source jo

Ks ₁ = A [Ve _x + ed _x - K [Vs ₁ + Vs ₂ - e)] ,
Vs ₂ = A [Ve ₂ + ed ₂ - K [Vs ₁ + Vs ₂ - «?)].

Lentransistor Λ / 5 is polarized or biased in that a terminal P is connected to a (not shown) compensation arrangement (replica) which supplies the control bias Upoi. The sink of the current source transistor M5 feeds the sources of the amplifier transistors M 1 and M ₂ . The load resistors N] and N ₂ work in the ohmic range, the gates and the sinks of these load resistors Ni and N ₂ formed by transistors being galvanically connected to a direct current supply line A] which is at the potential −V .

In order to limit the changes caused by technological parameter fluctuations as much as possible, the transistor pairs Mi, M ₂ and N \, N ₂ as well as Mr. M? made up of transistors that are as similar as possible to each other.

F i g. 7 represents an electrical equivalent circuit diagram of FIG. 6. The amplifier transistors M 1 and M ₂ are represented by amplifier A (with gain A) , the adding transistors Mf and M7 by an adder Σ, an amplifier K with a gain factor K being assigned to this adder. Voltages e, ed] and ed ₂ are offset voltages of amplifiers A and K.

The mathematical derivation of the results generated by the differential amplifier according to Fig. 1 and 2 obtained is as follows:

The output potentials V $ i and Vs _{2 are} calculated using the following equations:

After a simple algebraic transformation we get:

i / ^A i "" * ^A , j jv A TVe ₁ + Ve ₂ + ed _x + ed ₂ + 2Ke

] ■

Vs ₂ = - -J

Ve ₂ ) + y (ed, - ed ₂ ) + y Ve ₁ + Ve ₂ + erf, + ed ₂ +
1 + 2AK

According to the equations, the differential offset voltage (error voltage) of the voltage difference Ve \ - Ve ₂ at the input is given by ed] - ed ₂ . For this reason it is advantageous to work differentially (the difference between the voltages being smaller than each offset voltage itself) and to ensure that the amplifiers A (represented by the amplifier transistors M] and M ₂ ) are as similar as possible. If the amplifiers are identical, ed \ = ed ₂ applies and the differential offset voltage is zero.

The non-differential offset voltage V _o n at the system input is calculated as follows:

ed ₂

Ve ₁ + Fe ₂ + ed _x + ed ₂ + 2Ke 1 + 2AK

55

60

The equation shows that the influence of the technological parameter fluctuations (ed], edi and e) as well as the value of the input parameters Vei and Ve ₂ have only a slight influence on the offset voltage V _o n if the factor (1 + 2 AK), the so-called common-mode rejection, large is the common-mode offset voltage e (asymmetry of the common-mode gain) of the amplifier, the offset voltage of the adder transistors Me and M ₇ multiplied by the factor K, shows the interest in reducing K, with the product AK being constant in this way Common-mode negative feedback can be implemented very easily with a minimal number of components, with rapid negative feedback in particular being achievable

The transistor pair Mt and Mi also introduce a series resistance which _{reduces the output resistance of the current source formed by the transistors M 5} , M ₆ and M ₇ by reducing the slope of the current-voltage characteristic.

For this purpose 3 sheets of drawings

Claims (1)

Patent claims: 1. Differential amplifier built on a semiconductor chip with MOS field effect transistors with Compensation of the voltage fluctuations at the output of the amplifier in common mode operation, with a first current source transistor arranged between a first and a second direct current supply line, the impedance of which is controllable by a high voltage, which supplies a direct current which is based on the first and second. Field effect transistor divides and flows through a first and second load resistor, which is arranged between the first and second field effect transistor and the first DC power supply line, the gates of the FsldeffckttransL-Joren are connected to signal sources whose signals are to be amplified, characterized by one between the first and a second DC power supply line (Au A ₂ ) arranged replica of a differential amplifier, or one half of a differential amplifier, which contains at least: