DE2631916A1 - POLARIZATION ARRANGEMENT FOR DIFFERENTIAL AMPLIFIER - Google Patents

Description

Patent attorneys

Dipl.-Ing. R. B E E T Z sen.

Dipl.-Ing. K. LAMPRECHT Dr.-Ing. R. B E E T Z jr.

8000 Munich

Steinsdorfstrasse 1O

Tel. (089) 22 72 01/227244/295910

Telegr. Allpatent Munich Telex 5 22048

410-25.801P

l5. 7th 1976

Commissariat a! 'Energie Atomique, PARIS (France)

Polarization arrangement for differential amplifiers

The invention relates to a polarization arrangement or a circuit arrangement for generating a bias voltage for differential amplifiers,

The invention relates in particular to integrated, constructed from MOS field effect transistors Differential amplifier.

In practice, it is not possible to integrate the quality or quality of each individual component Circuits and especially in integrated MOS circuit

41O- (B5685 / 573O.3) -DWS1

608883/0981

lines to control, since the dimensions of the integrated circuits are very small and these in Can be mass produced. It is therefore imperative to have compensated integrated circuits to develop where imperfections of the transistors and associated technology-related parameter fluctuations are automatically compensated, namely without setting or adjusting the individual components.

The invention preferably relates to a polarization arrangement for a differential amplifier, which by two input voltages is fed, their difference should be strengthened. This difference is caused by two amplified voltages at the two outputs of the Differential amplifier shown.

Technologically conditioned parameter fluctuations can cause the amplifier transistors to operate outside of their normal operating range, i. H. outside of of the linear part of the transfer characteristic. To get the transistors working in the favorable part of the To ensure the transfer characteristic, the voltage difference at the output must be in the case of an input voltage difference Zero must also be zero, i.e. H. the operating point must on the one hand be on the linear part of the transfer characteristic each amplifier transistor must be placed, on the other hand, voltage offset voltages must be avoided will. In order to achieve this and to center it on the so-called "rest point" of the above-mentioned transfer characteristic of the amplifier, it is required that the sum of the output potentials at both amplifier transistors is zero or constant.

For this purpose, the polarization voltage is constantly in a suitable manner, which will be explained in more detail below

609bö3 / 098

Way to the power source for the "two in parallel." arranged amplifier transistors (the supply current source is generally a transistor, to whose Gate the polarization voltage is applied).

More precisely, uses a polarization arrangement according to the invention for differential amplifiers a copy or replica of at least part of the amplifier circuit, which is made up of individual components (preferably field effect transistors) that form the components of the actual differential amplifier are as similar as possible, so that technological parameter fluctuations of the components of the differential amplifier to the fluctuations in the same sense of the similar components of the Corresponding polarization arrangement. This causes a change in the polarization voltage of the supply current source of the differential amplifier and an automatic readjustment of the operating point of the amplifier components depending on the technological parameter fluctuations achieved in such a way that the sum of the output voltages Is zero or a predetermined constant value.

The polarization arrangement according to the invention for differential amplifiers relates to a differential amplifier with a supply current source that generates a controllable current. The value of this current is given by a polarization voltage applied to a control input of the supply current source is determined, the Current on two amplifier transistors connected in parallel between the supply current source and a DC voltage source divides. The two currents flow through the amplifier transistors in two load resistors (preferably transistors whose gates and collectors or sinks at the same negative voltage of the DC voltage source), each between the

ι; π 9 S H '\ l ü 9

2637916

Amplifier transistors and the source of equal delay are arranged. The gates of the amplifier transistors of the differential amplifier are connected to signal sources, whose tensions are to be increased. The property Polarization arrangement is formed by replicating part of the differential amplifier, wherein this replica has at least one supply current source, an amplifier transistor and a load resistor having. The control input for the supply current source is connected to the amplifier transistor whose Gate is grounded. The components of the polarization arrangement are selected in such a way that they correspond to the corresponding Components of the actual differential amplifier if possible are similar, so that their dependence on technologically conditioned parameter fluctuations by the same Lawfulness can be described.

In this way, the polarization arrangement is identical to one with respect to the most important components assigned amplifier stage of the differential amplifier. However, the polarization arrangement works statically, wherein the gate of the amplifier transistor is grounded. The output of this amplifier transistor is to the Control input of the supply current source connected, namely to the gate of a supply current source transistor of the differential amplifier, this transistor between a voltage of the direct current source and the sources of the amplifier transistors of the differential amplifier. As explained in more detail below, the Polarization voltage controlled by various technological parameters determined by the polarization voltage are compensated in such a way that the MOS amplifier transistors generate a constant voltage sum.

In an advantageous embodiment of the invention, the polarization arrangement according to the invention is combined

b09883 / 0981

with a negative feedback on both sides or in common mode Differential amplifier used. This differential amplifier has two DC voltages (e.g. -V and + V) that supply the amplifier with power, as well as two MOS amplifier transistors, each of whose gates are connected to a signal source are connected, which emit the voltages to be amplified. At the sinks of these amplifier transistors increased stresses are generated; the sinks are furthermore each connected to a load resistor positive DC voltage connected. These load resistors are, for example, MOS transistors that are im ohmic area work. The differential amplifier also has a current source transistor whose gate is connected to the polarization voltage of the polarization arrangement, as well as an adder whose inputs are each connected to a sink of the amplifier transistors. The current source transistor and the adder are connected in series between the common sources of the MOS amplifier transistors and a supply line the DC voltage source. An advantageous embodiment of the adder is a parallel connection of two MOS transistors, the gates of which are each connected to a drain of the amplifier transistors.

The invention will now be explained in more detail with reference to the drawing. Show it:

Pig. I the circuit diagram of an already developed

Differential amplifier to which the polarization arrangement according to the invention is applied;

2 shows the basic circuit of a first exemplary embodiment of the polarization arrangement according to the invention, the structure of which corresponds to the differential amplifier corresponds to Fig. 1;

fa "09883/0981

3 shows a second exemplary embodiment of the invention Polarization arrangement with only one branch of the differential amplifier according to FIG

4 and 5 further exemplary embodiments without an amplifier between the output of an amplifier transistor and the gate of a supply current source transistor the polarization arrangement according to Fig. 3> where Fig. 5 is one in the invention shows preferred embodiment;

6 shows a differential amplifier which, together with the polarization arrangement according to the invention is preferred j

FIG. 7 shows an equivalent circuit of the preferred differential amplifier according to FIG. 6.

Fig. 1 shows a previously developed differential amplifier to which the polarization arrangement according to the invention can be applied, as will be shown below. The amplifier v / eist a current source represented by a MOS transistor L, wherein are connected: the source of the transistor to a DC voltage + V and the sink to the sources of two amplifier transistors M, and Mp. To the gate or gate of the The transistor L feeding the amplifier transistors M and Mp is applied with a bias or polarization voltage U-, which determines the operating point of the amplifier transistors M and Mp. The amplifier transistors are connected to a direct voltage - V _{via load resistors N 1 and Np.} The load resistances are represented according to FIG. 1 by MOS transistors which operate in the ohmic range, and whose drains and gates are at the same potential - V. The two input voltages

609-83 / 0981

- Ύ -

whose difference is to be formed are applied to * inputs E ₁ and E ₂ , which are connected to the gates of the transistors M and Mp. Output voltages Vs. and VSp are generated at outputs S and Sp.

Fig. 2 shows a basic circuit of the polarization arrangement according to the invention. This arrangement has the same components as the statically operated differential amplifier according to FIG. 1, the gates of amplifier ^{transistors M 1} and M'p being grounded. The outputs S, and Sp of the amplifier transistors are connected to an adder Σ '. connected, which _{calculates the sum Vs 1} + VSp. This sum signal is fed to an amplifier K, the output of which is connected to the gate of a current source transistor L ^1, wherein the power fed to the transistor L, according to Fig. 1 polarization voltage U, is applied to the gate of the transistor ^L1 is applied. This arrangement is used to control or regulate the polarization _{voltage U 1 as a} function of technological parameter fluctuations in the various transistors M, N, L, in order to ensure the constancy of the total voltage at the output of the differential amplifier. To regulate the voltage U, a reference voltage is required, which is represented in FIG. 2 by the negative voltage - V. The technological parameters such as the threshold voltages of the MOS transistors M. and Mp (M ', and M'p), the channel width of the MOS transistors and the geometric channel lengths of the MOS transistors fluctuate in the differential amplifier in the same way as in the polarization arrangement, which also applies to possible fluctuations in the voltage + V. More precisely, the transistor N ¹ in the arrangement according to FIG. 2 as well as in FIGS. J5, 4 and 5 represents a load resistor operated in the ohmic range, the aspect ratio Z / L being less than one, with: Z = width of the Load carrier channel

GUii8H3 / 098i

between sink and source, and L = geometric length of the MOS transistor channel. This transistor N ¹ , like N-, is particularly sensitive to fluctuations Az and Al of the channel width and length; it makes it possible to adjust the voltage U- as a function of these fluctuations in order to compensate for the concurrent fluctuations in the transistor N.

The transistor M 'is a MOS transistor whose gate is at ground (ie at the reference voltage zero V) and which allows the fluctuations of the DC voltage + V with respect to the polarization voltage to be compensated. Finally, the transistor L ', the channel width Z of which is important, is very sensitive to the threshold voltage Vo, which often varies depending on the technology used. The transistor L ¹ * compensates for the fluctuations in the threshold voltage by readjusting _{the polarization voltage U 1 in} accordance with these fluctuations in the threshold voltage V _Q. It has been experimentally proved that the use of these three transistors in one of the four cases shown in FIG. 2, j5 * ² J- 5 and a compensation of the fluctuations of the parameters + V, V _g, Z and L permitted.

The polarization arrangement according to FIG. 2 is not optimal, since the relatively large number of transistors increases the number of causes of errors and the space requirement. Because of the interaction of the various components and because of the presence of the amplifier K, the arrangement also has a slow transient response. 5 shows an arrangement which has only a single branch of the differential ^{amplifier, ie the components M 'and N 1} , which are as similar as possible to the transistors M _{1 (and M 2} ) and N (and Np) of the differential amplifier. The component L ^f .

6 09883/0981

is derived from L., taking into account that the The current through L 'is only half as large as the current through L.

The embodiment according to FIG. 3 of the arrangement according to the invention dispenses with the two transistors M'p and N'p, whose technological parameter fluctuations run in the same sense as those of the transistors M ¹ and N ', so that the two transistors M'p and N 'p are redundant. The sink of the amplifier transistor M '^ is connected via the amplifier K to the gate of the transistor L', which is fed into the gate of the transistor L _{1 of} the differential amplifier according to Pig. I fed in polarization voltage U- generated.

4 shows an arrangement without a differential amplifier K, the phase conditions between the output of the transistor M 'and the gate of the transistor L ¹ being met by the structure. The geometry of the transistors L ',, M', and N ¹ is identical to the geometry of the transistors of FIG. 3. The arrangement of FIG. 4 operates satisfactorily, although the circuit is not optimal, since the gate of transistor ₁ IZ is at high potential, as a result of which the sink-source voltage of the transistor M 'is low and this transistor operates in the ohmic range instead of in the amplifier range.

An even better one and preferred in the invention Implementation used is shown in Fig. 5, in which the transistors L ', and M'. connected in parallel and are in series with transistor N '. The two DC voltages + V are connected to the series circuit and - V connected. In this arrangement the gate of the transistor M 'is always connected to ground and the gate

609883/0981

-lO-

of the transistor L ¹ is at the commonest output, ie at the drains of the transistors L '. and M ¹ . connected. ^{The transistor M 1} operates in this circuit. in amplifier mode, so that the circuit according to FIG. 5 delivers excellent results and generates an output polarization voltage U, which is suitable for regulating technological parameter fluctuations.

6 shows a differential amplifier with common-mode negative feedback, which is preferably used together with the polarization arrangement according to the invention. The differential amplifier has two MOS transistors M ₁ and M 2, the gates of which E 1 and Ep are provided by voltages and signals Ve. and Vep, which are output by signal sources (not shown), these voltages being referenced to ground. The sinks S, and S _? these transistors generate boosted voltages Vs. and VSp, which are fed into the gates of transistors Mg and M ₇ . are fed, which work as adding amplifier transistors of an adder, and whose sinks are connected to the source of a transistor Mp- to generate a common-mode negative feedback. The voltages applied to the transistors Mg and M ₇ connected in parallel affect that between the gate and source of the transistor ?; Mc- applied voltage and thus the current of the power source. The sources of the transistors Mg and M ₇ . are connected to a DC voltage line Ap, the potential of which is + V. The gate of the transistor Mj- is polarized or biased by connecting a terminal P to a polarization arrangement (not shown) which supplies _{the polarization voltage U 1.} The sink of the transistor M ^ feeds the sources of the transistors M, and Mp. The load resistors N ₁ and Np work in the ohmic range, with the gates and the sinks the-

609883/0381

- ii -

These transistors N and N _{2 are} galvanically connected to a power supply line A ₁ which is at the potential - V.

In order to limit the changes caused by technological parameter fluctuations as much as possible, the transistor pairs M ₁ , M ₂ and N ₁ , N ₂ and Mg, My are made up of transistors that are as similar as possible to one another.

7 shows an electrical equivalent circuit diagram of FIG. 6. The transistors M ₁ and M ₂ are represented by amplifier A (with gain A), the transistors Mr and Mr by an adder % , with this adder being an amplifier K is assigned with a gain factor K. Voltages e, edj and ed ₂ are offset voltages of amplifiers A and K.

The mathematical derivation of the results obtained by the differential amplifiers of FIGS. 1 and 2 is as follows:

The output potentials Vs ₁ and Vs _{2 are} calculated using the following equations:

Vs ₁ = A JVe ₁ + Bd ₁ -K (Vs ₁ + Vs ₂ - e) J Vs ₂ = A JVe ₂ + ed ₂ - K (Vs ₁ + Vs _g - e) J.

Obtained after a simple algebraic transformation

man:

A - Ve ₂ , + f

_nl Ve + Ve _o + ed ₁ + ed _o + 2Ke - ed ₂ , + f * ² * 2 ¹ 1 + 2 AK

Ve + Ve ₂ + ed ₁ + ed ₂ + 2Ke

1 + 2 AK

609883/0981

According to the equations, the ⁴ 'offset voltage (error voltage) is the voltage difference Ve. - Ve «given at the entrance by ed ^ - ed ₂ . For this reason it is advantageous to work differentially (the difference in the voltages being smaller than each offset voltage itself) and to ensure that the amplifiers A (represented by the transistors M. and Mp) are as similar as possible. If the amplifiers are identical, ed. = Edp and the differential offset voltage is zero.

The non-differential offset voltage V _off . at the system entrance is calculated as follows:

Ve + Ve + ed + ed. + 2 Ke

The equation shows that the influence of the technological parameter fluctuations (ed .., ed ₂ and e) and the value of the input parameters Ve. and Ve ₂ has only a slight influence on the offset voltage V _ff when the factor (1 + 2 AK), the so-called common-mode rejection, is large. The common-mode offset voltage e of the amplifier, the offset voltage of the adder transistors Mg and M ₇ multiplied by the factor K ₁ shows the interest in a reduction in K, the product AK being constant. In this way, common-mode negative feedback can be implemented very easily with a minimal number of components, with rapid negative feedback in particular being achievable.

A series resistance is also introduced by the transistor pair Mg and My, which increases the output resistance of the transistors Mp-, Mg and M ₇ . The current source formed is reduced by reducing the slope of the current-voltage characteristic.

609883/0981

Claims (10)

Claims il. Polarization arrangement for a differential amplifier with a first supply current source arranged between a first and a second direct current supply line for generating a feed current that can be controlled by a polarization voltage applied to the first feed current source , which is on a parallel between the first supply current source and the first DC power supply line switched first and second amplifier transistor and divided by a first and second load resistor that flows between the first and second amplifier transistors and the first DC power supply line arranged sist, wherein the gates of the amplifier transistors are connected to signal sources whose signals are amplified should be marked by one between the first and second DC power supply lines (A ,, Ap) arranged replica of a part of the differential amplifier, which has at least: ^{a second feed current source (L 1} ,) constructed similarly to the first feed current source (L,), 809883/098 1 one constructed similarly to the first amplifier transistor (M) third amplifier transistor (M '), and a third load resistor (N ') constructed similarly to the first load resistor (N.), wherein: a control input of the second supply current source (L ') is connected to the output of the third amplifier transistor (M '), and the gate of the third amplifier transistor (M') to ground, and the output voltage of the third amplifier transistor (M ¹ ) being applied to the first supply current source (L.) of the differential amplifier (Fig. 1-5) 2. Polarization arrangement according to claim 1, characterized by an amplifier (K) having a gain factor between the output of the third amplifier transistor (M ') and the control input of the second supply current source (L ^ ₁ ) (Fig. 2, 3). 3. polarization arrangement according to claim 1, characterized in that that the first supply current source (L) and the simulated second supply current source (L ') consist of MOS transistors are built up by the polarization voltage applied to their gates (U ..) are controllable (Fig. 1 - 5) · 4. polarization arrangement according to claim 1, characterized in that the first and third load resistance (N., N ¹ ^) are MOS transistors which work in the ohmic range (Fig. 1-5). 609883/098 2831316 5. polarization arrangement according to claim 4, characterized by a series connection of a second supply current source transistor (L ¹ ) with the third amplifier transistor (M ¹ ) and with the third load resistor (N ') between the first and second DC _{supply line (Α., A 2} ), wherein the gate of the third amplifier transistor (M ') is connected to ground and its output is connected to the gate of the second supply current source transistor (L'.,), and the polarization voltage (U,) at the output of the third amplifier transistor (M ') is applied to the gate of a first supply current source transistor (L ₁ ) (Pig. ² O. 6. polarization arrangement according to claim 4, characterized by a series connection of the second supply current source transistor (L '), which is connected in parallel to the third amplifier transistor (M'), with the third load resistor (N ') between the first and second DC power supply line (A, A ₂ ), the common output of the second supply current source transistor (L ') and the third amplifier transistor (M') being connected to the gate of the second supply current source transistor (L '), and the controlling polarization voltage (U,) at the output of the second supply current source transistor (L ') is applied to the gate of the first supply current source transistor (L ₁ ) of the differential amplifier (Fig. 5) 7. polarization arrangement according to claim 1, characterized in that the gates and sinks of the first and third load resistors (N ₁ , N ') are at the same potential and are connected to the first DC power supply line (A.) (Fig. 2-5). 8. polarization arrangement according to claim 1, characterized in that that the differential amplifier is a differential amplifier with common mode negative feedback between the first and 609883/0981 and second DC power supply line (Α., A ₂ ) is that the drains (S., Sp) of the first and second MOS amplification transistors (M, Mp) via the first and second load resistors (N j Np) to the first DC power supply line (A) are connected, and that the differential amplifier has an adder, the inputs of which are also connected to the sinks (S., Sp) of the amplification transistors (M, Mp), a current source transistor (M) and the output of the adder between the common Sources of the amplifier transistors (M, Mp) and the second DC power supply line (Ap) are connected in series (Fig. 6). 9. polarization arrangement according to claim 8, characterized in that the first and second load resistance (N, N _p ) are operated in the ohmic range MOS transistors, of which are connected: the gates and sinks galvanically to the first DC power supply line (A.) and the sources to the corresponding sinks (S., Sp) of the first and second amplifier transistor (M., M _? ) (Fig. 6). 10. polarization arrangement according to claim 7 »characterized in that that the adder has two parallel-connected MOS adding transistors (M, -, M), one of which is connected are: the gates to the sinks (S, S ") of the amplification transistors (M, Mp), the sinks to the source of the current source transistor (M-) and the sources galvanically to the second DC power supply line (Ap) (Fig. 6).