DE2620783A1 - Insulated gate field effect transistor prodn. - using ion etching in structurising stage preventing under-etching - Google Patents
Insulated gate field effect transistor prodn. - using ion etching in structurising stage preventing under-etchingInfo
- Publication number
- DE2620783A1 DE2620783A1 DE19762620783 DE2620783A DE2620783A1 DE 2620783 A1 DE2620783 A1 DE 2620783A1 DE 19762620783 DE19762620783 DE 19762620783 DE 2620783 A DE2620783 A DE 2620783A DE 2620783 A1 DE2620783 A1 DE 2620783A1
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- insulating layer
- layer
- etching
- ions
- polycrystalline
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- 238000000992 sputter etching Methods 0.000 title claims abstract description 8
- 238000005530 etching Methods 0.000 title abstract description 11
- 230000005669 field effect Effects 0.000 title description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 150000002500 ions Chemical class 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000003631 wet chemical etching Methods 0.000 abstract description 4
- 238000010849 ion bombardment Methods 0.000 abstract 1
- 239000012212 insulator Substances 0.000 description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 230000000873 masking effect Effects 0.000 description 5
- 230000005855 radiation Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000012895 dilution Substances 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 102000004316 Oxidoreductases Human genes 0.000 description 1
- 108090000854 Oxidoreductases Proteins 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- -1 argon ions Chemical class 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052756 noble gas Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000007704 wet chemistry method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
- H01L21/32132—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only of silicon-containing layers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Ceramic Engineering (AREA)
- Weting (AREA)
Abstract
Description
Verfahren zur Herstellung eines Haibleiterbauelementes mitMethod for producing a semiconductor component with
Isolierschicht-Feldeffektstruktur und einer Gate-Elektro de aus polykristallinem Silizium, Die Erfindung betrifft ein Verfahren zur Herstellung eines Haibleiterbauelementes mit Isolierschicht-Feldeffektstruktur, wie es im Oberbegriff des Patentanspruches 1 näher angegeben ist.Insulating layer field effect structure and a gate electrode made of polycrystalline Silicon, the invention relates to a method for producing a semiconductor component with insulating layer field effect structure, as described in the preamble of the claim 1 is specified.
Im Herstellungsverfahren fur Halbleiterbauelemente mit Isolierschicht-Eeldeffektstrukur werden auf ein Substrat aus Silizium eine erste Isolierschicht, z.3. eine Schicht aus Siliziumdioxid, und darauf eine Elektrodenschicht aus leitfähigem Material, z.B.In the manufacturing process for semiconductor components with insulating layer Eeldeffektstrukur a first insulating layer, z.3. a layer made of silicon dioxide, and on top of it an electrode layer made of conductive material, e.g.
eine Metallschicht oder eine Schicht aus polykristallinem Silizffum,aufgebr2chte Aus diesen beiden auf dem substrat befindlichen Schichten werden im weiteren Verfahren sodann Strukturen herausgeätzt. Dabei wird zunächst die Gate-Elektrodenschicht aus polykristallinem Silizium mit einer Struktur versehen, und die so stru:rierte Schicht aus polykristallinem Silizium dient dann als Ätzmaske für die Ätzung der darunter befindlichen Gate-Oridschicht. Beim chemischen Ätzen der Gate-Oxidschicht kommt'es an den Refgebieten der polykristallinen Siliziumschicht, die als Gate-Elektroden vorgesehen sind, zu Unterätzungen. Die durch solche Unterätzung hervorgerufenen überhänge der Gate-Elektroden aus Polysilizium über die darunter befindlichen Gate-Isolatoren führen bei den nachfolgenden Verfahrensschritten, bei denen zum Anbringen von Zuleitungen und Leiterbahnen das Substrat, die darauf befindlichen Gate-Isolierschichten und die Gate-Elektroden mit einer zweiten Isolierschicht überzogen werden und sodann auf die zweite Isolierschicht eine Metallisierungsschicht zur Herstellung der Leiterbairnen aufgebracht wird, zu Störungen, weil an diesen Überhängen die aufgebrachten Schichten Verdünnungszonen aufweisen. Beim Herausätzen der Leiterbahnen treten an solchen Verdünnungszonen häufig Unterbrechungen der Leiterbahnen auf, was zu einem völligen Ausfall des Bauelementes führen kann. In verbesserten Verfahren wurde zum Vermeiden dieser Überhänge nach dem Aufbringen der zweiten Isolierschicht und vor dem Aufbringen der Leiterbahnachicht eine Phosphorglasschicht auf der zweiten Isolierschicht abgeschieden. Durch diese Phosphorglasschicht werden die Verdünnungszonen der zweiten Isolierschicht ausgeglichen. Bei diesem Verfahren ist allerdings nachteilig, daß die Phosphorglasschicht durch einen nur schwer zu kontrollierenden Hochtemperaturschritt zum Fließen gebracht werden muß. Weiterhintritt bei der Verwendung von Phosphorglas eine erhöhte Korrosionsgefahr für das Bauelement auf, und schließlich ist das Ätzen von Kontaktlöchern durch eine Phosphorglasschicht aufwendiger als durch eine Siliziumdioxidschicht.a metal layer or a layer of polycrystalline silicon oxide In the further process, these two layers on the substrate become then structures are etched out. In doing so, the gate electrode layer is first made polycrystalline silicon provided with a structure, and the so structured layer made of polycrystalline silicon then serves as an etching mask for the etching of the underneath located gate orid layer. When chemically etching the gate oxide layer it comes at the ref areas of the polycrystalline silicon layer, which act as gate electrodes are intended to undercut. Those caused by such undercutting Overhangs of the gate electrodes made of polysilicon over the underlying gate insulators lead in the following process steps, in which to attach supply lines and conductor tracks the substrate, the gate insulating layers thereon and the gate electrodes are coated with a second insulating layer and then a metallization layer on the second insulating layer for producing the conductor bears is applied, to disturbances, because the applied layers on these overhangs Have dilution zones. When the conductor tracks are etched out, they occur Dilution zones often result in interruptions in the conductor tracks, resulting in a complete Failure of the component can lead. Improved procedures have been used to avoid these overhangs after the application of the second insulating layer and before the application the conductor track layer, a phosphor glass layer is deposited on the second insulating layer. The thinning zones of the second insulating layer become through this phosphor glass layer balanced. In this method, however, it is disadvantageous that the phosphor glass layer brought to flow by a difficult to control high temperature step must become. Furthermore, there is an increased risk of corrosion when using phosphor glass for the component, and finally the etching of contact holes through a Phosphorus glass layer more expensive than a silicon dioxide layer.
Aufgabe der Erfindung ist es, bei einem wie im Oberbegriff des Patentanspruches 1 angegebenen Verfahren Mittel anzugeben, durch die erreicht wird, daß beim Ätzen der Gate-Isolierschicht keine durch Unterätzungen hervorgerufenen Uberhänge des Gate-Isolators auftreten. Weiterhin soll das Verfahren möglichst dazu führen, daß die geätzten Strukturen, die aus der Gate-Elektrode aus Polysilizium und dem darunter befindlichen Gate-Isolator bestehen, einen einheitlichen Böschungswinkel aufweisen, so daß beim nachfolgenden Aufbringen weiterer Schichten die Flanken dieser- Strakturen aus Gate Elektrode und Gate-Isolator ohne Risse oder Lücken bedeckt werden.The object of the invention is, in one as in the preamble of claim 1 specified method to indicate means by which it is achieved that when etching the gate insulating layer has no overhangs caused by undercutting Gate insulator occur. Furthermore, the method should lead to the fact that the etched structures made up of the polysilicon gate electrode and the one below it existing gate insulator, have a uniform angle of repose, so that when further layers are subsequently applied, the flanks of these structures made of gate electrode and gate insulator without cracks or Gaps covered will.
Diese Aufgabe wird erfindungsgemäß nach der im kennzeichnenden Teil des Patentansprt1ches 1 angegebenen gleise gelöst.This object is according to the invention according to the characterizing part of the patent claim 1 specified tracks solved.
Weitere Ausgestaltungen des erfindungsgemäßen Verfahrens ergeben sich aus den Unteransprüchen.Further refinements of the method according to the invention result from the subclaims.
Der Vorteil des erfindungsgemäßen Verfahrens ergibt sich daraus, daß die Isolierschicht beim lonenätzen in einer zur Subatratoberfläche senkrechten Richtung abgetragen wird und daß daher an den Kanten der Gate-Elektroden keine Unterätzung auftreten kann. Auch in der Ausgestaltung des erfindungsgemäßen Verfahrens nach Unteranspruch 3, bei dem die Isolierschicht mit Ionen hoher kinetischer Energie bestrahlt wird und die bestrahlten Gebiete anschließend naßchemisch abgeätzt werden, tritt eine Unterätzung an den Rändern der Gate-Elektroden nicht auf. Dies ist daraus zu erklären, daß durch die energiereichen Ionen in der Isolierschicht Strahlen schäden hervorgerufen werden, und daß bei einer chemischen Ätzung diejenigen Gebiete der Isolierschicht, die mit Strahlenschäden versehen sind, wesentlich schneller abgetragen werden als die Gebiete ohne Strahlenschäden, die sich unter den als Strahlungsmaske wirkenden Gate-Elektroden aus polykristallinem Silizium befinden.The advantage of the method according to the invention results from the fact that the insulating layer during ion etching in a direction perpendicular to the substrate surface is removed and that therefore no undercut at the edges of the gate electrodes can occur. Also in the embodiment of the method according to the invention Dependent claim 3, in which the insulating layer with ions of high kinetic energy is irradiated and the irradiated areas are then etched wet chemically, undercutting does not occur at the edges of the gate electrodes. This is from it to explain that the high-energy ions in the insulating layer damage rays are caused, and that with a chemical etching those areas of Insulating layers that have been damaged by radiation are removed much faster are called the areas without radiation damage that are underneath as the radiation mask Acting gate electrodes made of polycrystalline silicon are located.
Im folgenden wird beschrieben und anhand der Figuren erläutert, wie das erfindungsgemäße Verfahren durchgeführt wird.In the following it is described and explained with reference to the figures how the method according to the invention is carried out.
Fig.1 zeigen schematisch, wie auf einem Halbleitersubstrat eine bis 6 Feldeffektstruktur und dazugehörige Leiterbahn-Anschlüsse aufgebracht werden, Fig.7 zeigen ein alternatives Verfahren.Fig.1 show schematically how on a semiconductor substrate one to 6 field effect structure and associated conductor track connections are applied, 7 show an alternative method.
bis 9 Auf ein Halbleitersubstrat 1 aus Silizium wird eine Siliziumdioxidschicht 2 abgeschieden und darauf eine Schicht aus polykristallinem Silizium 3. Auf diese Schicht aus polykristallinem Silizium 3 wird eine Maskieroxidschicht 4 aus Siliziumdioxid abgeschieden, und aus dieser Maskieroxidschicht 4 mittels eines fotolithografi- schen Verfahrens unter Verwendung einer Fotolackmaske 5 die Strunk turen 14 aus der Maskieroxidschicht herausgeätzt. Die Strukturen 14 dienen dann als Ätzrnaske für eine nachfolgende naßchemische Ätzung, bei der aus der Schicht aus polykristallinem Silizium die Gate-Elektroden 13 herausgeätzt werden (Fig.3). Sodann wird die Oxidase 14 und die Gate-Isolierschicht 2 einem Beschuß von Ionen 6 ausgesetzt. Dies kann entweder in einer Ionen-tsanlage geschehen, so daß durch lonenätzung die Ätzmaske 14 und die nicht von den Gate-Elektroden 13 bedeckten Teile der Gate-Oxidschicht 2 abgetragen werden. Beim lonenätzen beträgt die kinetische Energie der Ionen zwischen 200 und 1200 eV. Zum Abätzen einer Oxidschicht von 0,06-0,12/wm Dicke wird eine Dosis um 1Onen/cm2 benötigt.to 9 A silicon dioxide layer is placed on a semiconductor substrate 1 made of silicon 2 deposited and then a layer of polycrystalline silicon 3. On top of this Layer made of polycrystalline silicon 3 is a masking oxide layer 4 made of silicon dioxide deposited, and from this masking oxide layer 4 by means of a photolithographic ting Method using a photoresist mask 5, the Strunk structures 14 from the masking oxide layer etched out. The structures 14 then serve as an etching mask for a subsequent one Wet chemical etching in which the gate electrodes are formed from the layer of polycrystalline silicon 13 are etched out (Fig.3). Then the oxidase 14 and the gate insulating layer 2 exposed to a bombardment of ions 6. This can either be done in an ion tsanlage happen so that by ion etching the etching mask 14 and not from the gate electrodes 13 covered parts of the gate oxide layer 2 are removed. When ion etching is the kinetic energy of the ions between 200 and 1200 eV. For etching off an oxide layer from 0.06-0.12 / wm thickness a dose of 10nen / cm2 is required.
Zum lonenätzen werden bevorzugt Edelgasionen, insbesondere Argonionen, verwendet. Alternativ dazu kann auch ein Beschuß mit Ionen hoher kinetischer Energie (71 keV) durchgeführt werden, wobei die Maskieroxidschichten 14 und die von der Gate-Elektrode 13 freien Teile der Gate-Oxidachicht 2 mit Strahlenschäden versehen und sodann naßchemisch abgeätzt werden. Die kinetische Energie der Ionen beträgt hier beispielsweise 200 bis 400 keV, und es wird die zu entfernende Oxidschicht mit einer Dosis von 1011 - 1013 Ionen/cm2 bestrahlt. Für die naßchemische ätzungwird eine Lösung aus 152 gr NH4F, 50 ml HF-Säure und 228 ml H20 verwendet. Nach diesen Prozeßschritten erhält man eine Struktur, wie sie in der Fig.5 schematisch dargestellt ist. Sodann wird auf die Gate-Elektrode 13 und den darunter befindlichen Gate-Isolator 12 eine Isolierschicht 7 aufgebracht, in die dann Kontaktlöcher 8 geätzt werden. Auf die Isolierschicht 7 wird dann eine Schicht aus leitfähigem Material, z.B. Metall oder polykristallinem Silizium, aufgebracht und durch das Kontaktloch 8 eine elektrische Zuleitung zu der Gate-Elektrode 13 geschaffen.For ion etching, noble gas ions, in particular argon ions, are preferred used. Alternatively, bombardment with ions of high kinetic energy can also be used (71 keV), the masking oxide layers 14 and those of the Gate electrode 13 provided parts of the gate oxide layer 2 free of radiation damage and then etched off using a wet chemical process. The kinetic energy of the ions is here, for example, 200 to 400 keV, and it becomes the oxide layer to be removed irradiated with a dose of 1011-1013 ions / cm2. For wet chemical etching a solution of 152 g NH4F, 50 ml HF acid and 228 ml H20 was used. After these In the process steps, a structure is obtained as shown schematically in FIG is. Then the gate electrode 13 and the underlying gate insulator 12, an insulating layer 7 is applied, into which contact holes 8 are then etched. A layer of conductive material, for example metal, is then placed on top of the insulating layer 7 or polycrystalline silicon, applied and through the contact hole 8 an electrical Lead to the gate electrode 13 created.
Alternativ zu dem naßchemischen Herausätzen der Gate-Elektrode 13, bei der eine Maskierschicht 14 verwendet wird (vgl. Fig.1-4), kann die Gate-Elektrode 13 zusammen mit dem darunter befindlichen Gate-Isolator 12 auch in der im folgenden beschriebenen Weise hergestellt werden. Dazu wird auf das Substrat 1 zunächst die Gate-Isolierschicht 2 aufgetragen und darauf die Schicht aus polykristallinem Silizium 3. Sodann wird eine Fotolackmaske 5 auf die Schicht aus polykristallinem Silizium 3 aufgetragen. Mit Ionen 6 wird dann in einem Ionenstrahl-Atzverfahren der von der FotolaclmasLe 5 nicht bedeckte Teil der Schicht aus polykristalli nem Silizium 3 und der Gate-Isolierschicht 2 abgetragen, so daß der Gate-Isolator 12 und die Gate-Elektroden 13 übrigbleiben.As an alternative to the wet chemical etching out of the gate electrode 13, in which a masking layer 14 is used (see. Fig. 1-4), the gate electrode 13 together with the underlying gate insulator 12 also in the following described manner. For this purpose, the substrate 1 is first the Gate insulating layer 2 is applied and the layer of polycrystalline silicon 3 is then applied a photoresist mask 5 is applied to the layer of polycrystalline silicon 3. Ions 6 are then used in an ion beam etching process to create the photolaclmasLe 5 uncovered part of the layer made of polycrystalline silicon 3 and the gate insulating layer 2 removed so that the gate insulator 12 and the gate electrodes 13 remain.
Auf diese Strtitur aus Halbleitersubstrat 1, Gate-Isolator 12 und Gate-Elelctroden 13 wird sodann, wie bereits beschrieben, eine weitere Isolierchicht 7 aufgetragen, mit einem Kontaktloch 8 versehen und sodann eine Leiterbahn 9 abgeschieden.On this Strtitur from semiconductor substrate 1, gate insulator 12 and Gate electrodes 13 are then, as already described, a further insulating layer 7 applied, provided with a contact hole 8 and then a conductor track 9 deposited.
3 Patentansprüche 9 Figuren3 claims 9 figures
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19762620783 DE2620783A1 (en) | 1976-05-11 | 1976-05-11 | Insulated gate field effect transistor prodn. - using ion etching in structurising stage preventing under-etching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19762620783 DE2620783A1 (en) | 1976-05-11 | 1976-05-11 | Insulated gate field effect transistor prodn. - using ion etching in structurising stage preventing under-etching |
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| Publication Number | Publication Date |
|---|---|
| DE2620783A1 true DE2620783A1 (en) | 1977-11-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19762620783 Pending DE2620783A1 (en) | 1976-05-11 | 1976-05-11 | Insulated gate field effect transistor prodn. - using ion etching in structurising stage preventing under-etching |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2937993A1 (en) * | 1979-09-20 | 1981-04-02 | Siemens AG, 1000 Berlin und 8000 München | Silicon gate forming system for MOS transistor - uses laser beam to melt insulating layer over gate to prevent breakdown |
-
1976
- 1976-05-11 DE DE19762620783 patent/DE2620783A1/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2937993A1 (en) * | 1979-09-20 | 1981-04-02 | Siemens AG, 1000 Berlin und 8000 München | Silicon gate forming system for MOS transistor - uses laser beam to melt insulating layer over gate to prevent breakdown |
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