DE2937993A1 - Silicon gate forming system for MOS transistor - uses laser beam to melt insulating layer over gate to prevent breakdown - Google Patents
Silicon gate forming system for MOS transistor - uses laser beam to melt insulating layer over gate to prevent breakdownInfo
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- DE2937993A1 DE2937993A1 DE19792937993 DE2937993A DE2937993A1 DE 2937993 A1 DE2937993 A1 DE 2937993A1 DE 19792937993 DE19792937993 DE 19792937993 DE 2937993 A DE2937993 A DE 2937993A DE 2937993 A1 DE2937993 A1 DE 2937993A1
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- layer
- irradiation
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- radiation
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 13
- 239000010703 silicon Substances 0.000 title claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 12
- 230000015556 catabolic process Effects 0.000 title abstract 2
- 238000000034 method Methods 0.000 claims abstract description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 230000005855 radiation Effects 0.000 claims abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 5
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 3
- 239000001257 hydrogen Substances 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 33
- 239000004020 conductor Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 2
- 238000005496 tempering Methods 0.000 claims description 2
- 238000010521 absorption reaction Methods 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- -1 silicon diol Chemical class 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 3
- 238000002844 melting Methods 0.000 abstract description 3
- 230000008018 melting Effects 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 abstract 2
- 230000010349 pulsation Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000005670 electromagnetic radiation Effects 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/2636—Bombardment with radiation with high-energy radiation for heating, e.g. electron beam heating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Verfahren zum Herstellen von integrierten MOS-Halbleiter-Process for manufacturing integrated MOS semiconductor
schaltungen nach der Silizium-Gate-Technologie.circuits based on silicon gate technology.
Die Patentanmeldung betrifft ein Verfahren zum Herstellen von integrierten MOS-Halbleiterschaltungen nach der Silizium-Gate-Technologie, bei dem vor dem Aufbringen der Leiterbahnen auf dem Isolationsoxid die beim Herstellungsprozeß durch Strukturkanten und -Spalte entstandenen Oberflächen-Unebenheiten ausgeglichen werden.The patent application relates to a method for producing integrated MOS semiconductor circuits based on silicon gate technology, in which prior to application the conductor tracks on the insulation oxide during the manufacturing process through structure edges and gaps in surface unevenness are compensated.
Bei der Herstellung von Halbleiterbauelementen und integrierten Schaltungen treten häufig Strukturen auf, die sich über die allgemeine Oberfläche erheben und die an den herausragenden Teilen scharfe Kanten zeigen und/oder z. B. entlang der Pußpunktlinien zur allgemeinen Oberfläche kleine Spalte zwischen herausragendem Teil und der allgemeinen Oberfläche aufweisen. Solche Kanten und Spalte sind prozeßbedingt und können meist nicht vermieden werden. Sollen verschiedene Strukturteile, z. B. in integrierten Halbleiterschaltungen in MOS-Technik durch elektrische Leiterbahnen miteinander verbunden werden, dann müssen diese Bahnen über diese Kanten und Spalten hinweggeführt werden. Die Leiterbahnen werden über eine Maskentechnik durch strukturiertes Aufbringen von z. B.In the manufacture of semiconductor components and integrated circuits there are often structures that rise above the general surface and which show sharp edges on the protruding parts and / or z. B. along the Point lines to the general surface small gaps between protruding Part and the general surface. Such edges and gaps are process-related and can usually not be avoided. Should different structural parts, e.g. B. in integrated semiconductor circuits in MOS technology through electrical conductor tracks be connected to each other, then these orbits have to go through this Edges and gaps are led away. The conductor tracks are made using a mask technique by structured application of z. B.
Metallen oder Metallsiliziden hergestellt. Dabei tritt das Problem auf, daß diese derartig hergestellten Leiterbahnen an den Kanten und/oder Spalten unterbrochen sind, oder im weiteren Zeitverlauf durch chemische, mechanische, thermische oder elektrische Belastungen unterbrochen werden. Je höher der Integrationsgrad einer MOS-Schaltung ist, desto höher ist die Ausfallrate durch solche Defekte.Metals or metal silicides. This is where the problem arises on that these conductor tracks produced in this way at the edges and / or gaps are interrupted, or in the further course of time by chemical, mechanical, thermal or electrical loads are interrupted. The higher the degree of integration of a MOS circuit, the higher the failure rate due to such defects.
Die Ausbeute an funktionsfähigen Schaltungen oder auch deren Betriebssicherheit wird zu einem großen Teil durch diese Leiterbahnunterbrechungen gemindert.The yield of functional circuits or their operational reliability is reduced to a large extent by these line breaks.
Aus der US-Patentschrift 3.825.442 ist ein Verfahren zur Herstellung integrierter MOS-Halbleiterschaltungen in Silizium-Gate-Technologie zu entnehmen, bei dem zur Vermeidung dieser Leiterbahnunterbrechungen vor dem Aufbringen der Metall-Leiterbahnebene eine Phosphorglasschicht (sogenanntes Flow-Glas) verwendet wird. Dieses Phosphorglas fließt bei einem nachfolgenden Temperprozeß über die Kanten und Spalte und entschärft dadurch die kritischen Kanten bzw. die Spalten werden mit diesem Material aufgefüllt und geschlossen. Der Nachteil dieses Verfahrens liegt darin, daß die Anordnung für längere Zeit (30 Minuten) auf 1000 bis 11000C erwärmt werden muß.From US Pat. No. 3,825,442 there is a method of manufacture integrated MOS semiconductor circuits in silicon gate technology, in the case of avoiding these conductor track interruptions before applying the metal conductor track level a phosphor glass layer (so-called flow glass) is used. This phosphor glass flows in a subsequent tempering process over the edges and gaps and defused as a result, the critical edges or the gaps are filled with this material and closed. The disadvantage of this method is that the arrangement for must be heated to 1000 to 11000C for a long time (30 minutes).
Während dieser Zeitdauer können sich z. B. Dotierstoffelemente im Innern der Anordnung durch Diffusion umverteilen, so daß sich bestimmte, zuvor eingestellte Konzentrationsverteilungen oder Profile von implantierten Bereichen ändern. Dieser Effekt ist unerwünscht, da sich dadurch die Eigenschaften des Bauelementes ändern können.During this period, z. B. dopant elements in Redistribute inside the arrangement by diffusion, so that certain, previously set Change concentration distributions or profiles of implanted areas. This Effect is undesirable because it changes the properties of the component can.
Neben dieser Hochtemperaturbehandlung stellt das Flow-Glas-Verfahren aber auch einen zusätzlichen Prozeß schritt dar, das heißt, die Ausbeute sinkt und die Kosten pro Chip steigen.In addition to this high-temperature treatment, there is the flow-glass process but also an additional process step, that is, the yield decreases and the cost per chip increases.
Die Aufgabe, die der vorliegenden Erfindung zugrundeliegt, besteht darin, das Problem der Leiterbahnunterbrechung auf einfache Weise zu lösen, das heißt, ein Verfahren anzugeben, mit dessen Hilfe Unebenheiten der Oberfläche vor dem Aufbringen der Leiterbahnen ausgeglichen werden, ohne daß dabei die bereits hergestellten Bauelementstrukturen in der Anordnung durch hohe Temperaturen beeinträchtigt werden.The object on which the present invention is based exists in solving the problem of the trace interruption in a simple way, the means to specify a method with the help of which unevenness of the surface is found the application of the conductor tracks are compensated without the already produced component structures in the arrangement impaired by high temperatures will.
Diese Aufgabe wird durch ein Verfahren der eingangs genannten Art dadurch gelöst, daß die Oberfläche einer hochenergetischen Bestrahlung ausgesetzt wird, wobei die Energie bzw. die Wellenlänge dieser Strahlung so eingestellt wird, daß nur die oberflächennahe Schicht beeinflußt wird.This task is carried out by a method of the type mentioned at the beginning solved by exposing the surface to high-energy radiation where the energy or the wavelength of this radiation is set so that that only the layer near the surface is affected.
Vorteilhafte Weiterbildungen der Erfindung und bevorzugte Ausführungsbeispiele ergeben sich aus den Cr t7rS#r##sprUchen.Advantageous developments of the invention and preferred exemplary embodiments result from the Cr t7rS # r ## sayings.
Der Erfindung gemäß wird die zu behandelnde mit Kanten und/oder Spalten behaftete Oberflächenschicht bevorzugt mit elektromagnetischer Strahlung solcher Wellenlänge beaufschlagt, daß nur die zu behandelnde Schicht absorbiert, nicht Jedoch darunter liegende bzw. daneben liegende Schichten anderer Materialien. Für Beaufschlagung mit Materiewellen, das heißt Elektronen oder Ionen, muß deren Energie so gewählt werden, daß deren Eindringtiefe die Dicke der zu bearbeitenden Schicht nicht überschreitet. Dadurch wird in erster Linie vermieden, daß andere Schichten oder Schichtteile als die zu bearbeitende wesentliche und unerwünschte Veränderungen erleiden. Wird als Quelle der elektromagnetischen Strahlung z. B. ein kontinuierlich emittierender Laser verwendet, so kann die Bearbeitungszeit einer Flächeneinheit unter eine Sekunde heruntergedrückt werden, so daß nur die zu bearbeitende Schicht in die Schmelzphase gerät, während andere Schichten genügend kühl bleiben.According to the invention, the one to be treated is provided with edges and / or crevices afflicted surface layer preferably with electromagnetic radiation such Wavelength applied so that only the layer to be treated absorbs, but not underlying or adjacent layers of other materials. For charging with matter waves, that is to say electrons or ions, their energy must be chosen in this way that their depth of penetration does not exceed the thickness of the layer to be processed. This primarily avoids layers or parts of layers other than that are subject to significant and undesirable changes to be processed. Used as Source of electromagnetic radiation e.g. B. a continuously emitting When using lasers, the processing time of a unit area can be under a second be pressed down, so that only the layer to be processed in the melting phase device while other layers stay cool enough.
Weitere Einzelheiten sind den Figuren 1 und 2, welche anhand von zwei Ausführungsbeispielen beschrieben werden, zu entnehmen. Dabei zeigt die Figur 1 eine Anordnung vor der Durchführung des erfindungsgemäßen Verfahrens und Figur 2 die gleiche Anordnung nach dem Verrunden der Kanten bzw. dem Beseitigen von Spalten. Als Deckschicht wird dabei eine aus phosphorhaltigem Siliziumdioxid bestehende Schicht verwendet, welche besonders gut für das Verfahren nach der Lehre der Erfindung geeignet ist. Das Verfahren ist aber auch anwendbar für andersartige Deckschichten.Further details are FIGS. 1 and 2, which are based on two Embodiments are described, refer to. FIG. 1 shows an arrangement prior to the implementation of the method according to the invention and FIG. 2 the same arrangement after rounding the edges or removing gaps. A layer consisting of phosphorus-containing silicon dioxide is used as the cover layer used, which are particularly well suited for the method according to the teaching of the invention is. However, the method can also be used for different types of cover layers.
Figur 1: Auf einem Siliziumsubstrat 1 ist eine, z. B.Figure 1: On a silicon substrate 1 is a, z. B.
50 nm dicke thermische Oxidschicht 2 aufgewachsen. Auf diese Oxidschicht 2 ist als Struktur, z. B. als Gateelektrode eines MOS-Transistors, eine polykristalline, seitlich definierte Siliziumschicht 3 der Dicke 500 nm aufgebracht. Zum Schutz und zur elektrischen Isolierung wird diese Anordnung (1, 2, 3) mit einer z. B. 400 nm dicken phosphorhaltigen SiO2-Schicht 4 versehen. An den mit dem Bezugszeichen 5 und 6 gekennzeichneten Stellen kann die Schicht 4 Spalte aufweisen. Soll nun über die Schicht 4, insbesondere an den Stellen 5 und 6 eine Leiterbahn 7 geführt werden, so besteht die Gefahr, daß diese Leiterbahn an diesen Stellen 5 und 6 unterbrochen wird und damit ihre Funktion nicht mehr erfüllen kann.50 nm thick thermal oxide layer 2 grown. On this oxide layer 2 is as a structure, e.g. B. as the gate electrode of a MOS transistor, a polycrystalline, laterally defined silicon layer 3 with a thickness of 500 nm is applied. For protection and for electrical insulation this arrangement (1, 2, 3) with a z. B. 400 nm thick phosphorus-containing SiO2 layer 4 provided. At the with the reference number 5 and 6 marked locations, the layer can have 4 gaps. Should now over the layer 4, in particular a conductor track 7 at points 5 and 6, so there is a risk that this conductor path will be interrupted at these points 5 and 6 and thus can no longer fulfill its function.
Die Spalte 5 und 6 können nämlich normalerweise durch das die Leiterbahn 7 bildende Material nicht aufgefüllt werden.The column 5 and 6 can namely normally through the conductor track 7 constituent material cannot be replenished.
Wird nun z. B., wie in Figur 2 dargestellt, diese Struktur mit dem gebündelten Licht (Wellenlänge 10 /um) eines starken C02-Lasers 8 (200 Watt) mit einer Geschwindigkeit von z. B. 12 mm/Sekunde abgerastert, so beginnt die die phosphordotierte SiO2-Schicht 4 unter dem Einfluß des absorbierten Lichtes zu schmelzen, und zwar bei Temperaturen weit unterhalb der Schmelztemperatur der Schichten (1, 2 und 3). Da das Licht 8 des C02-Lasers unterhalb einer kritischen Energiedichte von Silizium sowieso nicht absorbiert wird, werden die aus Silizium bestehenden Teile der Struktur praktisch nicht beeinflußt, das heißt, Dotierungsprofile bleiben erhalten. Die Geschwindigkeit des Abrasterns darf nicht zu groß sein, damit für die Schicht 4 an den Stellen 5 und 6 genügend Zeit bleibt, die Spalte 5 und 6 aufzufüllen.If now z. B., as shown in Figure 2, this structure with the bundled light (wavelength 10 / um) of a strong C02 laser 8 (200 watt) with a speed of e.g. B. scanned 12 mm / second, the begins the to melt phosphorus-doped SiO2 layer 4 under the influence of the absorbed light, at temperatures far below the melting temperature of the layers (1, 2 and 3). Because the light 8 of the CO2 laser is below a critical energy density is not absorbed by silicon anyway, those made of silicon are Parts of the structure are practically not influenced, that is, doping profiles remain obtain. The speed of scanning must not be too great for layer 4 at positions 5 and 6 has enough time to fill gaps 5 and 6.
Da der überhang der Schicht 4 an den Stellen 5 und 6 über die polykristalline Struktur 3 das C02-Laserlicht 8 von den Stellen 5 und 6 ausblendet, kann in einem Ausführungsbeispiel nach der Lehre der Erfindung die Anordnung (1, 2, 3, 4) so gegen den Laserstrahl verkippt werden, daß dieser auch die Fußpunkte der Spalte 5 und 6 erreichen kann. Wie aus der Figur 2 zu entnehmen ist, bildet die Schicht 4 nun eine zusammenhängende Deckschicht, bei der alle Kanten verrundet und die Spalte geschlossen sind.Since the overhang of layer 4 at points 5 and 6 over the polycrystalline Structure 3 fades out the C02 laser light 8 from points 5 and 6, can in one Embodiment according to the teaching of the invention, the arrangement (1, 2, 3, 4) so against the laser beam are tilted so that this also the base points of column 5 and 6 can achieve. As can be seen from FIG. 2, the layer 4 now forms a coherent top layer with all edges rounded and the gaps are closed.
Über diese Schicht 4 kann nun anschließend die Leiterbahn 7 gelegt werden, ohne daß befürchtet werden muß, daß diese Leiterbahn 7 Unterbrechungen aufweist.The conductor track 7 can then be placed over this layer 4 without having to fear that this conductor track has 7 interruptions.
Anstelle des Laserlichts 8 können auch Korpuskularstrahlen eingesetzt werden. Diese haben den Vorzug, nicht selektiv absorbiert zu werden. Dadurch können hohe Temperaturgradienten an den Grenzflächen zwischen 4 und 3 vermieden werden. Das Verfließen der Schicht 4 an den Stellen 5 und 6 wird durch den Zieheffekt des abrasternden Strahlenbündels 8 noch begünstigt.Instead of the laser light 8, corpuscular beams can also be used will. These have the advantage of not being selectively absorbed. This allows high temperature gradients at the interfaces between 4 and 3 can be avoided. The flow of layer 4 at points 5 and 6 is caused by the pulling effect of the scanning beam 8 is still favored.
Entstehen durch das erfindungsgemäße Verfahren Grenzflächenzustände, so kennen diese in einem weiteren Niedertemperaturprozeß bei 400 bis 5000C ir, einer Wasserstoff enthaltenden Atmosphäre beseitigt werden.If the method according to the invention creates interface states, so know this in another low-temperature process at 400 to 5000C ir, one hydrogen containing atmosphere can be eliminated.
Die Schicht 4 kann an den Stellen 5 und 6 auch gleichzeitig mit mehreren zueinander geneigten Strahlenbündeln zur Prozeßbeschleunigung beim Auffüllen von Spalten bestrahlt werden. Die Anordnung kann auch mit kurzen oder ultrakurzen (10 8 Sekunden) Pulsen, Wellen oder Korpuskularstrahlen beaufschlagt werden.The layer 4 can also have several at the same time at the points 5 and 6 mutually inclined bundles of rays to accelerate the process when filling Columns are irradiated. The arrangement can also be short or ultra-short (10 8 seconds) pulses, waves or corpuscular rays are applied.
Die zur Durchführung des Verfahrens zu verwendenten Vorrichtungen sind bekannt. Insbesondere können solche Vorrichtungen verwendet werden, wie sie beispielsweise bei Laser- oder Elektronenstrahl-Ausheilverfahren verwendet werden. Typisch für diese Verfahren sind die kurzen Zeitintervalle der Energiezufuhr. Diese Intervalle liegen zwischen 10 8 Sekunden und 10 6 Sekunden pro Flächeneinheit, unabhängig davon, ob im Impulsbetrieb oder im Dauerstrichbetrieb gearbeitet wird.The devices to be used to carry out the method are known. In particular, such devices can be used as they can be used, for example, in laser or electron beam annealing processes. The short time intervals between the energy supply are typical of these processes. These Intervals are between 10 8 seconds and 10 6 seconds per unit area, regardless whether you are working in pulse mode or in continuous wave mode.
14 Patentansprüche 2 Figuren Leerseite14 claims 2 figures Blank page
Claims (14)
Priority Applications (1)
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DE19792937993 DE2937993A1 (en) | 1979-09-20 | 1979-09-20 | Silicon gate forming system for MOS transistor - uses laser beam to melt insulating layer over gate to prevent breakdown |
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DE19792937993 DE2937993A1 (en) | 1979-09-20 | 1979-09-20 | Silicon gate forming system for MOS transistor - uses laser beam to melt insulating layer over gate to prevent breakdown |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2481517A1 (en) * | 1980-04-28 | 1981-10-30 | Fairchild Camera Instr Co | METHOD OF CAUSING FLOW OF SILICON DIOXIDE MATERIALS USING A LASER |
EP0084985A2 (en) * | 1982-01-15 | 1983-08-03 | FAIRCHILD CAMERA & INSTRUMENT CORPORATION | Laser induced flow Ge-O based materials |
EP0109499A2 (en) * | 1982-11-18 | 1984-05-30 | Texas Instruments Incorporated | Laser processing of PSG, oxide and nitride via absorption optimized selective laser annealing |
EP0202572A2 (en) * | 1985-05-13 | 1986-11-26 | Nippon Telegraph And Telephone Corporation | Method for forming a planarized aluminium thin film |
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FR2193256A1 (en) * | 1972-07-17 | 1974-02-15 | Hughes Aircraft Co | |
US3825442A (en) * | 1970-01-22 | 1974-07-23 | Intel Corp | Method of a semiconductor device wherein film cracking is prevented by formation of a glass layer |
DE2307754A1 (en) * | 1973-02-16 | 1974-08-22 | Hitachi Ltd | Multilayer electrical conductors mfr. - by forming contacts by partial etching of coated substrate |
GB1422033A (en) * | 1972-10-12 | 1976-01-21 | Ncr Co | Method of manufacturing a semiconductor device |
US3950187A (en) * | 1974-11-15 | 1976-04-13 | Simulation Physics, Inc. | Method and apparatus involving pulsed electron beam processing of semiconductor devices |
US4022930A (en) * | 1975-05-30 | 1977-05-10 | Bell Telephone Laboratories, Incorporated | Multilevel metallization for integrated circuits |
DE2620783A1 (en) * | 1976-05-11 | 1977-11-24 | Siemens Ag | Insulated gate field effect transistor prodn. - using ion etching in structurising stage preventing under-etching |
US4151008A (en) * | 1974-11-15 | 1979-04-24 | Spire Corporation | Method involving pulsed light processing of semiconductor devices |
DE2825212B1 (en) * | 1978-06-08 | 1979-07-12 | Siemens Ag | Process for the production of semiconductor components using a short, intense laser light pulse |
-
1979
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US3825442A (en) * | 1970-01-22 | 1974-07-23 | Intel Corp | Method of a semiconductor device wherein film cracking is prevented by formation of a glass layer |
FR2193256A1 (en) * | 1972-07-17 | 1974-02-15 | Hughes Aircraft Co | |
GB1422033A (en) * | 1972-10-12 | 1976-01-21 | Ncr Co | Method of manufacturing a semiconductor device |
DE2307754A1 (en) * | 1973-02-16 | 1974-08-22 | Hitachi Ltd | Multilayer electrical conductors mfr. - by forming contacts by partial etching of coated substrate |
US3950187A (en) * | 1974-11-15 | 1976-04-13 | Simulation Physics, Inc. | Method and apparatus involving pulsed electron beam processing of semiconductor devices |
US4151008A (en) * | 1974-11-15 | 1979-04-24 | Spire Corporation | Method involving pulsed light processing of semiconductor devices |
US4022930A (en) * | 1975-05-30 | 1977-05-10 | Bell Telephone Laboratories, Incorporated | Multilevel metallization for integrated circuits |
DE2620783A1 (en) * | 1976-05-11 | 1977-11-24 | Siemens Ag | Insulated gate field effect transistor prodn. - using ion etching in structurising stage preventing under-etching |
DE2825212B1 (en) * | 1978-06-08 | 1979-07-12 | Siemens Ag | Process for the production of semiconductor components using a short, intense laser light pulse |
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Title |
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US-Z: Solid State Technology, April 1979, S. 143-148 * |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2481517A1 (en) * | 1980-04-28 | 1981-10-30 | Fairchild Camera Instr Co | METHOD OF CAUSING FLOW OF SILICON DIOXIDE MATERIALS USING A LASER |
EP0084985A2 (en) * | 1982-01-15 | 1983-08-03 | FAIRCHILD CAMERA & INSTRUMENT CORPORATION | Laser induced flow Ge-O based materials |
EP0084985A3 (en) * | 1982-01-15 | 1986-08-20 | FAIRCHILD CAMERA & INSTRUMENT CORPORATION | Laser induced flow ge-o based materials |
EP0109499A2 (en) * | 1982-11-18 | 1984-05-30 | Texas Instruments Incorporated | Laser processing of PSG, oxide and nitride via absorption optimized selective laser annealing |
EP0109499A3 (en) * | 1982-11-18 | 1985-07-31 | Texas Instruments Incorporated | Laser processing of psg, oxide and nitride via absorption optimized selective laser annealing |
EP0202572A2 (en) * | 1985-05-13 | 1986-11-26 | Nippon Telegraph And Telephone Corporation | Method for forming a planarized aluminium thin film |
EP0202572A3 (en) * | 1985-05-13 | 1989-09-27 | Nippon Telegraph And Telephone Corporation | Method for forming a planarized thin film |
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