DE2723933A1 - Etching metal, esp. polycrystalline silicon or aluminium - with definite angle of slope by ion bombardment before plasma etching - Google Patents

Etching metal, esp. polycrystalline silicon or aluminium - with definite angle of slope by ion bombardment before plasma etching

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Publication number
DE2723933A1
DE2723933A1 DE19772723933 DE2723933A DE2723933A1 DE 2723933 A1 DE2723933 A1 DE 2723933A1 DE 19772723933 DE19772723933 DE 19772723933 DE 2723933 A DE2723933 A DE 2723933A DE 2723933 A1 DE2723933 A1 DE 2723933A1
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Prior art keywords
etching
layer
etched
ion bombardment
esp
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DE19772723933
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German (de)
Inventor
Guido Dipl Chem Dr Bell
Joachim Ing Grad Hoepfner
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Siemens AG
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Siemens AG
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Priority claimed from DE19752554638 external-priority patent/DE2554638A1/en
Application filed by Siemens AG filed Critical Siemens AG
Publication of DE2723933A1 publication Critical patent/DE2723933A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
    • H01L21/32132—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

Prodn. of a definite angle of slope in etching a substrate is achieved by preceding ion bombardment with an ion energy of 200-1000 eV and a dosage of 1015 to 1017 particles/cm.2 as structural defects favouring etching, as in DT 2554638. The novel feature is that the process is applied to a metal layer, pref. of polysilicon or Al. The process is used in the prodn. of integrated circuits and extends the applicability of the parent patent. A plasma etching process is employed. The process is used for the prodn. of a conducting path, on which there is an insulating layer with another insulting path, esp. for etching a layer on a semiconductor substrate already having a semiconductor element.

Description

Verfahren zur Erzeugung definierter Böschungswinkel bei einerMethod for generating defined angles of repose for a

Ätzkante.Etched edge.

Die Erfindung bezieht sich auf eine Weiterbildung des im Oberbegriff des Patentanspruches 1 der vorliegenden Anmeldung angegebenen Verfahrens des Hauptpatentes.The invention relates to a development of the preamble of claim 1 of the present application specified method of the main patent.

Die technischen Vorteile des Verfahrens des Hauptpatentes zur Erzeugung definierter Böschungswinkel bei einer Ätzkante in Siliziumdioxid lassen sich auch bei Ätzkanten in Polysilizium oder Aluminium erreichen, die bevorzugte Materialien für Leiterbahnen in integrierten Schaltungen sind. Abgeböschte Kanten an Leiterbahnen sind insbesondere dort von Interesse, wo diese Leiterbahnen von einer gegebenenfalls weiteren isolierenden Schicht bedeckt sind, auf der sich dann andere Leiterbahnen befinden. Bei zu scharfen Kanten der erstgenannten unten liegenden Leiterbahnen besteht nämlich die Gefahr daß die darauf befindliche isolierende Schicht an den Leiterbahnkanten zumindest zu dünn ist und Kurzschlüsse an sich gegeneinander isolierter Leiterbahnen auftreten.The technical advantages of the method of the main patent for production Defined angle of repose for an etched edge in silicon dioxide can also be used achieve the preferred materials for etched edges in polysilicon or aluminum for conductor tracks in integrated circuits. Sloped edges on conductor tracks are of particular interest where these conductor tracks may be of a Another insulating layer are covered, on which then other conductor tracks are located. If the edges of the first-mentioned conductor tracks are too sharp namely, there is a risk that the insulating layer located on it to the The conductor track edges are at least too thin and short circuits are more isolated from one another Conductor tracks occur.

Die vorliegende Erfindung erstreckt sich auch auf das Anwenden des sogenannten Plasma-Ätzens der Leiterbahnmaterialien, wie Polysilizium oder Aluminium, sowie der bereits in dem Hauptpatent angegebenen Isolatormaterialien, wie Siliziumdioxid oder Siliziumnitrid.The present invention also extends to the application of the so-called plasma etching of the conductor track materials, such as polysilicon or aluminum, and the insulator materials already specified in the main patent, such as silicon dioxide or silicon nitride.

Es ist somit eine Aufgabe der vorliegenden Erfindung, eine Erweiterung des Anwendungsbereiches der Erfindung nach dem Hauptpatent anzugeben. Die Lösung dieser Aufgabe ist durch die Merkmale des Patentanspruches 1 umrissen. Weitere Ausgestaltungen und Weiterbildungen dieser erfindungsgemäßen Lösung sind aus den Unteransprüchen zu entnehmen.It is thus an object of the present invention to provide an extension indicate the scope of the invention according to the main patent. The solution this task is outlined by the features of claim 1. Further refinements and further developments of this solution according to the invention are derived from the subclaims refer to.

In dem nicht zum Stand der Technik zählenden Hauptpatent sind Einzelheiten zur Durchführung solcher Verfahrensmaßnahmen angegeben, die auch bei der vorliegenden Erfindung zur Anwendung kommen. Mit Rücksicht auf diese bereits vorliegende Beschreibung des flauptpatentes, die hiermit zum Bestandteil der vorliegenden Erfindungsbeschreibung gemacht ist, können Erläuterungen von bereits beschriebenen Einzelheiten zumindest kurzgefaßt entnormen werden.The main patent, which is not part of the prior art, provides details specified for the implementation of such procedural measures, which also apply to the present Invention come to use. With regard to this already available description of the flauptpatent, which is hereby part of the present description of the invention is made, explanations of the details already described can at least in a nutshell.

Ein Merkmal der vorliegenden Erfindung ist, mit einem Ionenbeschuß mit ungewöhnlich niedrigen Ionenenergien von nur 200 bis 1000 eV bei Ionenstrahlenergien bzw. -dosiswerten in der Größe von 1015 bis 1017 cm 2 eine sich in die Dicke der Schicht, in der die Ätzkante erzeugt werden soll, erstreckende Gefügestörung zu erzeugen, die bei nachfolgendem Ätzen das Entstehen eines relativ einheitlichen Böschungswinkels gewährleistet. Es ist wichtig, daß die Ionen des Ionenbeschusses eine solche geringe Energie haben. Zu einem gewissen Ausgleich trägt die relativ große Bemessung der Dosiswerte bei.A feature of the present invention is ion bombardment with unusually low ion energies of only 200 to 1000 eV for ion beam energies or dose values in the size of 1015 to 1017 cm 2 are in the thickness of the Layer in which the etched edge is to be produced, extending structural disturbance to produce which in the subsequent etching the emergence of a relatively uniform Approach angle guaranteed. It is important that the ions of ion bombardment have such low energy. To a certain degree, it helps relatively large dimensioning of the dose values.

Das gemäß einem weiteren Merkmal der Erfindung vorzunehmende, dem Ionenbeschuß nachfolgende Ätzen - zur Erzeugung der abgeböschten Ätzkante - kann auf verschiedene Weise erfolgen.The to be made according to a further feature of the invention, the Ion bombardment subsequent etching - to produce the sloped etching edge - can done in different ways.

Ein mit der Erfindung erprobtes Verfahren des naßchemischen Ätzens ist bereits im Hauptpatent für den speziellen Fall einer Isolatorschicht ausführlich beschrieben. Für das Ätzen von beispielsweise Siliziumdioxid auf beispielsweise Silizium werden die üblichen chemischen Ätzmittel verwendet, die das Sili- zium praktisch nicht angreifen und das Siliziumdioxid ätzen, wobei als Folge der vorausgegangenen erfindungsgemäßen Maßnahme des energieschwachen, aber dosisstarken Ionenbeschusses das abgeböschte Ätzen dann zwangsläufig auftritt.A method of wet chemical etching that has been tried and tested with the invention is already detailed in the main patent for the special case of an insulator layer described. For the etching of e.g. silicon dioxide on e.g. Silicon, the usual chemical etchants are used, which the silicon zium practically does not attack and etch the silicon dioxide, being as a result of the previous Measure according to the invention of low-energy, but high-dose ion bombardment the etching off then inevitably occurs.

Ein anderes Ätzverfahren ist das des sogenannten Plasma-Ätzens, das ein Ätzen aus der Gasphase ist. Bei diesem Plasma-Ätzen wird ein nicht gerichtetes, isotropes Plasma, z.B. in einem Quarzrohr, in einem elektrischen Feld erzeugt. Das Plasma wird z.B. in Freon erzeugt, das als Plasma Fluor abgibt. Dieses Fluor tritt als ionisiertes Fluor oder als angeregtes Fluor oder als Fluor-radikal auf. Dieses sozusagen in statu nascendi auftretende Fluor wird gegen die zu ätzende Fläche oder Schicht gerichtet, wo das Fluor dann die Ätzwirkung ausübt. Weitere Einzelheiten zum Plasme-Ätzen lassen sich bei James Daleshy, "A Study of the Etching Characteristic of Semiconductor Materials in RF-Plasma# NTIS Nr. AD/781831 (Juni 1974) entnehmen.Another etching process is what is known as plasma etching, the is a gas phase etch. With this plasma etching a non-directional, Isotropic plasma, e.g. in a quartz tube, is generated in an electric field. That Plasma is generated e.g. in freon, which emits fluorine as plasma. This fluorine occurs as ionized fluorine or as excited fluorine or as a fluorine radical. This So to speak in statu nascendi occurring fluorine is against the surface to be etched or Layer directed, where the fluorine then exerts the etching effect. more details For plasma etching, see James Daleshy, "A Study of the Etching Characteristic of Semiconductor Materials in RF-Plasma # NTIS No. AD / 781831 (June 1974).

Weitere im Zusammenhang mit der Erfindung anzuwendende Ätzverfahren sind das sogenannte Hochfrequenz-Sputterätzen und das Ionenätzen, wie sie schon im Hauptpatent beschrieben sind.Further etching processes to be used in connection with the invention are the so-called high-frequency sputter etching and ion etching, as they already do are described in the main patent.

Auch diese Ätzverfahren bringen den Vorteil mit sich, daß die geätzten Strukturen relativ einheitlichen Böschungswinkel aufweisen. Allerdings ist bei diesen letztgenannten Ätzverfahren zu beachten, daß sie relativ wenig selektiv sind und ein Ätzen darunterliegenden Materials, z.B. des Substratkörpers, nicht vollständig zu vermeiden ist.These etching processes also have the advantage that the etched Structures have relatively uniform slope angles. However, this is the case The latter etching process should be noted that they are relatively unselective and etching of underlying material, e.g. the substrate body, is not complete is to be avoided.

Die vorliegende Erfindung, d.h. mit'Ätzen auf naßchemischem Weg, mit Hilfe des Plasma-Ätzens, mit Hochfreauenz-Sputterätzen, mit lonenätzen und dergleichen, 12ist sich wie bereits oben erwähnt nicht nur bei dem bereits im Hauptpatent beschriebenen' Isolatormaterial, sondern auch bei Polysilizium, Aluminium und dergleichen anwenden, die für Leiterbahnen in integrierten Schaltungen Anwendung finden.The present invention, i.e. with etching by a wet chemical route, with The help of plasma etching, with high-frequency sputter etching, with ion etching and the like, As already mentioned above, not only is the ' Insulator material, but also apply to polysilicon, aluminum and the like, which are used for conductor tracks in integrated circuits.

Vorteilhaft ist es, eine Dosis von 1016.cm-2 für die erfindungs- gemäß vorgesehene "Störung" einer nachfolgend zu ätzenden Schicht vorzusehen, die z.B. eine Dicke von ungefähr 10 nm hat.It is advantageous to use a dose of 1016 cm-2 for the according to intended "disturbance" of a subsequent layer to be etched, e.g. has a thickness of approximately 10 nm.

Mit dieser Dosis vergleichbar ist ein Stromstärkewert von 0,3 bis 1 mA.cm#2 über eine Zeitdauer von einigen Sekunden-bis zu einer Minute.A current value of 0.3 to is comparable with this dose 1 mA.cm # 2 for a period of a few seconds to a minute.

Der Ionenbeschuß erfolgt vorteilhafterweise ganzflächig. Beim nachfolgenden Ätzen unter Verwendung einer wie üblich anzuwenden den Maske erfolgt ein gewisses Unterätzen des Maskenrandes, wobe: dieses Unterätzen im Bereich der der Maske zugewandten Oberfläch der zu ätzenden Schicht sich seitlich weiter erstreckt als in tiefer liegenden, insbesondere in substratnahe Bereichen dieser Schicht. Dies ergibt die bereits erwähnte abgeböschte Ätzkante.The ion bombardment is advantageously carried out over the entire area. At the next A certain amount of etching is carried out using a mask to be applied as usual Underetching the edge of the mask, where: this underetching in the area of the area facing the mask The surface of the layer to be etched extends laterally than in deeper lying, especially in areas of this layer close to the substrate. This gives the already mentioned sloped etched edge.

Weitere Erläuterungen der Erfindung gehen aus der Beschreibung zu den nachfolgenden Figuren hervor.Further explanations of the invention can be found in the description the following figures.

Fig.1 zeigt ein Teilstitok eines mit einer nachfolgend zu ätzender Schicht 8 bedeckten Halbleitersubstratkörpers 1 , der-gerade mit wie erfindungsgemäß vorgesehenem Ionenbeschuß 10 behandelt wird Zwischen dieser Schicht 8 und dem Substratkörper 1 befindet sich beispielsweise noch eine weitere Schicht 6 aus z.B. Isolatormaterial. Die Schicht 8 besteht beispielsweise aus Polysilizium oder Aluminium und dient dazu, in die Form von Leiterbahnen durch Ätzen umgearbeitet zu werden.FIG. 1 shows a partial stite of one to be etched subsequently with one Layer 8 covered semiconductor substrate body 1, which-just with as according to the invention provided ion bombardment 10 is treated between this layer 8 and the substrate body 1 there is, for example, a further layer 6 made of, for example, insulating material. The layer 8 consists for example of polysilicon or aluminum and serves to to be reworked in the form of conductor tracks by etching.

Fig.2 zeigt den Substratkörper 1 mit den Schichten 6 und 8 der Fig.1 und mit einer darauf befindlichen Maskierungsschicht (12), die Maskierungsöffnungen 14 hat. Die Darstellung der Fig.2 zeigt den Zustand nach erfolgtem naßchemischen Ätzen oder Plasma-Ätzen oder Hochfrequenz-Sputterätzen oder Ionenätzen. Mit 16 bis 20 sind die in der Darstellung der Fig.2 sichtbaren abgeböschten Ätzkanten bezeichnet, die in der Schicht 8 erzeugt worden sind, wobei das sich seitlich mehr oder weniger weit unter den Maskenrand der Maske 12 erstreckende Ätzen auf dem erfindungsgemäß zuvor erfolgten Ionenbeschuß und dem Jeweilig auftretenden Ätzverhalten beruht.FIG. 2 shows the substrate body 1 with the layers 6 and 8 of FIG and having a masking layer (12) thereon, the masking openings 14 has. The illustration in FIG. 2 shows the state after the wet chemical process has taken place Etching or plasma etching or high frequency sputter etching or ion etching. At 16 to 20 the sloped etching edges visible in the illustration of FIG. which have been generated in the layer 8, which is more or less laterally etching, which extends far below the mask edge of the mask 12, on the according to the invention previously carried out ion bombardment and the etching behavior that occurs in each case.

Die Fig.2 zeigt eine geschnittene Darstellung der durch das ätzen erzeugten Leiterbahnen 22, 24, 26, die sich beispielsweise parallel nebeneinanderliegend in Richtung der Senkrechten der Darstellungsebene auf der Isolatorschicht 6 des Substratkörpers 1 erstrecken.The Fig.2 shows a sectional view of the etching generated conductor tracks 22, 24, 26, which are, for example, parallel to each other in the direction of the perpendicular of the plane of representation on the insulator layer 6 of the Substrate body 1 extend.

Noch deutlicher sind die Leiterbahnen 22, 24, 26 aus der Darstellung der Fig.3 zu ersehen, wobei diese Leiterbahnen dort bereits mit einer weiteren Isolatorschicht 28 bedeckt sind. In der Darstellung der Fig.3 ist des weiteren eine Leiterbahn 30 zu sehen, die sich über die Schicht 28 in einer Richtung in der Darstellungsebene der Fig.3, d.h. quer über die Leiterbahnen 22, 24, 26 hinweg erstreckt. Die Darstellung der Fig.3 zeigt, daß diese Leiterbahn 30 über die abgeböschten Kanten der Leiterbahnen 22, 24, 26 ohne das Auftreten von scharfen Kanten verläuft. Scharfe seitliche Kanten der Leiterbahnen 22, 24, 26 könnten nicht nur zu einem Durchbrechen der Schicht 28 an der Stelle dieser Kanten führen, sondern könnten auch dünne Stellen oder gar Brüche in der Leiterbahn 30 auftreten lassen.The conductor tracks 22, 24, 26 are even clearer from the illustration 3 can be seen, these conductor tracks there already with a further insulator layer 28 are covered. In the illustration of FIG. 3, there is also a conductor track 30 seen moving across layer 28 in one direction in the plane of the drawing 3, i.e. across the conductor tracks 22, 24, 26. The representation 3 shows that this conductor track 30 over the sloped edges of the conductor tracks 22, 24, 26 runs without the appearance of sharp edges. Sharp side edges the conductor tracks 22, 24, 26 could not only break through the layer 28 lead at the point of these edges, but could also lead to thin areas or even Allow breaks in the conductor track 30 to occur.

Das erwähnte Plasma-Ätzen kann auch vorteilhaft zur Herstellung der erfindungsgemäß abgeböschten Ätzkanten bei einer Schicht aus isolierendem Material, wie es im Hauptpatent beschrieben ist, angewendet werden.The mentioned plasma etching can also be advantageous for the production of the according to the invention sloping etched edges in a layer of insulating material, as described in the main patent.

Das Arbeiten mit so geringen Ionenenergien von 200 bis 1000 eV ermöglicht es, daß sich im Substratkörper bereits fertiggestellte Halbleiterbauelemente oder Teile derselben befinden können, ohne daß diese Elemente oder Teile durch die Ionenbestrahlung Strahlenschäden erleiden.Working with ion energies as low as 200 to 1000 eV is made possible it that in the substrate body already completed semiconductor components or Parts of the same can be located without these elements or parts being affected by the ion irradiation Sustaining radiation damage.

Fig.4 zeigt einen Substratkörper 1, in dem sich Gebiete 2 und 4 befinden, die Source- und Draingebiet eines Feldeffekttransistors sein können. Auf der Oberfläche des Substratkörpers 1 befindet sich eine Gate-Elektrode 5. Die mit 8 bezeichnete Isolatorschicht aus z.B. Siliziumdioxid oder Siliziumnitrid ist bereits mit Kon- taktlöchern versehen, die abgeböschte Ätzkanten haben. Diese Kontaktlöcher sind nach dem Verfahren des Hauptpatentes unter Anwendung vorangehenden Ionenbeschusses durch Ätzen hergestellt worden. Die erwähnten Kontaktlöcher befinden sich über den Gebieten 2 und 4 sowie über der Gate-Elektrode 5. Mit 80 ist in Fig.4 eine Metallschicht aus beispielsweise Polysilizium oder Aluminium bezeichnet, die sich über die restlichen Anteile der Isolatorschicht 8 und in die Kontaktlöcher hinein erstreckt.4 shows a substrate body 1 in which areas 2 and 4 are located, the source and drain regions of a field effect transistor can be. On the surface of the substrate body 1 is a gate electrode 5 Insulator layer made of e.g. silicon dioxide or silicon nitride is already clock holes provided that have beveled etched edges. These contact holes are after the procedure of the main patent using the preceding ion bombardment by etching been. The aforementioned contact holes are located above areas 2 and 4 as well above the gate electrode 5. At 80 in Figure 4 is a metal layer of, for example Polysilicon or aluminum called, which extends over the remaining parts of the Insulator layer 8 and extends into the contact holes.

Diese aufgebrachte Metallschicht ist durchgehend einwandfrei, da die darunter befindlichen Anteile der Isolatorschicht 8 keine scharfen Kanten besitzen.This applied metal layer is flawless throughout, since the The portions of the insulator layer 8 located underneath do not have any sharp edges.

Durch nachfolgenden Ionenbeschuß, in der Figur mit 100 bezeichnet, werden der Schicht 80 dieJenigen Strahlenschdden zugefügt, die für das wie erfindungsgemäße abgeböschte Ritzen der Kanten erforderlich sind. Nach Durchführung einer Fotolithografie zur Erzeugung eines Strukturenmusters erfolgt dann ein Ätzen auf naßchemischem Wege oder mit Plasma-Ateen des Materials der Schicht 80. Auf diese Weise werden aus der Schicht 80 wie bereits erwähnte Leiterbahnen erzeugt, wie sie in Fig.2 des Hauptpatentes mit 20 bezeichnet sind. Diese Leiterbahnen dienen beispielsweise zum elektrischen Anschluß der einzelnen Gebiete 2 und 4 sowie der Gate-Elektrode 5.By subsequent ion bombardment, denoted by 100 in the figure, the layer 80 is inflicted with the radiation damage that is necessary for the as claimed in the invention sloped cracks on the edges are required. After performing a photolithography Etching is then carried out using a wet chemical method to produce a structure pattern or with plasma ateen of the material of layer 80. In this way, the Layer 80 is produced as already mentioned conductor tracks, as shown in Figure 2 of the main patent are denoted by 20. These conductor tracks are used, for example, for electrical purposes Connection of the individual areas 2 and 4 and the gate electrode 5.

6 Patentansprüche 4 Figuren L e e r s e i t e6 claims 4 figures L e r s e i t e

Claims (6)

Pa tentansprüche t Verfahren zur Erzeugung definierter Böschungswinkel bei einer tzkante an bzw. in einer auf einem Substratkörper befindlichen Schicht, wobei vor dem Ätzen ein Ionenbeschuß mit einer Ionenenergie zwischen 200 und 1000 eV und einer Dosis zwischen 1015 und 1017 Teilchen/cm2 als den nachfolgenden Ätzangriff beg~unstigende Gefüge störung der zu ätzenden Schicht als Vorbehandlung erfolgt, g e k e n n z e i c h n e t dadurch, daß die zu ätzende Schicht eine Metallschicht ist. Patent claims t method for generating defined angle of repose in the case of an etching edge on or in a layer located on a substrate body, before the etching, an ion bombardment with an ion energy between 200 and 1000 eV and a dose between 1015 and 1017 particles / cm2 as the subsequent etching attack favorable structural disturbance of the layer to be etched takes place as a pretreatment, it is not indicated in that the layer to be etched is a metal layer is. 2. Verfahren nach Anspruch 1, g e k e n n z e i c h n e t dadurch, daß die Metallschicht aus Polysilizium besteht. 2. The method according to claim 1, g e k e n n z e i c h n e t thereby, that the metal layer consists of polysilicon. 3. Verfahren nach Anspruch 1, g e k e n n z e i c h'n e t dadurch, daß die Ketallschicht aus Aluminium besteht. 3. The method according to claim 1, g e k e n n z e i c h'n e t thereby, that the ketallschicht consists of aluminum. 4. Verfahren nach Anspruch 1, 2 oder 3,g e k e n n z e i c h -n e t dadurch, daß für das nachfolgende Ätzen ein an sich bekanntes Plasma-Ätzverfahren angewendet wird. 4. The method of claim 1, 2 or 3, g e k e n n z e i c h -n e t in that a plasma etching process known per se is used for the subsequent etching is applied. 5. Anwendung eines Verfahrens nach einem der Anspruche 1 bis 4 zur Herstellung einer Leiterbahn, auf der sich eine Isolatorschicht und darauf eine weitere Leiterbahn befindet, die wenigstens zum Teil über eine abgeböschte Kante der geätzten Leiterbahn hinweg führt. 5. Application of a method according to one of claims 1 to 4 for Production of a conductor track on which there is an insulator layer and on top of it a further conductor track is located, at least partially over a sloped edge the etched conductor path leads away. 6. Anwendung eines Verfahrens nach einem der Ansprüche 1 bis 4 oder Anwendung nach Anspruch 5 bei einer zu ätzenden Schicht, die sich auf einem Halbleiter-Substratkörper befindet, in dem sich bereits ein Halbleiterbauelement befindet. 6. Application of a method according to any one of claims 1 to 4 or Use according to Claim 5 in the case of a layer to be etched which is located on a semiconductor substrate body is located in which a semiconductor component is already located.
DE19772723933 1975-12-04 1977-05-26 Etching metal, esp. polycrystalline silicon or aluminium - with definite angle of slope by ion bombardment before plasma etching Pending DE2723933A1 (en)

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DE19752554638 DE2554638A1 (en) 1975-12-04 1975-12-04 PROCESS FOR GENERATING DEFINED BOOT ANGLES FOR AN ETCHED EDGE
GB4434076A GB1551290A (en) 1975-12-04 1976-11-24 Ething of a layer supported on a substrate

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0003213A2 (en) * 1977-12-07 1979-08-08 Siemens Aktiengesellschaft Opto-electronic sensor based on the principle of charge injection and method for making it
EP0003733A1 (en) * 1977-12-05 1979-09-05 Siemens Aktiengesellschaft Process for the generation of windows having stepped edges within material layers of insulating material or of material for electrodes for the production of an integrated semiconductor circuit and MIS field-effect transistor with short channel length produced by this process
US4267011A (en) * 1978-09-29 1981-05-12 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device
US4314874A (en) * 1979-10-09 1982-02-09 Mitsubishi Denki Kabushiki Kaisha Method for forming a fine pattern of an aluminum film
EP0056530A2 (en) * 1981-01-12 1982-07-28 Kabushiki Kaisha Toshiba Process of forming a polycrystalline silicon pattern
EP0061350A1 (en) * 1981-03-25 1982-09-29 Hitachi, Ltd. Method of forming pattern
FR2542920A1 (en) * 1983-03-18 1984-09-21 Commissariat Energie Atomique METHOD FOR POSITIONING AN INTERCONNECTION LINE ON AN ELECTRIC CONTACT HOLE OF AN INTEGRATED CIRCUIT
CH662007A5 (en) * 1983-12-21 1987-08-31 Bbc Brown Boveri & Cie Method of soldering semiconductor components

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0003733A1 (en) * 1977-12-05 1979-09-05 Siemens Aktiengesellschaft Process for the generation of windows having stepped edges within material layers of insulating material or of material for electrodes for the production of an integrated semiconductor circuit and MIS field-effect transistor with short channel length produced by this process
EP0003213A2 (en) * 1977-12-07 1979-08-08 Siemens Aktiengesellschaft Opto-electronic sensor based on the principle of charge injection and method for making it
EP0003213A3 (en) * 1977-12-07 1979-09-05 Siemens Aktiengesellschaft Berlin Und Munchen Opto-electronic sensor based on the principle of charge injection and method for making it
US4267011A (en) * 1978-09-29 1981-05-12 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device
US4314874A (en) * 1979-10-09 1982-02-09 Mitsubishi Denki Kabushiki Kaisha Method for forming a fine pattern of an aluminum film
EP0056530A3 (en) * 1981-01-12 1982-08-18 Tokyo Shibaura Denki Kabushiki Kaisha Process of forming a polycrystalline silicon pattern
EP0056530A2 (en) * 1981-01-12 1982-07-28 Kabushiki Kaisha Toshiba Process of forming a polycrystalline silicon pattern
US4438556A (en) * 1981-01-12 1984-03-27 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming doped polycrystalline silicon pattern by selective implantation and plasma etching of undoped regions
EP0061350A1 (en) * 1981-03-25 1982-09-29 Hitachi, Ltd. Method of forming pattern
FR2542920A1 (en) * 1983-03-18 1984-09-21 Commissariat Energie Atomique METHOD FOR POSITIONING AN INTERCONNECTION LINE ON AN ELECTRIC CONTACT HOLE OF AN INTEGRATED CIRCUIT
EP0119917A1 (en) * 1983-03-18 1984-09-26 Commissariat A L'energie Atomique Positioning method for an interconnection line on an electrical contact hole of an integrated circuit
US4544445A (en) * 1983-03-18 1985-10-01 Commissariat A L'energie Atomique Process for positioning an interconnection line on an electric contact hole of an integrated circuit
CH662007A5 (en) * 1983-12-21 1987-08-31 Bbc Brown Boveri & Cie Method of soldering semiconductor components

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