DE2560577C2 - Injection semiconductor integrated circuit arrangement - Google Patents

Description

characterized in that

h) the first area (25) serving as a separation area in the half-liner (12) is belt-shaped is and

i) the second area (14) and an ohmic contact area (16) in each of the semiconductor sections (12a), which is belt-shaped through a lattice opening of the semiconductor layer (12) formed first region (25) are defined, are formed.

2. Semiconductor circuit arrangement according to claim

1, characterized in that a charge carrier blocking area (28) the semiconductor layer (12) penetrates up to the semiconductor substrate (11) and is arranged around the semiconductor layer (12).

3. Halley circuit arrangement according to claim

2, characterized in that there is an insulating layer on the charge carrier blocking area (28) (29) trained 1st.

60

The invention relates to an integrated injection (I ^{J L) semiconductor circuit arrangement} according to the preamble of claim 1. ft5

Such a ^ L-semiconductor circuit arrangement is the subject of the earlier patent DE-PS 25 12 737. In this 1 ^! In the L-semiconductor circuit arrangement, the separating regions consist of heavily doped semiconductor zones of the opposite conductivity type to the conductivity type of the semiconductor layer or of trenches which are etched into the semiconductor layer.

It is known that L-semiconductor circuit arrangements can be produced with a higher yield and higher integration density than TTL semiconductor circuit arrangements (TTL = transistor-transistor-dead logic). In general, such I ² L semiconductor circuit assemblies, e.g. B. from "Valvo reports", Volume XVIII (1974), Issue 1/2, pages 215 to 226, known.

The PL semiconductor circuit arrangements include a switching transistor and a lateral transistor, the Introducing minority charge carriers into the base region of the switching transistor.

In a conventional L semiconductor circuit arrangement, an N-type epitaxial semiconductor layer is grown on a semiconductor substrate with a predetermined conductivity type. As a P-conducting dopant, boron is diffused into the N-conducting semiconductor layer at a concentration of 10 "to 10" atoms / cm ³ in order to create a first and a second P-conducting area as a collector and emitter, respectively. As an N-conductive dopant, phosphorus is diffused into the first P-conductive region, to be precise with a concentration of 10 "to 10 ² 'atoms / cm', so as to form an N-conductive region.

An I ² L semiconductor circuit arrangement with this structure comprises a lateral transistor from the second P-conductive region as emitter, the N-conductive semiconductor layer as base and the first P-conductive region as collector and also a vertical transistor from the N-conductive Half-conductor area as the emitter, the first P-conducting area as the base and the N-conducting area as the collector.

The invention is based on the object of an IL semiconductor circuit arrangement to create according to the preamble of claim 1, in the case of high Efficiency of the individual Schaltka'.fslemente with simple means can be reliably separated electrically from one another.

This object is ^{achieved according to the invention in an I 2} L semiconductor circuit arrangement according to the preamble of claim I by the features contained in the characterizing part thereof.

In the invention, the first region thus acts simultaneously as a separating region and as the base of a lateral transistor, as a result of which simple electrical separation of the ^{circuit elements forming the I 2} L semiconductor circuit arrangement is achieved. For this purpose, the first region is formed with the same conductivity type as the semiconductor layer in the form of a grid in the I ² L semiconductor circuit arrangement in order to facilitate the integration of a large number of circuit elements.

Advantageous further developments of the invention emerge from patent claims 2 and 3.

Thus, in a further advantageous embodiment of the invention, a charge carrier blocking area is around an I ^! L-semiconductor circuit arrangement is provided around, which is formed by a plurality of integrated I ² L-Schalikrelselemente in order to prevent charge carriers from being lost to the outside.

Exemplary embodiments of the invention are described in more detail below with reference to the drawing:

Fig. 1 is a perspective view of an embodiment of the invention, in which a plurality of I ^! L-circuit elements are integrated on the same substrate; and

2 shows a perspective view of a further embodiment of the invention, in which the I ² L semiconductor circuit arrangement is surrounded by an area which blocks charge carriers and in which a multiplicity of I ² L circuit elements are integrated.

According to FIG. 1, an N-conducting semiconductor substrate 11 is overlaid by a P-conducting semiconductor layer 12. The semiconductor layer 12 is an epitaxial layer vapor-deposited onto the N-conductive semiconductor substrate 1 ϊ, which has a dopant concentration of 10 ¹⁴ to 10 "atoms / cm 'and a thickness of 2 to 3 μm and is doped with boron to give P ~ conductivity A region 14 (second region) is formed by diffusing phosphorus in order to achieve N conductivity in the P "-conducting semiconductor layer 12 with a concentration of ΙΟ" ¹ to 10 '"or from 10" to 10 ²⁰ atoms / cm ^!

An ohmic P * conductive contact area 16 is in the P -conducting semiconductor layer 12 by thermal diffusion of boron in an oxidizing high-temperature atmosphere from iö5 (r C to a depth of ί to 2 μπι made.

On the N-conductive area 14 and on the contact area 16, aluminum is vapor-deposited, which _{extends through openings in an insulating layer made of SiO 2 in} order to create electrodes.

The I ² L circuit element comprises a lateral PNP transistor LTr and a vertical NPN transistor ITr. In the case of the transistor VTr , the emitter is formed by the N-conducting semiconductor substrate 11, the base by the P-conducting semiconductor layer 12 and the collector by the second N-conducting region 14.

In the present embodiment of the invention according to FIG. 1, a multiplicity of I ² L circuit elements are now shown, which are integrated on the same substrate 11. For this purpose, a grid-shaped N-conductive region 25 (first region) is formed in the P-leading semiconductor layer 12, which extends as far as the N-conductive semiconductor substrate 11 below. In this grid-shaped N-conductive area 25, a gilier-shaped P-conductive area 26 (third area) is formed. The P "-conducting half-liner layer: 12 is subdivided into a plurality of sections 12a by this lattice-shaped first N-conductive area 25, the N-conductive area 14 and the P-conductive contact area 16 being formed in each of these sections 12a.

In the 1 ² L semiconductor circuit arrangement according to FIG. 1, a 1 ² L circuit element 27 is shown by dashed lines. Each I ² L circuit element 27 is surrounded by the grid-shaped, P-conductive region 26, which acts as an injector and through which a large number of minority charge carriers in the collector of the lateral PNP transistor LTr formed from the sections 12a Introduced from the area 25 existing base and through which the function of the I ² L circuit element can be improved. The neutral area 25 acts at the same time as a separating area for separating the respective I ² L switching elements from one another, which eliminates the need for an otherwise necessary separating area and, as a result, the design pattern of the I ^! L-semiconductor circuitry is greatly simplified.

The only disadvantage of the embodiment according to FIG. 1 is that the charge carriers are lost on the sides of the I ² L half-circuit arrangement, which prevents these charge carriers from being used effectively.

In view of this disadvantage, a further embodiment of the invention is shown in FIG. 2, in which an N-conducting region 28, which blocks the charge carriers, is arranged around the P'-conducting semiconductor layer 12 of the I ² L semiconductor circuit arrangement. It is therefore possible to design the area 28 blocking the charge carriers in such a way that contact is made with an area 25a of the first N-conductive area 25 which is arranged closest to the outer end face of the P ~ -conductive semiconductor layer 12. so as to achieve a P-type region 26a which is formed in the region 25a of the first N-type region 25, or around those P-type semiconductor sections 12a of FIG. 1 ^; L-circuit element 27a to contact which are arranged closest to the side of the semiconductor layer 12. The area 28 blocking the charge carriers can at the same time act as an insulation layer. The embodiment according to FIG. 2 has a further insulation layer 29, which is attached to the N-end region 28, which blocks the charge carriers. u'J's is superimposed. thereby enabling the region 2 "to be formed into a P ^T -type without change when the P-type region 26 is provided.

With all of the embodiments it is possible for the minority charge carriers to be effectively emitted by the injector of the lateral PNP transistor contained ^{in the I 2 L circuit element.}

In the embodiments described, there is an N-conducting Semiconductor substrate selected, and the conductivity types of all other semiconductor layers and areas are thereby determined. However, it is also possible to provide a P-conductive semiconductor substrate and all others Form semiconductor layers and regions with a corresponding reversal of the conductivity type.

1 sheet of drawings

Claims (1)

IO 25 claims: 1. InjekUons semiconductor integrated circuit device. consisting of a) a semiconductor substrate (11) of one conductivity type, b) one applied to the semiconductor substrate (11), epitaxial semiconductor search (12) des opposite line type, c) a first region (25) of the one conductivity type, which is in the semiconductor layer (12) Is trained, and el) the semiconductor layer (12) starting from the surface of the semiconductor layer (12) penetrated and contacted the semiconductor substrate (11), c2) a third region (26) of the opposite conductivity type, that of the flat Surface of the first area (25) starting in the first area (25; is formed, d) at least one second region (14) of the one conductivity type which is present in the semiconductor layer (12) is formed at a distance from the first region (25), wherein e) the third area (26), the first area (25) and the semiconductor layer (12) form a lateral transistor of one polarity, f) the semiconductor substrate (11), the semiconductor layer (12) and the second region (14) form a vertical transistor of opposite polarity, and g) a separation area, which the second Area (14) and the third Be-tich (26) surrounds and from the surface of the semiconductor layer (12) extends to the semiconductor substrate (11),