DE2447844B2

DE2447844B2 - ARRANGEMENT FOR CONTROLLING ALARM INDICATOR LAMPS IN A CENTRAL DISPLAY PANEL FOR OPERATIONAL MONITORING OF MESSAGE TRANSMISSION SYSTEMS

Info

Publication number: DE2447844B2
Application number: DE19742447844
Authority: DE
Inventors: Joel Dr.-Ing. 7150 Backnang Korn
Original assignee: Licentia Patent Verwaltungs GmbH
Current assignee: Bosch Telecom GmbH
Priority date: 1969-07-14
Filing date: 1974-10-08
Publication date: 1976-10-07
Also published as: DE2447844A1

Description

Taktverarbeitung bestimmte Gatter vorgesehen sind, von denen das erste von einem ersten Taktgeber und dem ersten Ausgang des Quittierungsspeichers und das »weite von einem zweiten Taktgeber mit kleinerer Taktfrequenz und dem komplementären zweiten Ausgang des Quittierungsspeichers ges euert wird, daß der Ausgang des ersten Gatters m!( dem einen Eingang eines Hilfsgatters verbunden ist, dessen zweiter Eingang vom zugehörigen Alarmkontakt gesteuert wird, und daß die Ausgänge des Hilfsgatters und des zweiten Gatters über je einen Widerstand mit der Basis des Lampentransistors verbunden sind.Clock processing certain gates are provided, the first of which from a first clock generator and the first output of the acknowledgment memory and the »wide of a second clock with a smaller one Clock frequency and the complementary second output of the acknowledgment memory is controlled that the output of the first gate m! (to which one input of an auxiliary gate is connected, the second input of which is controlled by the associated alarm contact, and that the outputs of the auxiliary gate and the second gate are each connected to the base of the lamp transistor via a resistor.

Ein Ausführungsbeispiel der Erfindung zeigt die Figur.The figure shows an embodiment of the invention.

Die Gatter C 1 und G 2 bilden den Quittierungsspeieher, der über die Steuerungs-Gatter G 3 und G 4 von dem Quittierimpuls an der Klemme Q oder vom Potential des Meldeeingangs E gesteuert wird. Die Wirkungsweise dieses Teils der Anordnung ist die gleiche wie im Hauptpatent.The gates C 1 and G 2 form the acknowledgment store, which is controlled via the control gates G 3 and G 4 by the acknowledgment pulse at the terminal Q or by the potential of the message input E. The operation of this part of the arrangement is the same as in the main patent.

G5 und G6 sind ein erstes und zweites Taktgatter, G 7 das Hilfsgatter. Alle Gatter sind Nand-Gatter.G5 and G6 are a first and second clock gate, G 7 the auxiliary gate. All gates are NAND gates.

Die Wirkungsweise der Anordnung ist folgende:The mode of operation of the arrangement is as follows:

Im störungsfreien Zustand herrscht am Ausgang A 1 des Quittierungsspeichers der Zustand 1, am Ausgang A 2 der Zustand 0, am Ausgang des Taktgatters G 6 der Zustand 1, am Meldeeingang E der Zustand 0 und am Ausgang des Hilfsgatters G 7 der Zustand 1. Der Lampentransistor Ts erhält keinen Basisstrom, und die Lampe leuchtet nicht.In the trouble-free state, the output A 1 of the acknowledgment memory has the state 1, the output A 2 has the state 0, the output of the clock gate G 6 has the state 1, the message input E has the state 0 and the output of the auxiliary gate G 7 has the state 1. The Lamp transistor Ts receives no base current and the lamp does not light up.

Tritt eine Störung auf, so erhält der Meldeeingang E den Zustand 1. Das Taktgatter G 5 folgt dem schnellen Takt seines Eingangs T\, weil sein zweiter Eingang von A 1 den Zustand 1 hat. Das Hilfsgatfer G 7 folgt den Ausgangstakt des ersten Taktgatters G 5, weil sein zweiter Eingang von E den Zustand 1 hat. Über den Widerstand R 2 erhält der Lampentransistor im Rhythmus des schnellen Taktes Basisstrom, und die Lampe flackert schnell.If a fault occurs, the message input E receives the state 1. The clock gate G 5 follows the fast clock of its input T \ because its second input of A 1 has the state 1. The auxiliary gate G 7 follows the output clock of the first clock gate G 5 because its second input of E has the state 1. The lamp transistor receives base current via the resistor R 2 in the rhythm of the fast cycle, and the lamp flickers quickly.

Nach dem Quittieren durch Anlegen einer 1 an die Klemme C* kippt der Quittierungsspeicher unv. sein Ausgang A 1 erhält den Zustand 0 und sein Ausgang A 2 den Zustand 1. Der Ausgang des Taktgatters G 5 erhalt den Zustand 1, damit erhält der Ausgang des Hilfsgatters G 7 den Zustand 0. Das zweite Taktgatter G 6 kann jetzt dem langsamen Takt folgen. Der Lampentransistor erhall über R 2 dauernd Basisstrom und über R 1 zusätzlich einen getakteten Basisstrom. Die Lampe leuchtet stetig.After the acknowledgment by applying a 1 to terminal C *, the acknowledgment memory flips over. Its output A 1 receives the state 0 and its output A 2 the state 1. The output of the clock gate G 5 receives the state 1, so the output of the Auxiliary gate G 7 the state 0. The second clock gate G 6 can now follow the slow clock. The lamp transistor receives a permanent base current via R 2 and an additional clocked base current via R 1. The lamp lights up steadily.

Wenn die Störung beendet ist und der Alarmkontakt geöffnet wird, erhält der Meideeingang f wieder eine O. Der Ausgang des Hilfsgatters G 7 erhalt cine I, der Lampentransistor erhält nur vom /weiten Taktgatier G6 über R 1 einen getakteten Basisstrom und flackert im langsamen Rhythmus.When the fault has ended and the alarm contact is opened, the avoidance input f receives an O again. The output of the auxiliary gate G 7 receives a I, the lamp transistor only receives a clocked base current from the / wide clock gate G6 via R 1 and flickers in a slow rhythm.

Nach abermaligem Quittieren über das Steuergatier G3 kippt der Quittierungsspeieher in seine Ruhelage. und die Lampe erlischt.After another acknowledgment via control gate G3, the acknowledgment store tilts into its rest position. and the lamp goes out.

Hit.'zu 1 Blatt ZeichnungenHit. 'To 1 sheet of drawings

Claims

3 243 24

Claim:

Electronic arrangement for controlling alarm indicator lamps in a central display field for communication systems, in which every possible fault can be evaluated by a monitoring receiver that closes an alarm contact when a fault occurs to earth, and in which an indicator lamp is provided for every possible fault, which is controlled in this way is that when the fault begins and the alarm contact closes, the lamp begins to flicker, when an acknowledgment button is pressed the lamp lights continuously, when the fault ends and the alarm contact is opened, the lamp flickers again and when the acknowledgment button is pressed again (acknowledgment of the end of the fault) the The lamp goes out, the control arrangement consisting of the lamp transistor, the emitter of which is connected to the pole of the supply voltage opposite to the earth potential, the collector of which is connected to the alarm contact via the indicator lamp and the base of a base series resistor to the alarm contact There is an electronic acknowledgment memory that controls a clock generator via an electronic switch in such a way that, in its rest position, a short-circuiting clock output in the rhythm of the flashing frequency short-circuits the base circuit of the Lanipentransistor and periodically extinguishes the burning lamp, while in its tight state a slrom-delivering clock output in the rhythm of the Flashing frequency of the base of the lamp transistor supplies a control current when the alarm contact is open and brings the lamp to light up periodically, the acknowledgment memory is controlled by the alarm contact and an acknowledgment button in such a way that when the alarm contact is open, the acknowledgment memory is in its rest position through the acknowledgment button and only in when the alarm contact is closed its excited position can herd and the acknowledgment memory consists of two NAND gates, the outputs of which are fed back to one of the two inputs of the complementary gate and the other inputs of which are set inputs, via which the state of the memory is determined by applying short 0-pulses, the set inputs having state 1 outside the setting time according to Patent 19 35 612, characterized in that two gates intended for clock processing are provided by which the first (G 5) from a first clock (Tl) and the first output (A 1) of the (acknowledgment memory and the second (G 6) from a second clock (T2) with a low clock frequency and the complementary second output (A 2 ) of the acknowledgment memory is controlled that the output of the first gate is connected to one input of an auxiliary gate (G7) , the second input of which is controlled by the associated alarm contact (E) and that the outputs of the auxiliary gate and the second gate each via a resistor ( R 2 or RX) are connected to the base of the lamp transistor (Ts) .

844 ₂

The main patent relates to an electronic arrangement for controlling alarm indicator lamps in a central display panel for communication systems, in which every possible interference can be detected by a monitoring receiver, the one Alarm contact closes in the event of a fault to earth, and for every possible fault an indicator lamp is provided which is controlled in such a way that at the beginning of the fault and closing of the Alarm contact the lamp starts to flicker, when an acknowledgment button is pressed the lamp continues to flicker if the malfunction ends and the alarm contact is opened, the lamp flickers again and when pressing the acknowledgment button again (acknowledgment of the end of the fault) the lamp goes out, whereby the Control arrangement from a lamp transistor, the emitter of which with the pole opposite to the earth potential the supply voltage, its collector via the indicator lamp with earth potential and its base via a basic series resistor is connected to the alarm contact, and from an electronic acknowledgment memory exists, which controls a clock generator via an electronic switch so that in its rest position a short-circuiting clock output short-circuits the base circuit of the lamp transistor in the rhythm of the flashing frequency and the periodically extinguishes the burning lamp. while in its excited state a current-supplying one Clock output in the rhythm of the flashing frequency of the base of the lamp transistor when open Alarm contact supplies a control current and brings the lamp to light up periodically, the Acknowledgment memory is controlled by the alarm contact and an acknowledgment button so that when the Alarm contact of the acknowledgment memory through the acknowledgment button only in its rest position and at closed alarm contact can only be brought into its excited position and the acknowledgment memory consists of two NAND gates whose outputs are complementary to one of the two inputs of the Gates are fed back and their other inputs are set inputs via which the state of the SDeichers is determined by applying short 0-pulses, with the set inputs outside the set time can have state 1.

The electronic changeover switch of the arrangement according to the main patent consists of the push-pull circuit of two transistors (Tt 1 and Tt 2), whose base connections are connected to the output of the acknowledgment memory, whose collector connections are connected to the base of the lamp transistor via a voltage divider and whose emitter is connected to the output of the fast resp. slow clock. When using an acknowledgment memory built up from integrated digital gates, as described in the main patent. there are adjustment difficulties between the integrated acknowledgment memory and the non-integrated switch.

In the case of a modern solution using only integrated modules if possible, it makes sense to also build the electronic switch from integrated digital gates.

The object of this invention is to design the arrangement according to the main patent so that the acknowledgment memory and the electronic switch consist of the same integrated digital gates.

To solve this problem, the arrangement according to the invention is characterized in that two for