DE2107521C3 - Clock generator for a step-by-step pilot regulator - Google Patents

Description

The invention relates to a clock generator for a step-by-step pilot controller of carrier frequency systems, which contains a reversible binary counter made of integrated flip-flops, whose counting direction is via / - and ^ Inputs of the flip-flops is controlled by applying 0 or 1 potentials and in synchronous operation the simultaneous application of clock pulses causes all flip-flops to continue counting, with the pilot regulator has a level discriminator controlled by the pilot voltage which, when a Level deviation enables the clock and determines the direction of the counter.

Such a circuit arrangement is known (DE-PS 35 525).

There are also arrangements for stepwise level control of carrier frequency systems are known, in which a pilot voltage is evaluated by a level discriminator which, if a Level deviation from the setpoint the counting direction of a reversible binary counter serving as an interlocking determined and activated a clock to operate the binary counter (DE-PS 11 18 831).

Such reversible binary counters consist of a number of flip-flops that can be accessed electronically Gates are interconnected.

For reasons of economy and space saving, it is now advantageous to use the meter from commercially available, build integrated / - ^ - flip-flops with a clock input.

Such a / -K-FIip-FIop with a clock input T has two condition inputs / and K, via which its mode of action is prescribed when a clock pulse is applied by applying potentials corresponding to logic 0 or 1 states. To operate the flip-flop, both edges of the clock pulse are required, whereby the effect starts from a certain pulse height of the starting edge of the clock pulse.It is not permitted to change the states of the / - and if inputs while a clock pulse occurs, otherwise it will react the flip flop wrong.

In the known arrangement of DE-PS 11 35 525 described above, the clock is rrit the Level discriminator coupled so that the clock is only released when the discriminator responds and after a specified, short delay time after setting the advance direction the counter a first clock pulse occurs and the counter immediately by one step in the target direction changed, while the further clock pulses follow according to the clock frequency until the discriminator has returned to its rest position

This ensures that there is no erratic

The counter changes at the beginning of a control process. At the end of a control process, The clock generator was held by the discriminator and the state of the / -K inputs was changed. The holding of the clock can act like a clock pulse

J5 and, since this pulse occurs when the counter JK inputs are switched, it causes the counter to change abruptly.

The invention is based on the object, in an arrangement of the type mentioned at the outset, to prevent that by holding the clock there is an abrupt change in the counter

This object is achieved according to the invention in that the actual clock generator has an arrangement is connected downstream, which is derived from the original clock of the clock generator by differentiating the The end edge of the initial clock wins, and that at the end of the control process not only the clock generator from the discriminator recorded, but also prevents the occurrence of a derived measure.

An embodiment of the arrangement according to the invention is shown in the drawing

PD is the level discriminator, TG is the clock and Z is the counter. The clock generator is controlled by the level discriminator via its output AT in such a way that it has a negative potential at its output A when the level is setpoint and emits relatively short positive pulses when the level deviates from the setpoint. The counter receives level discriminator on the outputs Al and his AK / - and

Control potentials corresponding to ω K inputs.

The arrangement for deriving the clock consists of a transistor Ts in an emitter circuit with a collector resistor R 1, the base of which via a decoupling diode D and a differentiating capacitor

μ C to the output A of the clock generator TG, via the decoupling diode D and a base series resistor Λ 2 to the positive pole of the operating voltage UB and via a further base series resistor R 3 to the

Output A T of the level discriminator PD is connected and whose collector is connected to the clock input T of the counter .Z.

The mode of operation of the entire arrangement is as follows: At the nominal value of the level, there is positive potential at the output AT of the level discriminator; the transistor Ts receives base current via the base series resistor R 3 and is conductive; the clock input T of the counter is at negative potential and the counter is blocked

Upon the occurrence of a level deviation from the target value, the control direction of the counter through its inputs / and K is adjusted immediately in accordance At the output ATdes level discriminator negative potential occurs, the clock generator TG is released, and top R 3 no base current flows more in the transistor Ts. Upper R 2 and the diode D but base current flows into the transistor 7s. The first positive pulse occurs at output A of the clock generator, during the duration of which the differentiating capacitor C is charged so that its left coating is positive and its right coating is negative. At the end of the first pulse, during its negative edge, the left capacitor plate is brought to the negative potential of the operating voltage, the capacitor voltage has a blocking effect on the transistor until the capacitor is reloaded via the base series resistor R 2; This differentiated pulse causes the transistor to be blocked for a short time and supplies a short positive clock pulse to the counter.

If there is a level deviation, further pulses occur in the rhythm of the clock frequency, which adjust the counter in the desired direction. The transistor TS is therefore continuously conductive and is blocked for a short time in order to emit a derived positive clock pulse

When the setpoint is reached, the level discriminator immediately detects the clock and the counter at its / - / C inputs is switched over to the level. In addition, the transistor Ts receives base current via the output AT of the level discriminator and R 3, which base current also flows when a differentiated pulse occurs as a result of the clock tipping over

occurs at the capacitor C. The decoupling diode D prevents the current flowing over /? 3 from being sucked off and the transistor Ts from blocking

of the counter is eliminated It can be seen that at the beginning of a control process between the reversal of the / - ^ - inputs and the occurrence of a first derived clock pulse, a time elapses which is equal to the duration of a positive pulse of the actual clock generator TG . This time is relatively small hold, the duty cycle of the clock generator is made highly asymmetrical, so that short positive and long negative pulses arise.

1 sheet of drawings

Claims (3)

Patent claims: 1. Clock for a step-by-step pilot regulator of carrier frequency systems, which contains a reversible binary counter made of integrated flip-flops, the counting direction of which is controlled via / - and / C inputs of the flip-flops by applying 0 or 1 potentials and which is operated in synchronous mode simultaneous application of clock pulses to all flip-flops is caused to continue counting, the pilot regulator having a level discriminator controlled by the pilot voltage, which releases the clock when a level deviation occurs and determines the incremental direction of the counter, characterized in that the actual clock (TG) an arrangement is connected downstream, which derives a clock derived from the original clock by time differentiation of the end edge of the original clock, and that at the end of the control process not only the clock is held in front of the discriminator, but also the occurrence of a derived clock is prevented. 2. Clock according to claim 1, characterized in that the arrangement for deriving the clock consists of a transisotr (Ts) in emitter circuit, the base of which via a decoupling diode (D) and a differentiating capacitor (C) to the output (A) of the Clock (TC), via the decoupling diode (D) and a base series resistor (/? 2) to the positive pole of the operating voltage (UB) and via a further base series resistor (R 3) to the output (AT) dts level discriminator (PD) and its collector with the clock input (T) of the counter (Z) ve. aunden is. 3. Clock generator according to claim 1, characterized in that the actual clock generator (TG) supplies pulses with a highly asymmetrical pulse duty factor with short positive and long negative pulses.