DE2326798C3 - Control device for a serial printer - Google Patents

Description

The invention relates to a control device for controlling a serial printer, which has a print logic has a data input, a constant drive mechanism, an anvil and a Print head, which is optionally driven by actuating a clutch that is parallel to the anvil and is automatically returned to the rest position when the clutch is released, the Control device is inserted between the data input and the print logic, and a register with an output connected to the print logic and with an input for the momentary storage of a single character as well as a buffer register with an input for the second input of digitally coded characters and an output for serial output of the digitally encoded characters to the register.

Such serial printers have a simply constructed drive mechanism and a high printing speed. However, they are only suitable for synchronous operation, i. H. for simultaneous data entry at the entrance of the printer. When used in conjunction with an input memory, they are also fed with input data that is faster than the printing speed can be entered as long as the capacity of the input memory is not exceeded. You read z. B. not feed with a typewriter-like data entry, the data flow is much lower than the printing speed, namely only a few characters per second in the Compared to a printing speed of 180 characters per second, for example.

In the case of data input with a lower data flow than the printing speed, up to now only increment printer used, d. H. Printer with a stepper motor. Such printers are however, it is costly because it has a complex control circuit for the motor and an expensive motor demand.

The invention is based on the object of providing a control device of the type mentioned at the beginning create, which an asynchronous output of alphanumeric characters regardless of the rhythm Entering the same allows between zero and a maximum, through the properties of the printer using an automatic mail merge printer.

When the rhythm of entering characters is equal to or faster than the printing speed of the Printer, the latter works continuously. However, if the rhythm of the data entry is slower, the printer works step by step.

The solution to this problem is given by an addressing device for the buffer register input, which indicates the address of the last character given to the buffer register input by a Addressing device for the buffer register output,

which indicates the address of the first character to be forwarded to the buffer register output, by a logical comparator which is the buffer register input address constantly compares with the highest address and with the buffer register output address, by an operation control means which, depending on the comparison result of the! Comparator, the input of a character to the input of the register or the transmission of a Characters-ä at the output of the same releases, and by a marker device to mark the through the printhead taken up at the coincidence of the addresses and to control the return of the printhead to the rest position in the event of coincidence and to control the speed of the printhead along the anvil until the assumed position is exceeded, if after one Coincidence new characters are entered.

Further developments are characterized in the subclaims.

The invention is illustrated below with reference to schematic drawings of an exemplary embodiment described in addition.

F i g. 1 is a schematic view of a known one Printer for use in connection with the invention;

F i g. 2 is a block diagram of a printer according to FIG the invention;

F i g. 3 is a block diagram of the control device according to the invention;

F i g. 4 and 5 are diagrams to illustrate the operation, and

F i g. 6 and 7 are flowcharts of operation control for the input and output of the controller, respectively according to FIG. 3.

F i g. Fig. 1 shows in detail an example of a printer for use in the present invention.

The printer uses a print head 1 which rests movably on two guideways (not shown) which run parallel to an anvil or plate 2 which does not move axially. The head is moved evenly from left to right by means of a drive belt 3 which is looped through two disks 4a, Ab. The pulley 46 is driven at a constant speed by a motor, for example a drive device 11 in the form of a synchronous single-phase motor, which rotates at a constant speed in the direction of the arrow, by an electromagnetically connectable belt and a pulley clutch 10. For easier illustration, the electrical supply device of the motor , the clutch and the control device for the clutch are not shown since they are conventional and known.

If the electromagnetic clutch 10 is released, the print head automatically returns to its Rest position at the far left end of the back, this is done by a spring 6 that normally comes with connected to a buffer which is not shown. One end of the spring is connected to the head 1, the other end with the frame of the device, which is symbolically marked with 13. the Spring 6 can of course be replaced by any other preloading system (for example electromagnetic).

The actuation of the clutch IO causes the head to begin to move from its rest position to the right. To ensure that printing is only carried out when the head is moved smoothly, the beginning of the printed line is shifted from the rest position. For this purpose, a photo-coupling arrangement 7 consisting of a light source and a transducer detects the passage of the head, and the latter actuates a cover plate 5 which normally covers the light source. As soon as the cover plate is actuated, a line start signal DL is generated. A regularly slotted disk 9 connected to the photocoupling device 8 (light source and a converter) generates a signal DC which synchronizes the start of printing of a letter. The signals DL and DC are applied to a conventional print logic 12, which receives coded input data at the input end 14 from an external control device (not shown) and controls the operation of the head.

For this purpose, the printing logic 12 controls under the control of the data applied to the input 14 and the signals DL and DC

- (i) Jen jump of the paper, through a to the

Plate applied line feed signal LF;

- (ii) the printing process, via a Si

gnal Ci, which is applied to the head in order to control the pressure elements of the head (actuation of selected electromagnets in the case of a head of the type mentioned above), and to the coupling 10 for energizing the same,

(iii) the continuous movement of the head when no printing is being performed by means of a signal HT (tabulation signal) to insert a space or a space bar either at the beginning of a line or during a line.

When data recorded in coded form is applied to input 14, rie are decoded in the printing logic and, if there are letter signals, are applied to the inputs of the head control synchronously with the DC signal, while the logic at the same time excites the clutch ( Signal Cl) controls. In order to achieve correct operation, the letter data must be applied to input 14 at printing speed; they can also be applied to the input at greater speed if the printing logic has a memory.

When the print head reaches the rightmost print position, a known one, not shown, controls Detector (a photocell array or any other Device that indicates the end of the line) the de-excitation of the clutch 10.

With this type of printer, the speed of data entry cannot be slower than that of the print head. Either is the clutch

not de-excited when there is no data to be printed and between each letter irregular vacancies would appear depending on the work of the printhead between the recording of consecutive data, or the clutch is de-energized (which is usually the Case is) and the head is moved back to its rest position: In the latter case, the successive Data either printed on top of each other

or at the beginning of consecutive lines, when the paper is moved further by de-energizing the clutch.

Printers of the ArI described above can be made into pseudo-incremental printers. by between the data input 14 and the printing logic d: e control device according to the invention is installed, the block diagram of which is shown in FIG is.

The basic idea of the invention, which enables an incremental operation of a synchronous printer, is as follows: If at a certain moment there are no more letters to be printed, the position of the print head is registered after the last letter has been printed, while the head is in its rest position is moved back far left, the RückkehT of Druckko ⁿ fcs not ^v on a Paniorsprung is accompanied.

As soon as new letters arrive, the printing process starts all over again, in the same place Line as before return of the head to the rest position, starting with that on the last one printed Letter following position.

For this purpose, the control device consists essentially of a buffer register 101 of the RAM (Random Access Memory) type, the output of which is connected to the print logic 12 via an output register 314 , of devices 17 and 18 for the respective display of the input address Ali and the output address AS to the register , from a logical comparator 304. which compares these addresses with one another and with the maximum capacity of the register, from a sequence control device 20 which enables the input of a character into the register or the output of a character from the register, depending on the results of the comparison in the logic comparator 304. and a device 21 for noting the position of the print head when the printing process is interrupted and for controlling the return of the print head to its rest position and then to the position following the last print as soon as a letter character appears on the Input 14 is placed.

F i g. 2 is a general block diagram illustrating the logical functions of the various basic elements of the control unit 15.

The release * ^: signals from the sequence control device 20 to the register 101 are fed through the lines 20a and Tfib. The signal OKE on the line 20 a connects the input 14 to the buffer register 101 and controls the transmission of an input character to the register at the address AE, while the signal OKS on the line 20 b the transmission of the character in the buffer register at the address AS to output register 314 .

When a signal OKS (the signal complementary to OKS ) is supplied, the sequence control device 21 notes the position of the printhead and supplies an instruction character to the output register (which at this time is not fed by the buffer register 101 ) via the line 21 α to return the head to its rest position (signal CRF, which controls the de-excitation of the clutch 10 in the case of the printer shown in FIG. 1). When the sequence controller 21 provides another OCS-Signa \, the coupling of the buffer register 101 triggers the register 314 via the line 21 b the device 21, which now controls the return of the print head in the following to the last print position position.

F i g. 4, 5 a and 5 b illustrate the mode of action of data acquisition and printing of the individual letters.

The buffer register 101 comprises, for example, 256 memory units, each of which can hold a group of 8 bits and forms an octet which

ίο is determined by the corresponding address a, b, c, r /, r ... (sub-units 101 π- 101 r, Fig. 4). In the figure it is assumed that each memory position in the row of data acquisition has received the characters A, Tt, C and D , the individual successive characters of course being able to be separated from one another by any time interval.

Two addressing devices are assigned to the buffer repister 101 , namely an input addressing device 17 and an output addressing device 18, which determine the address of the character entered last, that is to say in the particular embodiment according to FIG. 4 the addresses d and α of the characters D and A. It follows that every time a new character is entered into the buffer register, the input addressing device 17 is switched one step to the right, and that every time a new character is output, the Output addressing device 18 is switched one step to rcch'.s wciter independently of the input addressing device. When the characters A, B, C and D have been successively entered into the buffer register 101 , which form the word AIiCD, the input addressing device 17 successively displays the addresses a, b, c and d .

Assuming the printhead is in a correct position. the output addressing device 18 initially denotes the position 101 α in the buffer register 101 and enables the output of the character A. Then it continues character by character as a function of the step speed of the print head, the positions 101 b. 101 c and 101 d of the buffer register 101 are designated and the output of the characters B, C and D is enabled, respectively. As soon as the position 101d is designated by the input addressing device 17, the word ABCD is output. At this moment, the control device 21 controls the return of the print head to its rest position, namely ur.er the action of the spring 6 (Fig. 1). Since there is no paper jump (or line feed), this position is just before the beginning of the line that has just been printed and which is referred to in the following as the "print line". Due to the inertia of the print head, a small space is provided between the rest position and the beginning of the print cell to regulate the distance between the individual letters. The address of the most recently output character D is stored in an auxiliary memory so that the print head can resume forwarding immediately after a new character has come to the position where it is to be output. This is done by generating a number of spaces equal to the content of the auxiliary memory (marker device).

The addresses contained in the two addressing devices are, as will be explained below

is. determined, and the comparison of the contents from the Auxiliary memories enable, capture or output of characters in or from the memory.

The various positions of the buffer register 101 are of course not permanently occupied. They become jedcsmv free when a new character is output. Special means are provided to block the output of characters when the buffer register is empty. and to block the detection of characters when the buffer register is occupied, which is equivalent to limiting the displacement of the two address code devices 17 and 18 in FIG.

Fig. 5 shows another possibility in which the output of a word or a character after a Number of steps takes place. As shown in FIG. 5

Zn 19 spaces upstream, starting from the beginning of the line. First, "0 " is introduced to "tabulate" the code in the successive positions of the buffer register 101, as shown in FIG. 5a. then the number of spaces before a character to be output (here the 20th position) reduced by one unit, which corresponds to 19 consecutive spaces. This number is converted to binary code and finally the code of the character, such as Z, is output. The successive analysis of the contents of the successive positions of the buffer register 101 by the output addressing device results in a shift of the print head from the beginning of the line to the position at which the character Z is to be printed, that is the 20th position, as shown in FIG. 5b.

This feature of the controller has the advantage of having a number of locations in the memory that would otherwise be required for the successive generation of several tab codes and that at the same time the character acquisition speed for the following characters is increased. 4 "

Theoretically: The OKS signal appears as long as there is at least one character in the buffer register 101 . The OKE signal appears as long as the buffer register is not filled, ie as long as Λ E <256 in the present example. In practice, input and output to and from the buffer register do not take place completely simultaneously, and therefore devices are provided to synchronize input and output, as will be described further below with regard to an in FIG. 3, namely a master clock generator 504 which supplies release signals, will be explained in more detail.

The buffer register 101 of FIG. 2 is formed here from a RAM (Random Access Memory), which has a capacity of 256 groups of eight. Input and output lines of device 101 are shown here as single lines, but in reality there are eight parallel lines for input and eight parallel lines for output. Eight lines are also provided for inputting and outputting data.

Each time a character arrives at input 14 , a counter 302 is incremented; this counter indicates the address where this character must be registered in the register. Likewise, a counter 303 is incremented whenever a character is removed from register 101 and designates the address where this character can be found.

Thus, the operating address AD is optionally indicated by the counters 302 and 303 , which each have S bits and can therefore address the 256 memory positions of the buffer register. The content of these counters is decoded in the decoder 309. The arrangement of 302-309 corresponding to the device 17, the arrangement 303-309 of the apparatus 18 of F i g. 2.

The conditions under which a signal is entered into the memory register 101 are: Register not full and output address AS Φ input cadrcssc AE: a signal OKE is then generated.

The prerequisites for the output of a signal are: Register not empty, output address AS / input address AE 'riämüch AS -K. AE, since AS ^> AE impossible); then an OKS signal is generated.

For this purpose, a flip-flop 400 is brought to "I" via the carry pulse from counter 302 (state R) and back to zero (state 77) via the carry pulse from counter 303. Since the logic circuits 401 each have two inputs which are connected to the outputs of the comparator 19 or the flip-flop 400 , they generate the signals

OKE = Ή (AE φ AS), OKS = R. (AE φ AS).

The sequence control unit 20 according to FIG. 2 is formed from the two devices 316 (input sequence control unit) and 317 (output sequence control unit).

The OKE signal is applied to the device 316 , while the OKS signal is applied to the device

317 is laid. These two devices are also driven by master clock 504 so that the output signals do not appear at the same time. Although the master clock 504 is shown in this figure as part of the control unit 15 , it is understood that the output signals of the master clock, which is normally part of the conventional print logic 12 , also as signals to the sequence control devices 317 and

318 can be placed.

Each seven-bit character to be entered into the buffer register includes a signal SE which is applied to the input sequence controller 316. As long as the signal SE is present, the voltages must be absolutely stable. While the data signal is formed from eight logic levels which are applied in parallel to eight feed lines, the signal SE is applied to the unit 316 via a separate line. For a better illustration, however, all external control signals are drawn in such a way that they lead to a single end point 14 .

The input unit 316 consists of two bistable devices HE ₁ , 316 a, 316 b, HE ₂ . It can be triggered in four different states, as the table below shows, where HE ₁ and // E _{2 are} the bistable states of 316 a and 3166 .

HE _t HE ₁ state

0
1
0
1

0
1
2
3

State 0 is the idle state, the buffer register waits for a character to be entered.

When the OKE signal is present, the SE signal causes the unit 316 to cycle:

State I: The one indicated by the counter 302 Address will be sPbil;

- State 3: the input signal is written into the buffer register when dps signal E - HE ₁ . Signal ///? Means state I of 316 ", and HE ι means state 0 of the same. Σ is present, where L indicates that the output sequence record unit is in state 1 or 2, which latter is explained below, and which corresponds to the reading of a letter or a Tahulieradrcsse from the buffer register;

- State 2: Acknowledgment signal ACK from the buffer register to the external control unit controls the deletion of the signal5 £, and, if the latter is off,

- Return to state 0.

F i g. 6 shows the flow diagram of the unit 316.

When the signal OKS is present (which means that claC at least one character is registered in the buffer register 101), the output sequence / control unit controls the transfer of characters registered at the address AS in 101 to an S-bit output register 314 .

As mentioned earlier, these characters are either "print codes"; H. Codes that prevent the printing of Cause letters (these are essentially letter codes) or »function codes«, such as B. tabulator, line feed, with all function codes the forced return of the head in cause the rest position.

The data at the output of the register 314 are decoded in the decoder 318. If a letter code is recognized by the decoder, it increments a letter counter 310, the content of which CC must not exceed 133 letters per line. If a function code is recognized, the counter 310 is reset to zero.

If at one em ge given time, the buffer register is empty (UKS) and the last read from the buffer register code no radio Lions Code was the content of CC the letter counter 310, which is equal to 0, is stored in a further counter 312 whose "Plus" - The input is connected to the counter 310 and whose "MINUS" input is connected to the output of the buffer register 101; MCC means the value stored in counter 312. At the same time, the counter 310 is reset to zero and the code FCR (forced return of the print head) is applied to the register 314 via a signal generator 402, from where it is fed to the printing logic. (The codes CR and FR are the same, the letter F is only used here to indicate that the control of the return of the head is not generated by an input character, but is generated by the control unit.)

The signal CR is also generated by the generator 402 (an encoder which generates an 8-bit signal code) when the content CC of the counter is equal to IV + 1, where N is the maximum number of letters in a line, about N = 133.

When the OKS signal reappears (ie, when at least one more character has been registered in the buffer register), this character is fed to register 314.

If it is not a function character, the contents of the counter 312 are read.

If the character is other than zero, the push logic receives a number of distance commands equal to the contents of the MCC of counter 312 before the push trigger signal is applied to the push logic.

This arrangement enables a table to be displayed for each desired address in one line. Of the 'Fabulous //' / 'which is stored before the next letter (this is a feature of the signals applied to the general input 14) enables distances that are to be fabulated, from the beginning of the line to the next printed letter can be stored in the unit 312.

When a signal at the output of the buffer register

<liiiuiücilt,

Device 312 and thereby causes the device to be counted down to zero, the counter 312 sending distance signals ESP to register 314, which are applied to the printing logic, causing the head to be displaced along the anvil and no printing takes place. For this purpose, a flip-flop 319 is set to the "1" state by the decoder 318 when the code HT is recognized. If the flip-flop 319 is in the "1" state, it triggers the sequencer 317, which then increments the counter 303, so that the address AD of the tabulation jumps into the buffer register 101 and the flip-flop is reset to zero.

The output sequence control device consists of three bistable devices WL ₁ , // L ₁ and HL _V It can be triggered in eight different states according to the table below.

HL ₃ HL ₂ HL _x State 40 ₀ 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 45 y 0 0 4th 1 0 1 5 1 1 0 6th 1 1 1 7th

Only seven states are used (0, 1, 2, 3, 4, 6 and 7).

It should be mentioned again that the signal SE is applied to the input 14 by an external control device which feeds the printer with the information data; the signal SE is fed together with data information and lasts until the acknowledgment signal ACK from the buffer register to the external control device is registered by the latter.

The first clock pulse after the start of the signal SE triggers the unit 316 from the state 0 to the state (1). State (1) lasts until signal T. triggers you into state (3).

It should be mentioned again that the signal E indicates that no reading takes place at this time. State (3) corresponds to the enrollment time in the buffer register. When the registered mail finishes

is, the ACK signal triggers the unit 316 to state 2.

The time span (W) which is necessary for writing is the sum of the line for the state (1) in which the address is stabilized and the time for the state (3) in which the actual writing process takes place. When the writing process is finished, the OKS signal can appear. The next clock pulse then triggers the sequence control device from state 0 to state (1) or (2), depending on whether a tab was recognized (state 2) or not (state 1). The next clock pulse triggers the device to state (3) in which various functions are performed, as indicated above and as in the flow chart of FIG. 7 is shown.

When a signal Cl is present (i.e. when a book

SiilixMI / .L'lCnL'll UlXl) UICI I Wl) I I) ClI ι ·)!), Uiggcii UcT

The next clock pulse sets the unit 317 to state 7. The confirmation signal PEC from the print logic triggers the unit 317 to go to state 5. The next clock pulse starts the state (4) in which the signal CRF is recognized if it is present.

In order to understand the function of the complete control device, three are selected below Business cases discussed.

I. Operational case

At the moment when the printing is finished, the next .v characters of the text should all be stored in the buffer register 101 (that is, OKS = I during the entire output process, with only the last character corresponding to a function as defined by a Decoder 318 is detected, which is connected to the output of the output register 314).

Upon passage of output sequence control 317 through state 1, the output register becomes 314 loaded with the character to be printed.

In state 3, when / WCC = 0, only the increment formation of the output addressing device 303 alone is carried out. In state 7, the print control signal C1 is sent to the printer via the output sequence control 317, and the character counter 310 is incremented. This state ends when the PEC signal from the output sequence controller 317 has been received. The sequence control moves from state 4 to state 0, with no signal CRF going to the sequence control (which is the case if either the content of the character counter 31O = CC = O or if, in the presence of, OKS CC is different from the number of Characters in the lines.

The sequence control cycle takes place synchronously with the printer and enables ¹ stroke of the characters x— 1.

Since the last character is a function, the 10th cycle of the sequence control in state 7 causes the character counter 310 to be reset to 0 by the output sequence control 317. As soon as the function has been carried out, the sequence control returns to 0 and waits for the next output enable signal OKS.

2. Operational case

Assume that when χ characters have been printed, OKS = O , although the line contains x + y characters, and that only the character χ-hy represents a function.

If the printer has 132 characters per line,

the character counter 310 outputs a signal CRF . which indicates the accelerated return of the print head, either if the counter content is CC = 132 or if, in the absence of OKS, CC is different from 0. For the λ-I characters, the functional sequence is identical to that of the first

ίο case described process.

If for the .v. If the sequence control is running through state 4, the CRF signal is present. The output sequence control 317 is designed so that under these conditions a transition from state 4 to state 6 is achieved win '

In state 6, the code CR (carriage return) reaches the output register 314, and the content CC Vviiu ii'l uciVi iiiifS / .anicr 312 gCSpCiCnCrt.

The fast return of the print head is achieved with the »ο printer during the status 7 and 5 subsequent runs.

In state 4, the signal CRF is no longer present, since CC is now ¹ ^ 0, and consequently the output sequence controller 317 moves to state 0.

After the printhead has come to rest again, the value OKS becomes effective when new characters are entered in the memory register 101, so that spaces are generated by a .t-times transition in state 3 under the condition MCC = / = 0. If this χ If spaces are generated, printing of y characters is carried out as in the first case.

3. Operation case

If we now consider the case of tabulation, where the OKS signal is present throughout the operation, what is most? is the case, the memory register 101 contains the text A to be output and the tab code HT and then the tab address AD and a text B.

The output of the text A is done by the sequence of the output sequence control 317 according to the cycle 0, 1, 3, 7, 5, 4, 0.

When the code HT arrives in register 314, the signal CR is transferred to this register and a tabulator flip-flop 319 is switched. This flip-flop thus stores the code HT and allows the transition of the output sequence control 317 from state 0 to state 2. The output sequence control 317 is set up so that it can remember the tabulator address at this time (RAMz * MCC) and that the output addressing device 303 advances so that the address AD reaches the buffer register 301 and the flip-flop is reset to 0 . As soon as this has happened, the sequence control enables the passage through states 0, 1 and 3.

When passing through state 3, since the code stored in register 314 is not a function code and since the count value MCC is not 0, the counter 312 counts down, so that spaces are taken until MCC becomes 0. This is done by advancing the output sequence control 317 after cycle 0, 1, 3, 7, 5, 4, 0. If MCC = 0, the output of the text B is carried out from the address AD +1 .

When using the control device according to the

Invention can come in handy when the input speed the character is below the maximum speed of the printer, the printing one Line of characters run by the print head

gen executes, which from each other by a return movement of the print head to the beginning of the same Line are separated. With serial printers and especially with mosaic printers there is a

several successive translational movements 5 very wide range of use.

In addition 5 sheets of drawings

Claims (4)

Patent claims: 1. Control device for controlling a serial printer, which has a printing logic with a data input, a constant drive mechanism, an anvil and a print head, which is optionally driven by actuating a clutch that is parallel to the anvil and is automatically brought back to rest position when the clutch is released wherein the control device between the data input and the print logic is inserted, and a register with an associated with the print logic output and having an input for momenta- ¹ S NEN storing a single character as well as a buffer register having an input for the Serieneingab; contains digitally coded characters and an output for serial output of the digitally coded characters to the register, ge ao identified by an addressing device (17, 302, 309) for the buffer register input, each of which indicates the address of the last character given to the buffer register input by a Addressing device (18, 303, as 309) for the buffer register output, which in each case indicates the address of the first character to be forwarded to the buffer register output, by a logical comparator (304, 19, 400, 401), which the buffer register input address with the highest address and with the Buffer register output address constantly compares, by an operation control device (2 {, 316, 317) which, depending on the comparison result of the comparator, enables the input of a character to the input of the register or the transfer of a character to the output thereof, and by a flag device (21 ) to remember the through the printhead in case of coincidences z of the addresses assumed position and for controlling the return of the printhead to the rest position in the event of coincidence and for controlling the rapid movement of the printhead along the anvil until the assumed position is exceeded when new characters are entered after such a coincidence. 2. Control device according to claim 1, characterized in that the input and output addressing device comprises a first and second counter (302, 303) which are each switched by one step when a character is given or outputted to the input. 3. Control device according to claim 1 or 2, characterized in that the memory device comprises a third counter (310) which is advanced by one unit with each character step of the print head, and a fourth counter (312) into which the content of the third Counter is raised when an address match occurs, the content of the fourth counter being reduced by one with each step of a new printhead advance, and that an enabling device is also provided for outputting the first character stored in the buffer register when the content of the fourth memory is zero has become. 4. Control device according to claim 1 to 3, characterized by means (318) for detecting a tab code, by means (319, 310, 312) for incrementing the count of the second counter (303) and for preventing the output of a character until this counter exceeds (Me tab address.