DE2254254A1 - DEVICE FOR DIGITAL PULSE, PULSE AND PERIOD MEASUREMENT - Google Patents

Description

"Device for digital pulse, pulse and period duration measurement" The invention relates to a device for digital pulse, pulse and Period measurement. It is constructed in such a way that it corresponds to its start signal and Stop signal input supplied electrical signals according to the selected measurement type (Pulse, pulse or period duration) processed and at their outputs the for Control of digital counting decades necessary gate time, storage and reset pulses supplies.

When measuring the timing of electrical signals it is necessary, both their periodicity (period duration) and their time intervals between two arbitrarily selectable signal potentials (pulse duration ) to investigate. In the case of non-periodic signals (pulses) or pulse groups, it should also be possible after any pre-selection of signal potential Ue and signal slope dUe / dt to start the time measurement and to do so in an analogous manner stop and only after pressing a so-called "reset button" a new readiness for measurement to manufacture. With every measurement should the one displaying the measurement result Meter reading can be read immediately after the measurement.

Currently it is necessary to measure the period duration and the Pulse duration two separate input channels with the corresponding different types Preamplifiers or two different sub-units or plug-in units (see data sheet FET1, FET2 No. 473600 from Rohde & Schwarz). With the known Procedure "pulse duration measurement, OSNr.

2156? 66 "it is not possible to have the same period duration and pulse duration Measure signal. Also a method described in OS No. 1516316 of the "Prellstörungs- Suppression "is not comparable because of the fixed start and stop gradients, especially since here the possibility of two-channel measurement (i.e. a separate start signal and stop signal input for pulse and pulse duration measurement) is missing. That in 06 No.

1591850 described device for measuring the pulse duration "does not represent any Alternative, since this is a purely analog measuring method, without the possibility of preselecting signal potential and signal slope. Also lies a significant difference compared to the device described in OS No. 2017513 to display impulses in digital form and to classify them "therein, that in this case the same pulse is fed to several comparators at the same time, with Their comparison stresses change here, too a preselection of the signal slope is not possible. So far there is also no institution known that after the measurement has been carried out, the necessary to control counting decades Save and reset pulses in a time-defined and rapid manner generated.

The invention is therefore based on the object of characterizing the three the time sequence of electrical signals necessary quantities impulse, pulse and period duration with any preselection of the signal potentials triggering the measurement and to make signal slopes measurable by a single simple circuit. About that in addition, after each measurement, the necessary to control digital counting decades should Storage pulse and a reset pulse can be generated.

According to the invention, this object was achieved in that 1. the switchover from the measuring arm "pulse duration" to the measuring arm "pulse duration" by a 2-pole switch happens, 2. the measurement of the period duration with MeBart "pulse duration", but not with connected stop signal input, 3. a logical switching mechanism, consisting from 3 flip-flop circuits (1, 2 and 3) and 5 NAND gates t4C6X6,7 and 8) for it ensures that 3.1. in the MeBart "pulse duration" a flip-flop (i) after arrival of the first start pulse selected according to signal potential and signal slope The counting gate opens and then for all further start impulses via a gate (5) at the same time is blocked.

The first stop pulse selected according to signal potential and signal slope reaches a flip-flop (3), closes its output and thus the counting gate and locks itself at the same time for all further incoming stop impulses. Only after When a so-called "reset button" is pressed, the flip-flops (1) and (3) return to their starting position set back and thus a new readiness for measurement established.

3.2. in the MeBart "pulse duration" the selected start pulse the flip-flop (1) clocks so that the counting gate opens until the selected stop pulse the flip-flop (2) clocks, which sends a pulse to the reset input for a short time (50 ns) R of the flip-flop (1) emits and thus the counting gate closes again.

3.3. in the measuring arm "period duration" the flip-flop (1) after each run-in Start pulse inverts its initial state and thus for exactly 1 period Counting gate opens.

4. the memory pulse is generated in that one input of a NAND gate (12) the gate opening impulse directly, the other via an odd number n from inverters (9, 10 and 11) receives: every change of the gate opening pulse from log. "0" to Log. "1" delivers a pulse of log at the output of this NAND gate (12).

1 after log.O whose duration is equal to n times the running time of an inverter is.

5. the reset pulse is generated as in point 4, only in place of the gate opening impulse the memory impulse occurs. With the "Pulse duration" measurement type this reset pulse is blocked or not forwarded by a gate (19).

6. the start and stop signals to the non-inverting input and a freely selectable reference potential to the inverting input of each comparator got. Is the start or

The stop signal with Ue and the reference potential with Ur are at the output of the comparator log. "1" if Ue> Ur and log. "O" if Ue <Ur.

The advantages that can be achieved with this invention are multiple. The most important are: Any preselection of the measurement triggering signal potentials and signal slopes for both the start signal and also for the stop signal input, transition from period duration measurement to pulse duration measurement by switching off the stop signal input, transition from pulse duration measurement to pulse duration measurement through simple switching, through constant generation of the memory and Reset pulse it immediate display of the measurement result after the measurement what is particularly advantageous in connection with automatic measuring systems, cost-effective Construction using only a few simple logic circuits.

An embodiment of the invention is shown in the following drawings and is explained in more detail on the basis of these. The circuit shown in Fig.2 was developed with integrated circuits in TTL logic (i.e. log. "0" - 0 V, log.1,1 "$ +5 V). In principle, other logic families can also be used. 1 shows a block diagram of the entire measuring device and FIG. 2 shows a circuit diagram the "device for digital pulse, pulse and period duration measurement" according to Invention Fig.3a-m timing diagrams for pulse duration measurement Fig.4a-m timing diagrams for pulse duration measurement Fig. 5a-m timing diagrams for period duration measurement To Fig. 1 the signal to be measured either reaches both inputs simultaneously (single-channel Measurement) or there are different signals, their temporal relationship is to be examined, connected to one input each (two-channel measurement ). The input signals are sent to a comparator (12) and (13). With the potentiometers (P1) and (P2) and the switches (52) and (53) can be the signal threshold as required and the signal slope that is current for the measurement can be selected. The start (10) and stop pulses (11) reach a logic switching mechanism (1). This provides one the selected measuring arm corresponding door opening impulse (2), whereby the type of measurement by a changeover switch can be selected (S1). After pulse measurements, you can press the reset button (3) a new readiness for measurement can be established.

The gate opening impulse (2) reaches a so-called counter gate (4), whereby for the duration of the door opening time markers (5) - e.g. from 1 As period duration - in the run in digital counter (6). Its display (7) therefore corresponds to the end of the measurement exactly the duration of the gate opening impulse. Before each new measurement, the counter reading can be reset to "0". This is done by a so-called reset pulse (8). So that not the entire measuring cycle (i.e. reset of the counter reading to "0" - arrival of the time stamp pulses - display of the measured value - reset the meter reading) is displayed, a so-called memory pulse (9) is introduced, whereby the display only changes a maximum of once per measuring cycle. This memory pulse must be between the opening pulse and the reset pulse.

It is true that this basically results in the chronological succession of two Gate opening impulses are limited, but this limit is usually below the resolution the digital counting decade and is therefore meaningless. For example, at Using TTL logic in the circuit according to Figure 2, the storage pulse and reset pulse duration 35 ns each, which corresponds to a minimum success of 70 ns.

However, the minimum time stamp duration is 100 ns and is therefore longer than the measuring period.

According to FIG. 2, the start or stop signal reaches the start signal or. Stop signal input and from there to a comparator (21) or.

(20). At its output this delivers the signal log. "1" if Ue> Ur and log. "0" if Ue <Ur. With the potentiometers (P1) and (P2) are the Comparison voltages can be set separately for each channel.

A downstream gate (B) or (7) and a switch (S3) or

(52) allow the selection of the signal slope dUe / dt C, i.e. if dUe / dt> 0 the signal slope "+", and if dUe / dt <0, this is "-") of the start or stop signal. The switch contact (25) of the switch (S3) reaches the T input of the flip-flop (1), the switching contact (24) of the switch (S2) to the T input of the flip-flop (2).

Up to this point, the start and stop channels are structured identically. in the The following must be distinguished between the control rooms: Note: In the following For descriptions, reference is not made to a 1 1 e timing diagrams every time. Of the better For the sake of understanding, however, all switching states that occur were used for each type of measurement (each Fig. a - m). In the time diagrams, the baseline corresponds the state log. "0". - Overlined characters or words correspond to the inverse signal. (e.g. if R - = log. 1 «, then Q + log." 0 ") 1. MeRart "pulse duration" (See Fig.3a-m) The switches (Sla) and ISlb) are in position "Pulse Duration".

The clock edges for the start and stop pulse are described in the above Way selected. The readiness for measurement is confirmed by pressing the "Reset" key (26) produced. As a result, Q of flip-flop 1) is at logical "0" (FIG. 3d) and Q of flip-flop (3) to logical "1" (Fig.3h). Because of the linkage of Q from flip-flop (1) with mvon flip-flop (3) in gate (6) the gate opening pulse is logically "0" (Fig.3i). The first selected negative edge (clock edge) clocks the flip-flop [1), its Output O jumps to logical "1" so that the counting gate opens (Fig.3i) and the time stamps enter the meter. This signal is still inverted in the gate (5) (Fig.3f) and thus initially blocks the flip-flop (1) via the preparation inputs J and K for all further incoming start impulses. The first selected negative edge of the stop pulse clocks 1.) the flip-flop (2), its output pulse (Fig.3c) because of the current state of flip-flop 1) but has no effect.

2.) the flip-flop (3), whose output (Fig.3h) is at log.

"0" falls and in connection with gate (6) closes the counting gate. A similar locking mechanism to that of the flip-flop (1), i.e. preparation inputs J and K are connected to Q, preventing repeated clocking with stop edges.

If the "Reset" button (26) is pressed [Fig.3e), 1.) The flip-flop (1) is reset via 5 (FIG. 3d) 2.) The flip-flop (3) is unlocked via R 3.) the counter display is reset to d and with it a new one Made to measure. The memory pulse is generated by gates (9), (10), (11) and (12) formed immediately at the end of the gate opening pulse (Fig.3i). There Log. "0" is connected to gate (19) via gate (18), the gate (13), (14), (16). and (16) generated reset pulse is not passed on (Fig.3m).

2. Type of measurement "pulse duration" (see Fig. 4a - m) The switches (S1a) and (S1b) are in the "pulse duration" position.

The clock edges for the start and stop pulse are described in the Way selected. The negative edge of the start pulse (Fig. 4a) clocks the flip-flop (1), whose output Q (Fig.4d) gives the inverted gate opening pulse (Fig.4i). The negative edge of the stop pulse (Fig. 4b) clocks the flip-flop (2). This, switched by gate (4) as a pulse generator, gives for a very short time (»50 ns) a pulse log. "0" (Fig.4c) to the R input of flip-flop (1), whereby its Output Q jumps to logical "1" and thus for the time between the edges of the start and stop pulse emits the gate opening pulse.

The preparation inputs J and K (Fig.4f) of the flip-flop (1) are located log. "1" during this type of measurement. At the end of the door opening impulse, with With the help of gates (9), (10), (11) 2 and (12) the memory pulse (Fig. 4i) is generated. Immediately after the storage pulse, after its rising edge, by means of the gates (13), (14), (15) and (16) generate the reset pulse (Fig.4k). The gate (19) is connected as an inverter during this type of measurement (Fig. 41); it serves together with gate (17) to generate a certain time interval between reset and memory pulse.

3. "Period duration" measurement type (see Fig. 5a - m) The switches (S1a) and (alb) are in the "pulse duration" position during this type of measurement. Will the threshold (clock) of the stop signal outside its amplitude is applied or the stop signal input is not connected, no stop pulse is applied into the rear derailleur (Fig. 5b).

The logic level "1" is therefore applied to R of flip-flop (1) (Fig. Sc) J and K (Fig.5?) And on 3 of this (Fig.5e). So it works as a frequency divider for the start pulse frequency (Fig.5a) and therefore also opens the counting gate for the Duration of two successive clock edges (Fig. Si). The generation and temporal The sequence of store and reset pulses follows the same steps in section 2. described relationships.

Claims: Drawings Fig. 1 - 5

Claims (4)

Claims device for digital pulse, pulse and period duration measurement, which is suitable for direct control of digital counting decades, characterized by that the start signal input with one input and one with a potentiometer (P2) freely selectable comparison voltage (clock) with the other input of a comparator (21) is connected and analogously the stop signal input with one input and one by means of a potentiometer (P1) freely selectable comparison voltage (U?) with the other Input of a comparator (20) is connected to the outputs of the comparators a start or stop pulse is generated, which is sent directly to a with "+" as also via a gate (s) or (7) to a contact of a switch labeled "+" (33) or (S2) arrives, the switching contact (26) of the switch (S3) to the T input of a JK master-slave flip-flop hereinafter referred to as FF for short) (1), the switching contact (24) of the switch (S2) to the T input of one FF (2) and each (3), the preparation inputs J and K of the FF (i) with the output of a NAND gate (5), that of the FF (3) with its Q output and one input of a NAND gate (6) are connected and the other input of this gate 6) with a The input of a gate (s) and the output Q of the FF (1) is connected, the S input of the FF () and the R input of the FF (3) by means of a key (26) to log. "0" placed can be, the Q output of the FFC2) with the input of an inverter (4), whose Output with the R input of this FF and the R input of the FF (i) is connected, a 2-pole changeover switch is attached in such a way that the switch contact (23) of one level (SIe) in switch position §'Pulse duration "with the output of the Gate (6), connected to the Q output of the FF (1) in the "pulse duration" switch position and daR is also in the switching position on the switching contact (22) of the other level (Sib) "Pulse duration" log. "1", in the switch position "Pulse duration" log. "0" and this switch contact (22) is connected to another input of the gate (5), immediately at the end of the gate opening pulse a storage pulse and at the end of this a reset pulse is produced. 2.) Device according to claim 1, characterized in that the storage pulse is generated in that the one input of a NAND gate (12) the gate opening pulse directly, the other one via an odd number of inverters or as an inverter switched NAND gate receives. 3.) Device according to claim 2, characterized in that the reset pulse is generated in that one input of a NAND gate 16) with the memory pulse directly, the other via an odd number of inverters or connected as an inverter Gate is connected. 4.) Device according to claim 3, characterized in that the output of the gate (16) via an inverter (17) to one input, the switching contact (22) of the switch level (S1b) via an inverter (18) to the other input of one NAND gate is connected, which means that at the output of this gate (19) only when measuring "Pulse duration" and "Period duration" a reset pulse is generated.