DE2036412A1 - Circuit for determining the frequency of a counter-frequency modulated transmitter assigned to a markable point in time - Google Patents

Description

Circuit for beat tuning the frequency associated with a markable point in time of a frequency modulatable in opposite directions Transmitter

The invention relates to a circuit for determining the one markable point in time during a frequency sweep associated frequency is a frequency according to an in particular linear time function between two limit values mutually variable, in particular wobble, transmitter with an adjustable Auxiliary voltage with a time-dependent frequency indicating voltage (Wobbeis voltage) is subjected to an amplitude comparison in a comparator.

Known circuits of this type form a comparator pulse as a comparison result, which gives the recorded Frequency curve reproducing display device is supplied as a frequency marker pulse. During the comparator pulse Defines the point in time, the assigned frequency is read off a frequency scale, which is either the frequency marker position on the screen of the display device or the position of the setting element for the auxiliary voltage indicates. However, there are reading errors and inaccuracies here the frequency scale can hardly be avoided.

The invention is based on the object of designing a circuit of the type mentioned at the outset so that the one markable time associated frequency can be determined with greater accuracy, in particular without having to use the pictorial representation of a frequency mark on a frequency curve viewer to help.

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This is achieved according to the invention in that during the outward as well as the return as comparison results generated comparator pulses triggerable, pulse-generating Means for the delivery of a respective gate pulse of a predetermined, in particular adjustable, length cause the one the pulse counter counting the transmission frequency via a gate circuit that is effective for preferably gate impulses of the same length are added to each other in the outward and reverse direction, the resulting counting impulse partial sums ra. where the addition result is evaluated, and that at least one of the comparator pulses is used to mark the point in time.

The main advantage of the invention is that the frequency to be determined is displayed digitally and thus easily readable or can be registered in a simple manner with an automatic measurement run. Due to the adjustability the length of the gate pulse is also the accuracy with which the frequency is to be determined freely selectable according to the respective requirements.

The invention is explained in more detail below with reference to a preferred exemplary embodiment shown in the drawing. It shows
1 shows a basic circuit of the invention applied to a measuring station for frequency-dependent measurement

of four-pole transmission properties, Fig.2 a preferred embodiment of a sub-circuit of

Fig. 1 and
3 voltage-time diagrams for a more detailed explanation of the circuit according to FIG.

In Figure 1, a continuously frequency-modulatable, in particular wobble, transmitter 1 is shown, at the frequency control input 2 is a frequency control voltage U ₀ , which is from

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a generator 3 is generated. In the illustrated embodiment, U has a time-linear, triangular course and has a periodic time dependency in the event of a wobble of the transmitter 1. At the same time, U is also fed to the first input of a comparator 4, the second input of which is connected to an adjustable DC voltage U ₁ . An amplitude comparison between U and U ₁ carried out in FIG. 4 results in a comparator pulse 5 which is fed to a triggerable, pulse-generating circuit 6 when a certain amplitude ratio is present, for example when the amplitudes are equal. After the arrival of the comparator pulse 5, this forms a rectangular gate pulse 7 »which is fed to the upper input of a gate circuit 8. The latter, implemented as a NAND gate in the illustrated embodiment, is opened for the duration of the gate pulse 7, so that voltage pulses of the alternating voltage U emitted by the transmitter 1, which fall during the opening time and have a uniform polarity, are counted in a pulse counter 9. Since comparator pulses 7 and 7 'of equal length are obtained both for the forward and for the reverse of the frequency, ie for the rising edge and for the falling edge of U ₃ , the pulse counter 9 forms two counting pulse sub-units that must be added together. The sum of the two is then evaluated as the counting result.

At least one of the comparator pulses 5 is, if necessary after appropriate amplification and / or pulse shaping, output via a line 10 and marks the point in time the frequency f of the transmitter 1 which can be seen from the counting result of the pulse counter 9 is assigned.

If the circuit part described above is supplemented by the ones indicated on the right-hand side of the terminals 12 to 14 Circuit units, this creates a measuring station for frequency

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dependent measurement of the transmission properties of a quadrupole X, the input of which is connected to terminal 12. The four-pole output 15 is followed by a measuring amplifier 16 and a measuring rectifier 17, the output voltage of which is fed at 18 to one deflection device of a viewing or recording device 19, for example a slectron beam oscilloscope 20. At the same time, the frequency control voltage U _{o is} communicated via the terminal 21 of the other deflection device of 19 as a time deflection voltage.

Depending on the changing frequency of the transmitter 1, which is recorded over the time base of the device 19, This results in a graphic representation 22 of the curve profile of the measurement voltage tapped at the four-pole output 15, which e.g. represents a measure for the four-pole attenuation. The pulse 5 is fed to the frequency mark input 23 and causes a frequency mark to be formed in a manner known per se, e.g. in the form of an additional deflection 24 of the electron beam in the vertical direction or in the form of a brightness control of one of the curve points.

Instead of the device 19, an evaluation device 25 can also be connected to the terminals 18 and 23 via the terminals 18 'and 23'. This contains a gate circuit 26 and an evaluation device (digital voltmeter) 27. The pulse 5 causes the gate circuit 26 to open briefly, so that a measured voltage value at 18 is scanned and preferably digitally evaluated in 27 chin, Bs consists e.g. . the possibility of the resulting digital measurement result in 27 to face the measuring frequency indicative of counting of the pulse counter. 9

In Fig _. 2, a preferred embodiment of the triggerable pulse-generating means 6 is shown in detail, this using building blocks of the logical

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Circuit technology are built. The comparator pulse 5 supplied by 4 is fed to the first input of an OR gate 28, the output of which is connected to the counting input 29 of a binary divider stage 30. The output Q of 30 », which is in the state« O * after the arrival of a release pulse R, is connected on the one hand to the first input of a NAMB-ßatters 31, the second input of which is normal frequency pulses XS ^ with the frequency f ', and on the other hand with input J of a JK flip-loop 32, which switches the logic information present at input J through to output Q when a clock pulse arrives at input Cl. Output $ of binary filing stage 30 is connected to input K of 32 .

As can be seen from Pig.2, the clock pulses for 32 are derived from the standard frequency pulses U ". The output Q of 32 is connected to one input of a NAND gate »θ, the output of which is led to the input of the expediently decadic pulse counter 9. At the second input of 8 is the output voltage u * _{v of the} transmitter 1, the instantaneous _{frequency ί χ of} which is to be determined at the point in time marked by the comparator pulse 5 within the frequency sweep. The output of the NAND gate 31 is connected to the input of a second, preferably decadic counter 33, which counts the normal frequency pulses Ujj. The output of a selectable counter stage, for example 35, is applied to the second input of the OR gate 28 via a changeover switch 34-.

In addition, a JK flip-flop 36 is provided, the input J of which is assigned via a terminal 37 of a logical ^H T ^M during the frequency run-down, but with "0" during the frequency runback. For this purpose, 37 is connected to the frequency control voltage IJ via a differentiating stage 3a.

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switched. The input K of 36 is connected to ground, while the clock input Cl is connected to the output Q of 32. The Q output of 36 is connected to the first input a NAND gate 38 whose second input is also connected to the output Q of 32 iat. Of the The output of 38 is via a negation stage 39 to the clock input Gl of another JK flip-flop 40 switched, its Input J is fed to terminal 37 via a negation stage 41, while input K is connected to ground. The output Q of 40 is to a terminal 4? led over an evaluation signal U is fed to the counter 9.

The operation of the subcircuit according to FIG. 2 is explained in more detail below with the aid of the voltage-time diagrams according to FIG. 3: FIG. 3a shows the normal frequency pulses Ujj and FIG U ₁ · At time t ₁ , that is, when U and U .. have equal amplitudes, a comparator pulse 5 (FIG and whose output Q is set to "1 ¹¹ , while the complementary output ÖT changes from" 1 "to" O ". As long as an ^H 1" is present at output Q of 30, the NAND gate 31 remains for the normal frequency pulses ü "(Pig .3a) open. These run into the pulse counter 33 and are preferably counted there in decadic form. The counter output 35 selected by means of the switch 34 becomes an output signal

U received after a time allocated to the output, desa

sen positive edge PF is fed via 28 to input 29 as a further counting pulse. This switches output Q from 30 to "0" again, while Q goes to state "1". As a result, the NAND gate 31 is blocked for υ «and the counting process in 33 is thus completed.

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The start of the counting process in 33 is correspondingly
the output states of 30 at input J of JK flip-flop 32 a "1" and at input K a "0". Based on this
leads the next negative plank of U ^ (NFN in
3a), which is fed to the input Cl of 32, for transferring the "1" from J to Q. This opens the NAND gate 8 over its lower input for the incoming oscillations of the transmitter voltage U, which are then counted in 9 will. With the completion of the counting process in 33, which is indicated by the
Is effected, the "1" from the input J of the stage 32 is switched off and replaced by the "0", o that when the next negative edge of Ujj occurs, the output Q changes to the state "0". In order to
8 is blocked for U, which means that the counting process in 9
is completed. The output shown in Fig.3d
voltage of 32, which only has the value "1" during a period specified by the selected output 35,
thus corresponds to the gate pulse 7 in Fig.1.

During the frequency trace, ie during the rising edge of the voltage U, a logic "1" is present
the input J of the stage 36, while at the same time via the
Negation stage 41, the signal ¹¹ O "is fed to input J of stage 40. If a gate pulse 7 now occurs on the output side" from 32, its negative edge is transmitted via the input.
franr Gl of 36 is used to transfer the "1" from J to Q. This will make the NAND gate 38 over his
upper input wired with a logical "1". However, since the gate pulse 7 is also fed to the lower input of this gate at the same time, its lower input is switched to "0" at the same time, so that at the output of 38 the
State "1" remains unchanged. Via the negation stage 39, a “0” is thus passed on to the input Gl of 40 during the entire outward run. As a result, there is no signal U "

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on that your counter 9 could be fed as an evaluation signal. So this shows that during the frequency trace generated partial result is not displayed.

During the frequency reversal, the process of counting the normal frequency pulses U _n and the associated counting of the voltage pulses from U is repeated in the manner already described, with the start of counting being prepared again by a comparator pulse 5 '(Figure 3e), which, if U. and U ₁ arises. After the start of counting in 33 causes the next following negative edge of U _n, the 'denotes the transfer of the appended with J ^M 1 ^M to the Q output of the stage 32, whereby a further gate pulse 7' in Figure 3a with NFN (Fig.3f), the length of which, like the length of 7, depends on the position of the switch 34. If this position is not changed between the outward and return movement, gate pulses 7 and 7 of the same length are created.

The trailing edge of 7 ¹ transfers the logic "O" from input J of 36 to output Q, since it is fed to clock pulse input 01 of 36. Thus both will. At this point in time, the inputs of the gate circuit 38 are transferred from the state "1" to "O", which results in an output-side switching from "0" to "1 ^M. The stage 39 inverts this process, so that at the clock pulse input Cl of 40 a negative pulse edge arises, which transfers the "1" present at J during the frequency decrease to Q and thus supplies an evaluation signal U_ to the counter 9 'via terminal 42.

t Z

U ₂ causes the counter 9 to display or output the counter result, for example by means of a lighting control of the display tubes (Nixi tubes) assigned to the individual counter stages or by transferring the counter result to a connected memory 9a (FIG. 1)

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The use of a memory in wobble operation has the advantage that even with the marking of a point in time shortly after the start of the frequency sweep, no time that is too great There are time intervals between the individual counting result displays, in the case of a memoryless lighting control could lead to an annoying flashing process, especially at a low wobble frequency.

Is after completion of the entire counting process completed "of the effect of the evaluation signal U _n, is derived preferably from one of the sub-circuit 6 zugeführten.Spannung, including U-, an erase pulse R, the step-the counter _Ä 9 and 33 and the subcircuits 30, 32, 36 and ^ 40 is supplied and this switches back to the idle state. This prepares the circuit for the next counting process. ;

In the method of determining each of the two time bases 7 and 7 'for the counter 9 by a second counter 33 into which a normal frequency f «is counted, the resulting error is a maximum of a period of Ujj. Furthermore, the addition of the two partial sums obtained during the frequency back and forth, assuming gate pulses 7 and 7 »of the same length and a constant frequency change rate of U _y for the outward and m return, causes a further error in the allocation of the counter result of 9 the point in time marked by 5 or, 5 ' , which corresponds to a maximum of half a period of U ^. This error is due to the fact that the time interval between the pulse 5 and the beginning of the gate pulse 7 can vary by a maximum period of U «compared to the time interval between 5 'and the beginning of 7'. The maximum error occurring when assigning the counted frequency to the marked point in time t- under the stated conditions is therefore half a period of

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ORIGiNAL INSPECTED

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Ίο

υ «as a result of the different duration of the time bases and in addition a further half period duration as a result of the different time intervals mentioned and can
by a sufficiently high value of f «, e.g. 1 MHs,
can be kept correspondingly small.

6 claims
3 figures

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INSPECTED

Claims (1)

Claims Circuit for determining the frequency associated with a markable point in time within a frequency sweep of a transmitter with an adjustable auxiliary voltage that can be changed in opposite directions, in particular wobble, in its frequency according to an in particular linear time function between two limit values,
those with a time-dependent frequency indicating
Voltage (wobble voltage) in a comparator one
Amplitude comparison is subjected, thereby
^{characterized in that comparator pulses (5> 5!} ) formed as comparison results during the outward and return travel can be triggered, pulse-generating
Means (6) for outputting a gate pulse (7, 7 ¹ ) of predetermined, in particular adjustable, length cause the pulse counter (9) counting the transmission frequency (f) via a gate circuit (8) so that the pulse counter (8) is activated for preferably the same length Gate pulses (7 »7 ') are added to each other resulting counting pulse partial sums during the outward and return movement, the result of the addition being evaluated and that at least one of the comparator pulses (5, 5 ^f ) serves to mark the point in time (t-). Circuit according to Claim 1, characterized in that each comparator pulse (5 »5 ')
the opening of a second gate circuit (31) assigned to a second counter (33) causes the preferably stabilized normal frequency pulses (U «) to be counted in so that the second counter (33) uses a preferably selectable output (35) to generate a divided normal frequency in the form of a Emits square-wave voltage (U_), one edge (PF) of which causes the blocking of the wide gate circuit (31), and a signal weL - VPA 9 / BATH ORIGINAL ches defines the opening time of the second torso posture (31), the gate pulse (7, 7 ') for the gate circuit (8) connected upstream of the pulse counter (9) can be derived. 3. A circuit according to claim 2, characterized e i without t that the signal defining the opening time of the second gate circuit (31) via the output (Q) a binary divider stage (30) is obtained, which the comparator pulse (5, 5 ') and which effect the blocking Edge (PP) of the square-wave voltage (U) as counting pulses are fed. 4. Circuit according to one of Claims 2 or 3, characterized in that the signal defining the opening time of the second gate circuit (31) can be fed to the input (J) of a flip-flop (32) whose clock input (01) carries the normal frequency pulses (U ^) is applied so that the applied signal information is switched through when the next following edge (NiFK, NFN ¹ ) of the standard frequency pulses (U «) occurs, which edge has a predetermined polarity. 5. Circuit according to one of the preceding claims, marked g by applying it to a measuring station for the frequency-dependent measurement of four-pole transmission properties, wherein the output voltage (U) of the frequency-modulable transmitter (1) after passing through a test object (X) a downstream viewing or recording device 09), in particular an electron beam oscilloscope (20), which can be supplied as measuring voltage, is the pulse used to mark the point in time (t.) (5, 5 ') is communicated to the frequency mark input (23) of the device and indicating the frequency variation Voltage (U) preferably that for the time base voltage s provided device input (21) applied. VPA 9/443 / 24b -13- 109885/0928 6. Circuit according to one of claims 1 to 4, marked g by applying it to a measuring station for the frequency-dependent measurement of four-pole transmission properties, with the output voltage (U) of the frequency modulatable transmitter (1) after passing through a test object (X) over a Gate circuit (26) can be fed to an in particular digital evaluation device (27) as a measuring voltage and is used for Marking the time (t ^, tp) serving pulse (5, 11) is used to briefly open the gate circuit (26). VPA 9/443 / 24b 10988S / 0S28