DE2244598A1 - PROCESS FOR OBTAINING ERROR ANALYSIS DATA ON THE BASIS OF UNITS, REPLACABLE, ADJUSTABLE OR REPAIRABLE IN A SYSTEM - Google Patents

Description

Boeblingen, August 31, 1972 mo-ba

Applicant: IBM Deutschland GmbH

7000 Stuttgart 80 Pascalstr. 100

Official file number: New registration File number of the applicant: GE 972 021

Process for obtaining error analysis data on the basis of replaceable, adjustable or repairable in a system

ren units

In the development of electronic data processing systems, the reliability and availability of the systems are becoming increasingly important. This is due to the demands of the user with regard to availability and reliability and the demands of the manufacturer with regard to the shortest possible repair times.
Basically, two influencing factors determine the result:

1. the reliability of the components;

2. the duration of the repair time

The repair time depends on the length of the error analysis time certainly. Therefore, considerable efforts are made / to reduce the analysis time. Particularly aggravating however, there is the fact that most errors occur sporadically or intermittently. In general, there are Divide errors into intermittent errors on the one hand and fixed errors on the other. Fixed errors become such Understand errors that do not occur temporarily but continuously and usually require immediate intervention by the maintenance service

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personnel in the sense of replacing the defective assembly require.

The invention is concerned with measures for Determination of the fault location of temporary or intermittent faults. Such intermittent errors - they make over the Half of all errors off - can be "covered over" to a large extent by the system itself or by measures taken by the operating personnel so that when they occur there is no final machine stop is associated with the need for immediate repair. The following measures are usually available for continued operation (recovery) of the data processing system despite an intermittent error that has occurred: and corrective circuits or programs or measures to be initiated by the operating personnel, e.g. a restart or the start of a program point that was a little back in the past and has been error-free up to that point. Although in these cases with the Data processing system the task once posed can ultimately be solved as if no error had occurred, it is However, known to record the fact of the error occurrence in e.g. printed error logs, so that within the framework of the usual maintenance in the event of an accumulation of detected errors, possibly necessary repair work carried out can be. For example, in a computer equipped with its own error detection and correction facility, it is known that Frequency of the occurrences of errors (corrected automatically by the system) to count over certain time intervals and to exceed them to issue a warning of a limit value (IBM Technical Disclosure Bulletin, Vol. 12, No. 6.6. Nov. 1969, Page 895).

The known methods therefore only consist in "collecting" such error data at the time of their occurrence, with in retrospect, an attempt is made to draw conclusions (error analysis) from the collected data about the error location. According to determination the faulty assembly (component) is replaced, adjusted or repaired at the location of the fault. The conclusion (analysis) on

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the location of the fault is also often fully or partially automated in order to carry out the analysis faster and more reliably. The great However, the problem with these analyzes is the reliability of the analysis result. This result is highly dependent the degree of the possibility of drawing conclusions from the error data collected on the fault location, since identical fault data constellations can be caused by different assemblies. However, the likelihood of the defect data belonging to certain assemblies is mostly dependent on the quantity the components involved in a specific function. Accordingly, the maintenance technician has already been given so-called Priority lists were given, which indicated which exchangeable assembly should be used if a type of error was detected should be replaced first. In other words, these priority lists contain information about which assembly at is particularly "suspicious" for a particular bug.

However, these known measures have the disadvantage that the causes of errors in relatively "unsuspicious" assemblies are practically ignored. The error data collected relate only to the specific error type _r as it ultimately occurs, and not to the proportions of the assemblies that may be causing the error.

The object of the invention is to provide a method for obtaining of error analysis data in the case of intermittent errors, which means that detailed consideration is also less frequent appearing and i.a. less expected causes of errors and thus the time to determine the Error location and their reliability improved.

In a method of the type mentioned in the opening paragraph, the invention consists in that when an intermittent Error the assemblies that are eligible for this type of error in the ratio of their probability determined Proportion of the respective type of error, error points are assigned

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that are totaled for the individual assemblies. If an error occurs in the system, no more edits are made Defect data as such "collected", but instead assigned defect points to the assemblies that are eligible for this type of defect, relatively "unsuspecting" circuit parts are also taken into account according to their respective proportion. The number of failure points for each "involved" assembly depends on the percentage probability belonging to the "error area". For each error that occurs, a certain total error score is awarded, the is distributed to the individual modules or the errors assigned to the modules. Caused by the intermittent Most errors are characterized by a statistical distribution of points, which is much more detailed than is previously designed. At the time of the error analysis, the modules "burdened" with error points are sorted according to the The amount of their total error points. In this way, the assembly with the highest can be determined very precisely Probability caused the failure.

Further details, features and advantageous refinements of the invention are given in the following description of an exemplary embodiment as well as in the subclaims.

In Fig. 1 the are functionally connected to one another schematically standing assemblies 1 to 8 are shown. These assemblies 1 to 8 represent the interchangeable, adjustable or repairable units and can, for example, individual semiconductor wafers (chips) with it integrated circuits, so-called modules with several semiconductor wafers built into them, circuit cards with several modules or the like. In Fig. 1, 4 possible error areas A, B, C and D are also shown. Errors in an error area, e.g. A, lead to the same "error image" regardless of the module. From Fig. one recognizes, for example, the different for the error area A.

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percentages of the assemblies for this defect area. In the embodiment shown, for each occurring Error 100 error points awarded according to 100%. The points allocated when an error occurs are in each added to a counter per module. For the error range A it follows from Fig. 1:

Assembly share of the defect area A Defect points

1 30% 30

2 10% 10

3 20% 20

4 40% '40 '

The percentage shares of the individual assemblies 1 to 8 in the possible error areas can easily be determined from the circuit structure of the respective assemblies. For example it is seen that at the fault region A, only the modules 1, 2, 3 and 4 are involved _/ but not, for example, the module 8. These relationships result in each case from the circuit function of the modules and are predetermined. The percentage share of an assembly in a defect area can expediently be determined depending on the number of components of the assembly involved. However, it is also possible, instead of or in connection with this, to take into account the types of components in the individual assemblies because, for example, it is known that certain types of components are particularly prone to errors.

The basic evaluation procedure is shown in FIG. 2 of an error that has occurred. A specific error that occurs is characterized by a so-called error pattern. This error image information FB (error address) is fed to an error image decoder 10. The error image decoder 10 sets from this input information the counters Z1 to Z8 to be loaded with error points corresponding to the modules 1 involved

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to 8 fixed. The level of the load on the individual assemblies with fault points takes place via the fault point control 11. The Fault point signals are generated in the fault point generator 12 and under the influence of the fault point controller 11 on the Assemblies 1 to 8 assigned error point counters Zl to Zε passed.

Because for each error that occurs, not just one Error information is collected, but proportions of the total number of error points according to the participation of the various assemblies are assigned, the result is a much more precise picture of the individual possible error locations. In particular The error contributions of relatively unsuspicious assemblies can also occur according to their share in the error status be held. As a result of the repeated allocation of fault points, an unsuspicious circuit can can be recognized in the event of frequent involvement of errors.

It can be useful in some cases, but not for every type of error to award the same total number of error points, but rather the type or severity of the total number of error points Error to be taken into account. When awarding error points, it can and should also be considered find that, within the framework of an error pattern, certain errors belong to a family of errors and, for example, consequential errors are one of the main ones causative error are. Such defect family or defect pattern properties are also in the circuit function justified and can be predetermined from it. Here, too, the method according to the invention offers the advantage of eliminating consequential errors not to be completely disregarded, but to be taken into account in the sense of a corresponding reduction in the error point rate, because it cannot be ruled out that these errors actually occurred independently.

As has already been mentioned, the inventive Procedure the determination and evaluation of during normal

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Operating mode of the system encountered errors. With this, however, the system continuously delivers the error information required for subsequent maintenance. However, it may also be appropriate, instead of or in conjunction so that such error occurrences can be used as error information to be evaluated that is due to special test processes were determined during work cycles of the assemblies involved that are not used otherwise.

Finally, it should be noted that the method described is not applicable to the application of fault location determination in a data processing system is limited. It offers the above-mentioned advantages in general with interchangeable of several, but functional connected assemblies in existing systems in which intermittent errors occur. Such systems must be included also by no means be exclusively electrical in nature.

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Claims (12)

- 8 PATENT CLAIMS Method for obtaining error analysis data on the basis of interchangeable, adjustable or in a system repairable units, characterized in that when an intermittent fault occurs, the for this type of defect in questionable assemblies in the ratio of their percentage determined according to the probability Error points are assigned to the respective error type, which are added up for the individual assemblies. 2. The method according to claim 1, characterized in that the assemblies for error analysis or error location determination placed in a sequence according to their load with fault points and according to the one created in this way Priority order of troubleshooting, e.g. repair, adjustment or replacement measures can be carried out. 3. The method according to claims 1 or 2, characterized in that that for several functionally related assemblies, the respective relative error proportion is specified for a relevant type of error or an error range. 4.. Method according to one of the preceding claims, characterized characterized in that the determination of the proportion of errors of a certain assembly in one of several assembly functions dependent error type taking into account the number of components of the individual assemblies. 5. The method according to any one of the preceding claims, characterized characterized in that the determination of the proportion of errors of a certain assembly in one of several assembly functions dependent error type taking into account the component types in the individual assemblies. 409812/0649 GE 972 021 224A598 6. The method according to any one of the preceding claims, characterized characterized that .as an assembly unit with its own accumulation of error points a coherent integrated Semiconductor circuit board / a so-called module with several semiconductor circuit boards built into it, a circuit card or the like. Is selected. 7. The method according to any one of the preceding claims, characterized in that for each occurring error in total a certain number of failure points is assigned, which is distributed to the individual assemblies involved and summed up for each of these assemblies. 8. The method according to any one of claims 1 to 6, characterized in that that depending on the type or severity of an error that occurs, a different total error score is awarded. 9. The method according to any one of the preceding claims, characterized characterized in that in the module-based allocation of fault points for a type of fault from the circuit context necessary or likely resulting consequential error or error family properties in the sense a reduction in the error point guote consideration Find. 10. The method according to any one of the preceding claims, characterized in that in the course of normal operation of the system, e.g. a computer, errors that occur and have been corrected by the system or the operator can be used as error data to be evaluated. 11. The method according to any one of the preceding claims, characterized in that such error occurrences as to be evaluated Defect data are used which, due to special test procedures, during work that is not used otherwise ■ 409 8-12 / 0649 GE 972 021 22U598 - 10 cycles can be determined. 12. The method according to any one of the preceding claims, characterized in that each to a certain type of error associated error image information is fed to an error image decoder which, together with an error point control and a fault point generator, the loading of the respectively involved assemblies with correspondingly proportional Controls error points for advancing the error point counter assigned to the individual assemblies. 409812/0649 GE 972 021