DE2219014C3 - Circuit arrangement for multiple checking circuits in telecommunications switching systems, in particular telephone switching systems - Google Patents

Description

• ^ starting with individual tests, but with par-stams continued testing process, with the largest

η cSwindiokeit starting! but continued with the small ^ n ¹ speed, with the result of each SuMaß under Single Check-draining,

Senenfails also a beginning under individual tests? and shorter under Parallel Check continued Verzögeiungsvorgang the other hand, an expiring under Parallel Check deceleration operation longer than the test period lasts As a result, for a first test of two with temporal overlap Aufprüf-chaltung the individual means causes aufzuprüfen to the central Aufprüfschaltung this purpose, via the input E in F i g. 1 initially shown a ground pulse on the circuit arrangement emitted. The capacitor C 2 is charged by this pulse. It consists of the following circuit:

R ₅
Zl A

Zl, A3, 7Ί

alfdeSeSSnÄ to lead success. The temporal priority of the er-SdeTufprüfcircuits, which is still within the small-Sgsaät (smallest reaction time of the sSS), does not remain so, but rather has the effect that the whole of the first test circuit is essentially the response time of the second test

ghed in

thus pursues the goal of a time ^v _Af f _{ii {haUunee i} Dependent

1) trde, h,

As soon as the capacitor C 2 hits the J

voltage between the operating voltage and

voltage of the Zener diode Z is running, w.d the

via this Zener diode and the emitter-Bas.s-path

of the transistor T 1 running branch of the circuit

ses 1 de-energized. After the end of the earth impulse

The capacitor Cl is via the input E

the resistors R 4 and R 5 are discharged.

In the period of time during which ubei-die_Em.t-

SSHSSSäSS

, 5 of the circuit arrangement shown in Fig. 1 wrd thus the earth impulse supplied via input £ is shortened. Due to a repeated implementation in

Check the organ and, if it is determined that it is free, keep the ⁸ test circuit and block zuge.ch against further attempts to connect by other checking devices. The blocking is set as a result of a positive test process, i.e. at the end of the same, test multiple circuits, on the other hand, work according to the previously known principle that testing and blocking start at the same time. In the manner already indicated, in known arrangements, this has the effect that no two devices, which simultaneously or only partially simultaneously seek and prove the common organ via its self-locking test, cannot check. This adverse effect is largely eliminated by the invention.

In the drawings Fig. I and 2 is an Ausdngsbeispiel of the invention shown, whereupon s, e, e-

^^^ iÄL and so ^ ^them
50 years of age

and
55 well
was standing

^Pu "^; ^2nd _single test circuit after

^ S'f ach circuit according to F i g. 2, r _{Djode ß2 and den}

_{Do series saddle} i g of resistance _The ^ _{characterized a} _

_{at the} ^g _point P 1 is consequently through

_{the wide} residues R 6 in FIG. 1 erte _{2 determined if}

uno » _{about the cons} .

? »P switches on. The partial span distance R ^ brop _{between the resistance changes}

" ^un & ^am / ^e ^ ^m _R2 } ^V _{nm so much} more positive that the £ _with fJVs * _S t7ect of the transistor Γ21 currentf ^^ · ^ _VeBUchen two test videos according to Fig. 1 at the same time, on the _t i"" _{according to} ^B. _F ig aufzuprüfen 2 so Α ⁸ transistor Til

"SS

S ^ sÄung now returns to the circuit

Order according to fig. 1 back. First, consider the case that a single Aufprüf circuit of FIG. 1 tries to check the common on test circuit of FIG. As already stated, reaches at connection of a Erdimpulses longer duration via the input E g a shortened Erdimpuls via the collector Tl to the diode D 2 and this on the Prüfvielfachschaltung by Fi. 2. This earth pulse also reaches the resistor R 7 connected to the resistor R 8 and the capacitor C 3 connected in parallel with it. Since in this case the transistor Γ 22 of the test multiple circuit according to FIG the resistors R 27 and R 28 and a current through the resistor R 9. There is a voltage divider on the one hand from the resistor J? 7 and on the other hand from a parallel connection of the resistor R 8 with the resistor R 9 connected in series with the resistors R 27 and R 28 connected in parallel. The capacitor C 3 connected in parallel with the resistor R 7 is charged. The partial voltage increases at the connection point between the resistors RT, Ri, R9 and RIO, starting at ground potential in the negative direction. As soon as the voltage of the capacitor C 3 exceeds the value of the Zener voltage of the Zener diode Zl , a current flows through the emitter-base path of the transistor Γ 3. The ground potential supplied via the collector of transistor Γ 2 reaches the base of transistor TS via the emitter-collector path of transistor Γ 3 and resistor R12. As a result, this transistor also becomes current-permeable and switches on the voltage divider formed from resistors R14 and RIS. The partial voltage generated by it is applied to the base of the transistor T 4. As a result, the earth potential applied via the contact ab reaches the emitter of transistor Γ 3 and diode D 2 via diode D 4. Via transistor Γ 4, the relay PU in series with resistor R18 is also switched on, which responds and switches through caused the desired connection in a manner not shown in detail.

The shortening of the earth pulse received via the input E with the aid of the described charging of the capacitor Cl and the Zener diode Zl is decisive for the test duration specified for the test circuit according to FIG. It is therefore suitable for the various test circuits according to FIG. 1 uniformly limited.

Now tests a single test circuit according to FIG. 1 in the manner described. 1 to a test multiple circuit according to Fig. 2, then the delay period determined by the capacitor C3 and the voltage divider resistors Rl, R8, R9, R27 and R 28 from the beginning of the limited test period until the transistor Γ4 is turned on is less than the limited test period, that is, the transistor Γ 4 is turned on before the transistor Γ2 is blocked again. The transistor T3 is kept in the switched-on state via the transistor Γ 4, and the common test multiple circuit according to FIG. 2 remains blocked until contact is opened in FIG. 2 the idle state is brought about again. It can now happen that two different checking circuits according to FIG. 1 to the test multiple circuit according to FIG. 2 try to check. In this case, earth potential is switched on in parallel via two resistors R 6 and at the input P1 of the test multiple circuit according to FIG. 2 effective. As a result, the potential at the base of the transistor Γ 21 is shifted so far in the positive direction that its emitter-base path is de-energized. As a result, the transistor Γ 22 is blocked. In both of the test circuits of FIG. 1, the resistor R9 is de-energized.

ίο The capacitor Γ 3 connected in parallel with the resistor R 7 is only charged via the resistor R 8. The time constant is greater in this charging process. In addition, the voltage divider ratio determined in this case solely by the resistors R 7 and R 8 is different than when a single test circuit is tested individually. In this case, the capacitor Ci is charged to a low final voltage value. Due to the fact that in this case the parallel testing of two reports

ao test circuits larger time constant for the charging process of the capacitor C 3 as well as due to the charging of the capacitor C 3 the lower partial voltage, the capacitor can only be used at a much later time.

point reach the voltage value that corresponds to the Zener voltage of the Zener diode Zl. In this case the decisive determined by the capacitor C 3 and the voltage dividing resistors R 7 and R 8 delay period is greater than the uniform limited test period determined by the capacitor Cl and Zener diode Zl. At the end of this test period, the transistor Tl is blocked again and the charging process of the capacitor C 3 is prematurely terminated. The capacitor is discharged through the resistor R 7. The transistors 3, Γ 4 and Γ 5 are not turned on in this case. The relay PU does not respond either. So check two Aufprüfschalrungen according to Fig. 1 at the same time, so the PU test relays cannot respond in both.

Then consider the case that two test operations of two test circuits according to Fi g. 1 start one after the other within the uniformly limited test duration. In addition, assume

men that even before the transistor is turned on Γ4 in the first of these two test circuits, the test procedure for the second test circuit begins. The test process of the second test circuit is made possible by the voltage divider

resistors R 7 and R 8 predetermined, determined previously described larger delay period. The second test circuit comes to a negative result, that is, your relay PÜ can not respond in the end. The through is remarkable

the capacitor C 3 determined delay process in the first of the two check circuits Before the start of the test process of the second Aufpruf circuit, the delay process has the dei smaller delay time corresponding large

Running speed on. After the start of the test procedure for the second test circuit, the Ver delay process in the first verification circuit] determined by the corresponding smaller running speed corresponding to the greater delay period. De

Delaying process in the first verification circuit: is thus successively due to two different Ab Running speeds determined, first by the larger and after the start of the test

ges of the second check-up circuit due to the lower processing speed.

After the start of the checking process of the second checking circuit, the charging process of the capacitor C 3 is continued. If the capacitor voltage reaches the value of the Zener voltage of the Zener diode Z 2 before the end of the uniformly limited test duration of the first test circuit, the transistors T 3, T5 and TA

controlled and the relay PU activated .

It should also be mentioned that it is useful to add a resistor to the emitter-base path of the transistor Tl to connect in parallel. This ensures that the Zener diode can safely reach the Zener voltage Zl required minimum current guaranteed and thus the temporal spread of the uniformly limited Test duration reduced.

1 sheet of drawings

$ 09637/173

Claims (3)

the preference of one over the other Claims: test circuit prevents an actually free audited body only not due to parallel examinations I. Circuit arrangement for with a self- can be occupied. This principle is used when testing Blocking test multiple cooperating on- 5 of organs applied to the test process Test circuits with uniformly limited test- several equal rights to establish the connection permanent in telecommunication switching systems Telephone exchanges, thereby dials and is then occupied for a long time. One characterized in that the Aufprüfschaltim- repetition of test processes on the part of a test with a test at the beginning of the test process and with regard to one and the same, thus the delaying organ started early would be uneconomical in this case are equipped, which only with a voühch. - Circuit arrangements of this type are through «The German exhibition shops 1 030 885, 1 170 476, which run continuously within the test period, »Elimination process a positive test result from 1 242273 and 2047 878 known, there, and its delay process in single 15 In circuit arrangements according to the second of check at greater speed, at the same time, the two principles mentioned above are used for checking at a slower speed and with the facilities only a single common too an organ that begins with individual examinations but can be reached with an examining body. In this case, at Parallel testing continued test process, with the occupation of the examined organ the test process like this starting at greater speed, but repeated at the ao for a long time until it yields a positive result continued at a slower rate, with which leads If the common organ to be examined is occupied, Result expires that everyone under individual testing so the testing facility repeats the test procedure and possibly also a downfall until the common organ is free again Individual testing is beginning and under parallel testing. This procedure is used when If the continued delay process is shorter, it is the common organ to be examined a switching device that is always only delay process longer than the test duration is briefly occupied (e.g. corrector). In the case of parallel 2. Circuit arrangement according to claim 1, there is no check of two test circuits characterized in that the delay time train. Because of the short occupancy times member of a series connection of a condenser 30 of the common organ is a repetition of the tors with at least one resistor and one test in the parallel test case is economical and useful the capacitor voltage controlled noise. For switches that work according to this principle consists and that the capacitor and the circuit arrangements is the term »self-locking Switch of the test circuit, on the other hand a Wi-test multiple «has been stamped. the status belongs to the test multiple. The invention relates to a circuit arrangement 3. Circuit arrangement according to claim 2, therefor together with a self-locking test multiple characterized in that the resistance consists of working test circuits with uniform values There is a voltage divider from which the test duration in telecommunications switching systems is less limited, At least one branch of the checking circuit and an in particular long-distance communication switchboard. whose branch belongs to the test multiple. 40 test multiple circuits are available in great variety Knows It is based on the German patent specifications 919479, 942934, 1005 567, 1013 702, 1036 325 and 1 119 921. A self-locking test multiple is used to In telecommunication switching systems there is 45 simultaneous connection of more than one individual arrangement for checking and assigning individual switching devices to a central one directions the special problem of parallel testing switching device leading common line with fens two test circuits, which are to be prevented with certainty at the same time. In each of the individual «To be connected to a body to be examined. These sound devices are a test relay and a means of The problem has already been solved in various ways, such as connecting the individual switching device to been. Known circuit solutions provided the common line. Try two principles can be recognized for this: at the same time more than one individual switchgear ! a) In the event of two of the parallel testing testing "" δ ™ for the self-locking Prüfvielfach aufzuprüschaltungen is a priority over the ^fe _ ⁿ - ^so _tt ^{k can "right? de} ^ ^several test relays atispreanderen, namely by ^Μ <: ^hen · Under "simultaneously" is to be understood that a 1) temporal preference ^the P ^ f processes of at least two individual testing2) circuit- ^related preference for dual switching devices, e.g. the response time b) -for the case of parallel testing, both ™ ^ume * · "« ■ P ™ frelais, at least partially time-tested test circuits, are rejected and both test pre-, cover. gears repeated; Elimination of a single ^6o _Λ ^D ' ^e 8f. ^sets « ^A " (8 ^from « _t ^w T ^d according to the invention da-test circuit through time spreads in the re- ^dun * &? ™ 1> ^d ? ^{ß d} ! ^e PrufschaHungen with a retrieval rhythm of the various test ^circuits * ™ ** & * ^{of the} pinching process, i.e. the tests, are equipped with a permanently started delay element, which only with a completely within the test In circuit arrangements according to the first of the ⁶ 5 continuous delay process a positive two previously mentioned principles only gives a test result, and its delay process a single test process with the result "free" with single peeps at a higher speed, with or "occupied" instead. With the help of switching means for parallel testing at lower speed and at