DE2215357A1 - Method for producing an intermetallic contact on a semiconductor component - Google Patents

Description

Dipl.-Ing. H .. Sauenland · Dn.-lng. R. König · Dipl.-Ing. K. Bergen

Patent Attorneys ■ 4gdo Düsseldorf · Cecilienallee 7S ■ Telephone 43S7aa

Our file: 27,348. March 28, 1972

RCA Corporation, 30 Rockefeiler Plaza,

New York , 'NY 10020 (V.St.A.)

"Method for producing an intermetallic contact on a semiconductor component"

The invention relates to a method for producing an intermetallic contact on a semiconductor component.

In the semiconductor industry, various types of deposited contact layers are currently known as ohmic Contacts used for semiconductor components. The type of contact layer that is used is determined by their Reliability, costs and the manufacturing conditions of the component are determined.

A more reliable and expensive contact structure that has been developed is commonly called the "beam-lead" contact designated. In fact, this term is used to denote a number of similar structures, most of which are covered by a first layer of platinum are identified in an opening of an insulating 'layer and on the surface of the semiconductor, for example Silicon, are precipitated. The platinum layer is sintered to form an intermetallic (platinum-silicide) To form area that extends below the surface of the semiconductor body. Secondary metal layers like titanium and gold, are then left on top of that

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Applied to platinum.

The depth and conductivity of the intermetallic area can be monitored by controlling the thickness of the metal layer and the sintering temperature; Thus, when using a relatively thin metal layer which was produced at low temperatures, for example between 400 and 700 ^° C., an alloy region can be created which extends relatively flat in the semiconductor body. However, intermetallic contacts made in this way have relatively low conductivity.

Continue to have intermetallic areas, which are manufactured at such low temperatures, not the ability to follow high manufacturing temperatures withstand, as is the case with intermetallic areas, eg above 700 ⁰ C, produced at higher temperatures.

The object of the present invention is therefore to propose a method that enables the production of thick, highly conductive intermetallic contacts at relatively high Sintering temperatures allowed, with the intermetallic contacts only down to shallow depths below the Extend surface of the semiconductor body.

This object is achieved according to the invention in that the semiconductor body has an insulating layer on one surface is provided which has an opening extending to the surface that in this opening a semiconductor layer is produced on the surface to which a metal layer is applied, which, with appropriate treatment, forms an intermetallic compound with the semiconductor layer, and that the Metal and semiconductor layers are treated in such a way that they form an intermetallic compound of metal and Form semiconductors.

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Based on the "preferred" shown in the drawing Exemplary embodiment, the invention is explained in more detail below. Show it:

1 shows a component during the production method according to the invention, on which some known method steps have already been carried out, in cross section;

FIGS. 2 to 4 show the component shown in FIG. 1 during further method steps according to the invention, in cross section.

Referring to FIGS. 1 to 4, the inventive Process below using the example of production a bipolar transistor explained. It goes without saying, however, that the method does not apply to such Components is limited, rather also in the manufacture of diodes, thyristors, integrated circuits and other types of semiconductor components can be used. -

The component shown in FIG. 1 has already been subjected to various known manufacturing steps before it receives the structure shown. As can be seen from FIG. 1, these method steps lead to a highly conductive collector substrate 11 of one conduction type (in the illustrated example N ⁺ ) on which an epitaxial collector region 12 of the same (N) conduction type but with a higher resistance is located. A diffused base region 18 of a second (P) conduction type extends into the collector 12 at its upper surface 14 and forms a base-collector PN junction 20 between collector 12 and base 18. An emitter region 19 of the first (N) conduction type extends into the base region 18 and forms an emitter-base PN junction 21.

Preferably contain collector substrate 11 and collector

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gate, base and emitter regions 12, 18 and 19 silicon; their dimensions are not critical.

Fig. 1 also shows that parts of an original insulating layer 16, for example made of silicon dioxide, remain at the surface 14 on the collector area. After the previously carried out diffusion steps for the base and emitter, a further insulating layer 22 is formed on surface 14 on the base and emitter areas 18 or 19 and the remaining parts of the original insulating layer 16 are left. In practice they are Insulating layers 16 and 22 are very thin, approximately between 10,000 and 20,000 Å. However, to the present invention To clearly show the thickness of the insulating layers 16 and 22 as well as that of others to be described Layers greatly enlarged.

According to Fig. 1, the insulating layer 22 is treated so that base and emitter contact openings 24 and 25 are formed therein, expose the parts of the base and emitter regions 18 and 19, respectively, on the surface. This treatment step can be implemented, for example, by photolithographic methods, the insulating layer 22 with einöm Covered photoresist, masked with a pattern containing contact openings 24 and 25, exposed and developed will. The layer 22 is then treated with an etchant, which only those in the openings 24 and 25 located parts of the layer 22 removed.

According to FIG. 2, layers 26 and 27 of semiconductor material are then deposited only in openings 24 and 25, respectively. Each layer 26 and 27 has the same conduction as the area 19 and 18, respectively, which it contacts, and is preferably very highly conductive. In the example shown, layer 26 has N ^{+ line} and layer 27 has P ^{+ line} .

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The semiconductor layers 26 and 27 are preferably monocrystalline., although polycrystalline semiconductor material can also be used. Furthermore, the semiconductor layers 26 and 27 do not need to consist of the same semiconductor material to consist of which the collector substrate 11 and the areas 12, 18 and 19 consist, but is this is preferably the case. For example, if that .... Substrate 11 and region 12 as shown in FIG. O. For example, containing silicon, the semiconductor layers 26 and 27 also preferably contain silicon The thickness of the semiconductor layers 26 and 27 is not critical. However, as will be explained in more detail below, the thickness of the semiconductor layers 26 determines and 27 partially the alloy depth of the intermetallic Contact below the surface 14, which after- ' is formed following. For example, the semiconductor layers 26 and 27 can have a thickness of 5Q00S. These layers 26 and 27 can be incorporated into openings 24 and 25 by any of a number of known ones Techniques that do not fall within the scope of the present inventions are discarded. For example For example, the semiconductor layers 26 and 27 can be produced by hydrogen reduction of silicon tetrachloride will.

According to FIG. 3, the insulating layer 22 and the semiconductor layers are applied 26 and 27 a metal layer 28 is deposited in the openings 24 and 25 by means of known methods, e.g. by evaporation or spraying. It is important that the metal of layer 28 be one of the metals is that with appropriate treatment an intermetallic compound with. the material of the semiconductor layers 26 and 27 forms. The metals that can be used for this include gold, silver, platinum, palladium and rhodium. Because however, given the relatively well-researched intermetallic properties of platinum and silicon, platinum is preferred ».

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The thickness of the metal layer 28 is also not critical; however, it is also true here that the The thickness of the layer 28 partially corresponds to the alloy depth of the intermetallic contact below the surface 14 certainly. For purposes of illustration, a thickness of approximately 8000 S can be specified for the metal layer 28.

Thereafter, the semiconductor and metal layers 26, 14 and 28 are treated to form an intermetallic compound that defines a base intermetallic contact 30 only in the base opening 24 and an emitter intermetallic contact 31 only in the emitter opening 24. The contacts 313 and 31 can be formed by sintering the semiconductor and metal layers 26, 27 and 28 at a temperature between 400 and 900 ^° C. in an inert atmosphere, for example argon.

If the metal layer 28 contains platinum and the semiconductor layers 26 and 27 contain silicon, as is the case in the present exemplary embodiment, intermetallic contacts 30 and 31 are made of platinum silicide in the openings 24 and 25 by sintering the layers 26, 27 and 28 at a temperature of produced about 75O ⁰ C. If the thickness of the layers 26, 27 and 28 is selected accordingly, the platinum silicide contacts 30 and 31 extend to a shallow depth into the base and emitter regions 18 and 19, respectively, as shown in FIG. 4. For example, when the platinum and silicon layers are thick 3000 S, respectively, and a sintering temperature is used above 75O ⁰ C, the Platinsilizidkontakte 30 and 31 extend about 1200 Å deep in the base and emitter regions 18 and 19th

After the intermetallic contacts 30 and 31 have been formed, the remaining platinum 28 is removed and metallic emitter and basic contact are shown in 0hm'schein contact

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the intermetallic contacts 30 and 31 are depressed.

The method according to the invention leads compared to the prior art of technology, among other things, to the considerable advantage that an intermetallic contact can be made on a semiconductor component regardless of alloy depth considerations.

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Claims (7)

RCA Corporation, 30 Rockefeller Plaza, New York , NY 10020 (V.St.A.) Claims; / 1 .JProcess for producing an intermetallic contact on a semiconductor body, characterized in that that the semiconductor body is provided with an insulating layer on one surface, which has an opening extending to the surface that one in this opening on the surface Semiconductor layer is produced, on which a metal layer is applied, which with appropriate treatment an intermetallic compound with .the "semiconductor layer forms, and that the metal and semiconductor layers are treated so that they are an intermetallic Form a connection between metal and semiconductor. 2. The method according to claim 1, characterized that the semiconductor layer is monocrystalline. 3. The method according to claim 1 or 2, characterized in that that the semiconductor layer has the same conductivity type as the semiconductor body. 4. The method according to one or more of claims 1 to 3, characterized in that the The semiconductor body and the semiconductor layer consist of the same semiconductor materials. - 5. The method according to claim 4, characterized in that that the semiconductor material contains silicon. 2 U 9 8 h 2/1081 6. The method according to one or more of claims 1 to 5, characterized in that the Metal layer from, a metal of the group containing gold, silver, platinum, palladium and rhodium. 7. The method according to one or more of claims 1 to 6, durchgeke η η ζ ei eh. Η et,. that the layers are heated to a temperature above -75O ^{0 C in an inert atmosphere.} 209842/1081 Blank page