DE2200393A1 - BUFFER STAGE WITH SLIDING REGISTERS - Google Patents

Description

Buffer Stage with Shift Registers The invention relates to a buffer stage with shift registers to which parallel input signals are fed, which in in the same order as when entering data from the shift register outputs are, with the entire content of the shift register by one level of the shift register is shifted further, and the input signals with the help of a ~ control register in a selected line of the shift registers can be stored, the line from across to the shift registers lying stages of this register is formed and the selection the Line is done by a control logic, which is the last free memory line before the output of the shift register.

Such buffer stages are used for temporary storage of information used in data processing electronic systems, especially in the event that that information is offered to a consumer at irregular times should, with intermittent the speed with which the information is supplied - is greater than the consumer can process at the moment. Another It is used, for example, when synchronous further processing arrives asynchronously Information should be done.

Well-known buffer levels of this type are often several in parallel lying shift registers, with the stages forming a line of the Shift register one word or one

Can store bytes. Here the word is parallel in the first And shifted from line to line to the last free line. The consumer retrieves the information from the last line -from this The last line that has become free by shifting the entire memory content by in each case one line is filled up again towards the last line. This must be ensured be that information is only then stored in the next line, even if this line has really become empty. Complex comparison circuits are therefore required and / or delay elements required, which prove to be poorly integrated circuits let build up and cause the circuit to work relatively slowly. So there is a possibility that no information is available to the consumer although there is information in the memory that was previously stored has been.

These disadvantages can be avoided according to the invention if each Stage of the individual shift register has a set input, -der with the output of an AND element is connected, one input each of the AND element of a shift register is connected to a common input for the input signals and a second input the AND elements in connection with a stage of the control register via a control logic which is assigned to the corresponding stages of a row of the shift registers is. The writing of incoming information.

The last free one goes into the buffer level immediately Line without having to move from line to line. To ensure, that if the buffer memory is empty, the information is read into the last line, A set input of the last stage of the can also be designed as a shift register - Control registers are at the output of an AND element, one input of which is at the signal input for a control bit, which together with the input signals for the shift register occurs, and a second input of the AND element with an output of the last Level of the tax register.

A simple structure for the control register and the control logics results: # if a signal is provided for a control bit that is combined with the parallel input signals for the buffer stage occurs which is stored the signal input is at the input of a monostable multivibrator, which emits short pulses at an output that are within the pulse duration of the input pulses for the buffer stage, and this output to the control logic of the shift register stages of the buffer memory and the last level of the control register is kept. Here a common control logic can be assigned to each row of the shift register stages be, where the control logic contains a flip-flop as a single-ended memory, its output when a pulse arrives - from the signal input for the control bit - Assumes the signal state of a second input at a first input, which is connected to an output of a stage of the control register, which of the preceding Row is assigned to the corresponding shift register stage.

The control logic can be changed in a simple manner by the different Switching status of the first occupied level of the control register to the last free level this register takes place when the first input of the single-ended memory of the control logic at the output of an AND element, the first input of which is connected to the input for the Control bit is connected and its second input at an output of a Level of the control register is connected, which of the line of the corresponding Shift gas stage is assigned. The shift register, the control register and the essential parts of the control logics can easily be taken from commercially available integrated building blocks.

Further details and the mode of operation of the invention result from the following description of an embodiment that shows a circuit principle shows a buffer level with integrated blocks.

In the drawing there are three olocksynehrone 5 bits that can be set and deleted Shift register 1; 2 and 3 are shown parallel to each other, which are based on can connect further shift registers on the right. These shift registers can consist of integrated modules, as they are offered in stores (here e.g. the blocks SN 7496 N from Texas Instruments). The setting Entrances of the individual shift register stages are each at the negated output of an AND element 4 (hereinafter referred to as Nand element), of which an input 5 with the same Inputs of the other shift registers is connected line by line.

The second inputs of this NAND element 4 are each in the shift register modules connected to one another, the combined inputs 6 of the first shift register to a voltage source with an L signal and the combined inputs 7 and 8 of the shift registers 2 and 3 as well as the adjoining # eating # shift register Input adjustments 9; 10 to signal inputs E1; E2 to En are performed.

The series input 11 of all shift registers is at 0 potential, while the directional inputs 12 of all shift register stages are combined and can receive a # n negative reverse pulse via an inverter 13. The Q and Q husgands of the individual shift register stages are each connected to the R-S inputs of the following Level connected. The clock inputs 14 of all shift register stages are also summarized and can via a further negator 15 with negative pulses be applied when the information in the individual shift registers by one Level is to be pushed further.

At the Q outputs of the first shift register 1 are exceptions of the Gi bus passage of the first stage - which is part of line 1 - a first input each connected to a NAND element 16, the second inputs of which are connected to one another amplified via two inverters 17 and 18, and slightly delayed by an RC element 19 nugatise pulses can be obtained from a monostable cultivator 20, wherein at the 4 output of the multivibrator: 20 the input of the first inverter 17 via the Resistance of the RC element 19 is connected. The outputs of the four Nand members 16 is always at the clock input 21 of a so-called D flip-flop 22, whose D input 23 each connected to the Q output of the stage of the first shift register 1 that precedes the stage, to whose Q output the respective NAND element 16 is connected is. The four D flip-flops 22 also have a preset input 24 that is interconnected are connected to the Q output 25 of the monostable level vibrator 20. The Q output the D flip-flops 22 are connected to the line-by-line via an inverter 26 Inputs 5 of the NAND members 4 out, with one of the NAND members 4 at the set input the stage of the first shift register 1 is at the Q output of the D input this D flip-flop 22 is shot. The output 27 of the last stage of the first Shift register 1 is also connected to one input via an inverter 28 of an AND element 29, the second input of which is together with the Nand elements 16 to the inverters 17; 18 is connected and its output to the line by line combined inputs 5 of the NAND elements 4 of the last row 5 is located.

The mode of operation of the buffer memory is as follows: Together with the Input information - which is to be stored and consists of several parallel, the number of shift registers 2; 3; ... the corresponding bit can exist - becomes a Control bit generated, which arrives at the input S of the nultivibrator 20. Through this the Nultivibrftor tilts at its Q output to 0 and generates the capacitor des RC # element 19 a lel & ht delayed 0 pulse, which is sent to all inputs of the NAND elements 16 arrives. If the buffer memory is empty, e.g. all stages of the shift register through a directional pulse is set in the marked starting position via the inverter 13, is at all Q outputs of the first shift register 1 - that as a control register acts - a 0 signal. As a result, all N; Lnd elements 16 are blocked, only at the second input of the AND element 29 is a via the negator 28 # Signal, which gives all NAND gates 4 of row 5 an Ii signal at one input is fed. As a result, the input information becomes the respective input adaptations 9; 10; .... at one input of the NAND element 4 of all stages of the corresponding shift register 2; 3;. '' Is stored in line 5, since all other NAND elements 4 of the Lines 1 to 4 remain blocked. At the same time, the NAND element 4 of the tax register 1 the level of line 5 of the control register is set to Q = L.

If there is now a further input information can be obtained from the control bit This input information is no longer generated by the control pulse via the AND element 29 because the output of the control register stage in line 5 is now set to L. On the other hand, the NAND element connected to this output is activated by this L signal 16 pass the control pulse to the clock input 21 of the last D flip-flop 30, This results in the information 0 from the Q output of the stage at the D input from line 4 of control register 1 in the Q output. This 0 signal arrives as an L signal via the inverter 31 to the inputs 5 of all NAND elements 4 of the set inputs in line 4. This stores this information in line 4, and the Level of control register 1 in line 4 set in Q = L. After the service life has expired of the multivibrator 20, the D flip-flop 30 is reset again via the preset input 24 and the Q output, as with all other D flip-flops 22, is held in Q = L.

Registered mail is therefore only possible when the Multivitråtor is not in use for a short time possible, whereby interference pulses that are outside the service life cause the storage can not influence.

In the case of a further information input, this is done from line 5 the control register 1 always one step further to line 1 at the Q output = L set. Where the last output is "0" and the output is the next Stage has an L in the direction of line 5, this will be the case at these two Q outputs connected flip-flop set briefly to Q = 0. This results in storage of the incoming information In the same order, always directly to the last free line with the highest line number.

The information is read out in a manner known per se with the help of a push-through pulse via the negator 85, the information content of the entire memory including that of the tax register by one level in Direction to exits A1; A2; until An moves and the old one, at the exits deletes previously pending information. Via the Q-husgang 27 of the last stage of the Control register 1 can also have the control bit assigned to the information at output 32 can be tapped in the same way.

If necessary, with an appropriate choice of the pulse lengths in a simple way, a simultaneous storing n '## of the information e.g. can be avoided by switching an AND element in front of the 1 control bit input S. is that by a blocking pulse upstream of the push-through pulse during the short duration of a relocation is blocked. With a sufficiently chosen The length of the pulse duration of the input information and the control bit is then entered Save only before or after the information has been re-saved or moved on at the shift registers.

The entire buffer storage can be largely integrated be built with semiconductor elements without difficult to be produced delay elements or resistors, etc. are required, whereby a higher packing density and a higher degree of security against errors in manufacturing and results during operation.

Claims (8)

Expectations Buffer stage with shift registers to which parallel input signals are supplied, which are in the same order as when entering from the outputs the shift register are retrievable, with the entire contents of the shift register is shifted by one stage of the shift register, and the input signals with the help of a control register in a selected row of the shift register can be stored, the row of these stages lying transversely to the shift registers Register is formed and the line is selected by a control logic, which selects the last free memory cell before the output of the shift register, characterized in that the çede stage of the individual shift registers (2; 3) one Has set input which is connected to the output of an AND element (4), oe one input of the AND element (4) of a shift register (2 or 3) at a common one Input (7 or 8) for the input signals and a second input (5) for the AND elements (4) via a control logic (16; 21 to 26) with one stage of the control register (1) which is related to the corresponding stages of a row of shift registers (2 ~ 3) is assigned. 2. Buffer according to claim 1, characterized in that a Set input of the last stage (line 5) of the - also designed as a shift register - Control register (1) is at the output of an AND element (19), one of which is an input at the signal input (S) for a control bit, which together with the input signals occurs for the shift register, and a second input of the AND gate (29) with is connected to an output (27) of the last stage of the control register (1). 3. Lufferstuf e according to one of claims 1 or 2, characterized in that that a signal input (S) is provided for a control bit, which together with the parallel input signals (t1; E2 to En) for the buffer stage that is stored the signal input (S) at the input of a monosta # Ilen t4ultivibrator (20), which emits short, delayed pulses at an output that are within the pulse duration of the # input pulses for the buffer stage, and this output to the control logics (16; 21 to 26) of the shift register stages (2; 3) of the buffer memory and the last stage (line 5) of the control register (1) is kept. 4. buffer stage according to one of claims 1 to 3, characterized in that that each row of the shift register stages (2; 3) has a common control logic (16; 21 to 26). 5. buffer stage according to one of claims 2 to 4, characterized in that that the control logic for the shift register stages (2; 3) is a flip-flop as a single-ended tape recorder (22) whose output when a pulse arrives - from the signal input (S) for the control bit - the signal state of a second at a first input (21) Input (23) accepts that at an output (Q) of a stage of the control register (1) is connected, which of the previous line of the corresponding Schi eberegi stage is assigned. 6. buffer stage according to claim 5, characterized in that the first The input of the single-ended memory (22) is at the output of an AND element, the first of which The input is connected to the input for the control bit (S) and its second Input connected to an output (Q) of a stage of the control register (<) which is assigned to the row of the corresponding shift register stage. 7. Buffer memory according to one of claims 1 to 6, characterized in that that the individual stages of the shift register (2; 3) and / or the control register (1) from IK flip-flops with additional set and straightening inputs as well as parallel input and Exits exist. 8. Buffer memory according to one of claims 1 to 7, characterized in that that the shift register (2; 3) the control register (1) and / or the control logic (16; 21 to 26) for the shift register stages as. built-in integrated circuits are. L e r s e i t e