DE2158512B2 - Data transmission system with majority checking device - Google Patents

Description

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The invention relates to a data transmission system with a plurality of data transmission devices, from which each transmit data to other such devices on the basis of specified control commands or can receive, with each data transmission device f> 5 with a majority checking device for checking the control commands transmitted in parallel to select the correct control command is provided, also with a number of control units, each via a control line normally give identical control commands to each data transmission device in parallel.

DT-PS 1 290 960 describes a method for transmitting signals in telecommunications system "known, according to which d" 2 signals over two independent signal channels are transmitted, after evaluating the received signals an approval signal or a Repeat signal is transmitted back. By transmitting the signals over two channels from one Switching center to another should reduce the risk of failures. With this system but no special control devices are provided that give commands to the switching centers to activate one of a number of such centers. The questions of a synchronization of such Control devices therefore do not arise in the previously known system

From the DT-AS 1 199 C? 6 is a data processing system known, in which information is passed from one level to another, with a Comparison device is provided. the characters issued by the transmission stage with acknowledgment characters compares that are returned by the receiver stage via a feedback channel. 1st this one If the comparison is positive, an equality signal is generated.

This known system is also not equipped with a plurality of control units that synchronously give the same control command sequence to the transmission stage or transmission stages, which is why such a synchronization Control command sequences is neither intended nor required.

From the IBM News, February 1970, pp. 7 to 13, information transmission over three is redundant Lines known with a subsequent majority decision. This method allows when taking the signals coming over the three lines is a wrong signal, this by means of the majority decision identify and turn off.

US Pat. No. 3,501,743 discloses a system for correction known of signal errors occurring in one or more of a variety of signal transmission channels appear. A majority circuit is assigned to each channel. Those coming through the channels Signals are given to a plurality of devices that are assumed to be that they could fail during operation. The outputs of the devices coupled in this way are then given to a majority circuit, which processes the correct signal.

On the basis of the data transmission system mentioned at the beginning, the object of the invention is now in the case of redundant control command transmission over more than two lines, the possible delivery correcting an incorrect control command and transferring the same information to all redundant To restore lines.

According to the invention, this is achieved in that the data transmission device addressed by the command returns the selected control command to each of the control units via each of the control lines, that furthermore each control device with a control command generator for storing the command issued, a register for the temporary storage of the returned command and a comparator to compare these two commands is provided and that if a control unit has a majority decision in the addressed data transmission device as

Has issued an incorrectly recognized command and stored it in the register that stored in the control command generator Commands compared with the retransmitted command stored in the register until they match will be

Further developments of the invention are characterized in the subclaims. An example embodiment the invention is explained below with reference to the drawing, in which

F i g. 1 schematically shows a block diagram of a system according to the invention;

F i g. 2 shows the sequence of the data flow on the data lines;

F i g. 3 and 4 show the mechanical structure of a control unit and _J5

F i g. 5 and * »show schematically the structure of a Data transmission device.

F i g. 1 shows three independent control lines Hl, Hl and H3, each of which is monitored via its own control unit HCl, HCl and HC3. Also shown are three peripheral data transmission devices PUl, PUl and PUi, which should be noted. that a much higher number is normally used. Each data transmission device has a separate connection to each control line. Via these and their connections to the data transmission devices, data cannot be transmitted in both directions at the same time, but in each direction. Each control unit generates the same sequence of control commands under the control of its own clock pulse generator. The sequence does not have to be issued symmetrically, but it is often the case that some commands have to be repeated more often than others. The control units work independently of one another.

F i g. 2 shows part of a sequence of control commands, it being assumed that the three control units operate synchronously. Each control unit delivers a control command CIx. The command delivered first, which is shown in the upper part of FIG. 2 activates the individual data transmission devices. Each data transmission device is delayed for a time IV after receiving the first command on one of the control lines before the others can arrive, after which the three commands are checked during the time interval CT. If accepted, the command is executed and the value X is transmitted to the receiving units by the data transmission devices on all three control lines. Immediately before the data is transmitted, the data transmission equipment sends ^{back the control command CIx 1} , which synchronizes the three control units. After a short time interval Γ, the three control units transmit the next control command CIy. A clock pulse is assigned to each bit of the control command and can be transmitted on a separate clock pulse line CH.

In the F i g. 3 and 4 show a schematic diagram of a control unit. This has a control command generator CIG which, for example, can have the form of a read-only memory and contains the full 8 command sequences that the control unit has to output. In the F i g. 3 and 4, the clock circuits are not shown in detail. The output value supplied by the control command generator CIG is transferred to a Regis .er HR and a shift register OSR . Since a parity check is required on a data transmission device, the output of the control command generator CIG also controls a generator PG, which is there. ' passes the required pantäts-Bit on to the shift register OSR In the same way from a generator CBG evaluation and other control bits to the shift register OSR r. This shift register OSR is connected to a data line DH , which is monitored by this special control unit.

The transmission of control commands from the shift register OSR to the data line DH is controlled by clock pulses from a clock pulse generator CP. The output of the generator is connected via a blocking element GX to both the shift register OSR and to the clock pulse line CH . In addition, receives a detector EOD whose output extensive with eiiiem input of a three input OR gate G9 is connected to clock pulses, said member controls the addressing of the control command generator CIG The output of detector EOD is further connected to the set input of a monostable circuit L . The setting output of the monostable circuit L forms one of the three inputs to an OR element G2, the output of which forms the blocking input for element GX . The output of element GT. also forms one input of an AND gate G3, the other input being connected to the clock pulse line CH. The output Gi forms the clock pulse input for a register RISR, the data input of which is connected to the data line DH . The register RISR is connected to a comparator C and thus to the register HR . The register RISR is also connected to a detector RID and to a content-addressed memory CAM . The output of the detector RID is connected to the reset input of the monostable circuit L and to the setting input of another monostable circuit T. The output of T forms a / wide input for the OR element Gl,

The output of the detector RID is connected to the reset input of a monostable circuit F via an edge detector £ 1. The output of F is connected to an AND gate GA comprising three inputs, the other two inputs representing the outputs of the detector RID and the comparator C. The output of the gate G4 forms an input of an OR gate G5, while the other input is transmitted by an edge detector £ 2 to which the output of the monostable circuit F is applied. The output of G5 is connected to the reset input of a monostable circuit R. The setting input of the monostable circuit R is branched off from an AND element Gb comprising two inputs, one input of this element representing the output of the detector RID . The other input of G6 results from reversing de; Output of the comparator C via an inversion link GJ. The output of the monostable circuit R forms the remaining input to the OR gate G to one of the three inputs of an AND gate GS provided with three inputs. The other inputs led to GS are the output of the memory CAM and the inverted comparator output of Eq.

The output of GS is transmitted as an input to each of the two OR gates G9 and C10 and to a delay device D. The output of G9 forms the addressing input for the control command generator CIG, and the detector EOD provides a second input to the element G9. The exit de

Delay device D forms the second input of the OR gate ClO. The output of GlO is connected to the setting input of the monostable circuit F via an edge detector £ 3, the output of which is connected via an inversion element GYl to an AND element GIl comprising three inputs together with the output of GlO and the signal from RlD is.

The control unit described above works as follows:

The control command generator CIG issues a command to the register HR and to the shift register OSR. This last-mentioned register also receives every required parity, evaluation or control bit from the generator PG and from the generator CBG. If there is no blocking by the element Gl, the clock pulse generator CP supplies a clock pulse sequence by means of which the command stored in the shift register OSR is transmitted to the data line DH. At the same time, the clock pulse train is transmitted to the clock pulse line CH. The output end on the data line is detected by the detector EOD , which transmits an address signal to the control command generator CIG via the element G9 and brings the monostable circuit L into its unstable position. The output of the circuit L passes through the element G2 and blocks the element Gl, which prevents further clock pulses from being transmitted to the shift register OSR or to the clock pulse line CH while L remains in the set / position. The output from the element Gl is also transmitted to an input of the AND element G3.

The blocking of the clock pulses means that the shift register OSR contains the next instruction together with its parity and control bits, but the register HR still contains the first instruction. The second command is not transferred to the HR register within this switching state.

Provided that the system as a whole is working properly, one of the data transmission devices returns the command to the control device before the time interval determined by the monostable circuit L has expired. This returning instruction is accompanied by a clock pulse train which triggers gate G3 and enables the instruction to be read into register RISR.

The receipt of this return command is received by the detector RID , the output of which resets the monostable circuit L and sets the monostable circuit T. The latter maintains the blocking on member Gl via member G2 . The return command in register RISR and the command given first in register Hi? are compared with one another by the comparator C. If these match, the time cycle of the monostable circuit continues without other influencing factors. After the time interval of Γ has elapsed, the monostable circuit takes over its own reset. The blocking input is thus separated from the element GI, and the next command can be output via the clock pulse sequence and entered into the register HR to carry out the next comparison. This sequence of functions is retained as long as the system is working properly. If no test command is received during the time delay of the monostable circuit L , the blocking input is disconnected from the element Gl at the end of the delay period and the next control information is output via the data line.

The time intervals of L and Γ are the same in each control unit of the system and are dimensioned to be sufficiently long so that each data transmission device can carry out the necessary switching operations. The time interval of Tist in FIG. 2 shown.

If a command received from the RISR register does not match the command previously issued and stored in the HR register, the control unit starts a “resynchronization” in order to find a command within the sequence of control commands that matches the one already received. As mentioned earlier, it is very likely that some will occur more than once and others only once within the sequence of instructions. These commands, which only appear once, can be used for this purpose. to re-synchronize the control unit. The content-addressable memory CAM is used to identify these special commands that occur only once within the sequence.

If there is a discrepancy between the transmitted and received signals, the comparator C supplies an output value. If the received command is not one that occurs only once, output values result from the detector RID and from the comparator C, but not from the memory CAM. Accordingly, operates only the gate G6, since the signal of RID and the inverted comparator output via GJ is established In this manner, the monostable circuit R is set, the output from R, is indeed fed from the gate G8, causes no function of the limb, because the output from CAM is not available. The output from the monostable circuit allows only the gate Gi to operate, whereby a further blocking pulse is transmitted to the gate Gl for the duration of the time delay of the monostable circuit R. After this delay has elapsed, the next command is issued.
If, on the other hand, the received command is a one-time command that causes an input from the memory CAM, the full resynchronization process starts. In this case, in addition to the setting of the monostable circuit R described above, the element G8 is switched on.

The output from OB goes through element G9 and addresses the control command generator CIG. This runs at the highest possible speed, and each new instruction is read into the shift register OSR as well as into the register HR. Thieves-

errors in the shift register OSR are not transferred to the data line because the clock pulses are blocked.

The commands from the control command generator CIG are successively compared with the fed in register RISR eherten command. In the event of a match, the comparator output stops. so that no more output is supplied by the element GS. At the same time the Emstell input to the monostable circuit R is interrupted via the gate G6, and the

<* R clock period starts. By disconnecting the output from G8, the addressing input from GS to element GS is also disconnected. In contrast, however, the delay device D delivers a signal via the elements GlO and GI1 to element G9. to the

*> 5 to address the control command generator CIG again. Any disconnection of the output from the element GIO is detected by an edge detector £ 3, after which the monostable circuit F is set. Here-

through an input is separated from the link GIl. The next return command is now expected. If there is a match with the command stored in register HR , the output of RID causes the monostable circuit F to be reset via the edge detector E1 and the monostable circuit T to be set, after which the monostable circuit R via the element GA as a result of the non-occurrence of the comparator output is reset, whereby an input is separated from the element Gl . The clock pulses remain blocked, but in this case through the output of the monostable circuit T. After the time interval of T has elapsed, the clock pulse block is canceled and normal operation is resumed. If the last comparison is unsatisfactory, the output of comparator C appears again and the entire resynchronization process starts again.

If no other command is received after the clock cycle of the monostable circuit F has started, the monostable circuit R is reset at the end of the output from F via the edge detector El via G5 after the clock cycle of F has expired.

The F i g. 5 and 6 show in schematic form the arrangement of a data transmission device for checking and processing incoming control commands. As can be seen from the illustration, the signals are received by each clock pulse and data line via receivers Ri to Rh. The signals (data) received from receivers R2, R4 and /? 6 are transmitted to an input of three blocking elements G22, G24 and G26 and from here they reach the data inputs of three registers IRi, IR2 and IR3. The Si signals (clock pulses) of the receivers Al, R3 and / 75 who via blocking elements G21, GH and G25 each to OR elements G27. G2 » and G29 placed. Their outputs are connected to the clock pulse inputs of the registers IRi, IRl and IRi . The other input to each OR element G27, G28 and G29 is branched off from an AND element G30 comprising two inputs, which has internally generated clock pulses IC and a cycle check signal CC which are applied to these inputs.

The outputs of the three links G21. G13 and G15 are also CTI with separate counters. CTl and CTi connected. The outputs of the three counters are applied as inputs to cm I 'ND element G31 and to an OR element 32. The output of the element G31 is connected to one input of an OR element G33, while the output of the element GM is connected to the other input of the element C33 via a delay device DL. The output of the element G33 represents the signal IH used for blocking.

The register IR3 differs from the other two registers in that the output from the element G26 is not transferred directly to the register, but forms an input for an OR element G34. The other input of G34 is derived from a gate network described in more detail later.

Each of the registers Wl. IRZ IR3 is designed in such a way that two corresponding outputs are available. The register IRi supplies an output Wl V which indicates that the word (or the command) which is transferred to the memory is valid. ie has the corresponding BIT number; an output Wi is also provided. In the same way, the register IR2 also has two outputs IV2V and W1; the register / A3 has the two outputs WJV and Wi. The outputs Wi V and IVI are connected to the AND element G35, the outputs W2 Kund IV2 are connected to the AND element G36 and the outputs Wi V and Wi are connected to the AND element GX1. The outputs of the elements G35, G36 and G37 are connected to an OR element G38. The output of this forms an input of an AND gate G39 and the output of G39 forms an input of an OR gate G40. As already mentioned, the output of G40 is connected on the one hand to the OR gate G34 and on the other hand to a parity check circuit PC.

The schematically in F i g. 6 is shown with free connections for the sake of simplicity. The outputs Wl V, Wl V and 1 * 3 V of the three input registers are connected to a word counter VWC whose output signals 1 V, 2 V, 3 V depend on the number of valid words contained in the registers. The 1V signal for "one-word validity" is connected to element G39. If necessary, the words themselves can be fed to a majority checking device VR which selects the corresponding bits by successive bit checking according to the majority principle. The output is a composite command word CtV (unless there is only one word in the registers or all words match, as should be the case). The output of the composite word CW is processed with the signal 3 V for "three-word validity" in a member G41, resulting in an output 3 VC which is fed to member G40.

The remaining main logic part is a comparator CMP, which checks the equivalence of the words used. The outputs Wi V and »VI of the register IRi are connected to an AND element G42, the output of which is connected to an input of the comparator via an OR element G43. In the same way, the outputs Wi V and VV3 of the register IRi are fed to an AND element G44, the output of which is connected to the other input of the comparator via an OR element G45. An AND gate G46 receives the outputs W2V and Wl transmitted from the register IR2. whereby the output of G46 is connected to one input each of two AND gates G47 and C * 48. The gate G47 receives the output Wi V at its other input, its output being connected to the OR gate G43. In the same way, the gate G48 receives the output Wl V on its other input, its output being connected to the OR gate G45. The output of the element G43 is also connected to an AND element G49, to which the 2 V signal is applied as a further input. The output of G49 is a signal 2 VC which is transmitted to element G40.

A command memory IS contains all commands to which the respective data transmission device should respond. The instruction memory / 5 and the output DA from the register IRi are connected to a comparator CM, the output DA here via an AND element G56. to which a signal Db is transmitted. The output of the comparator CM controls an AND element GS5, via which data OD is transferred from a data source OS to an OR register.

Another group of control elements shown in FIG. 6 is used to inform the data transmission device about the status of the command that was last checked. An AND element GSQ is used as an input

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ge the signal 2 V from the word counter VIVC and the signal 2 V / from the comparator CMP . The output of G50 is applied to an OR element G51 together with the output of an inverter element G52, to which the 2 V signal is applied as an input. The output of G5X forms an input of an AND gate G53, to be precise together with the signal from the parity check circuit PC and the output of an OR gate G54, which receives the three signals 1V, 2V and 3V from the word counter VWC.

F i g. 6 also shows devices for returning a command to the control units from a of the data transmission devices.

The content of the register / A3, which is available after the test procedure, is read into the register OR and transmitted from here via the control circuits DRX to DRZ to the three data lines DHX, DH1, DHi . At the same time, the internal clock pulses / C are processed by an AND element G57 together with a signal OP and transmitted to the clock pulse lines CW1, CW2, CHi via control circuits DR4 to DR6.

The data transmission device works as follows: A word (or a command) is read into each register IRX, IR2, / A3 under the control of the clock pulses on the clock pulse lines. If each word can be viewed as complete, the associated counter CT supplies an output value. Each counter output causes the delay device DL to start up, which activates the blocking signal TH from the element C-33 after a predetermined time interval and prevents further data from being transferred to the register IR . On the other hand, if all three input commands are fully received before the time delay expires, the same blocking signal is generated via elements G31 and G33. A test cycle is now carried out.

If all three commands are complete and if they match, as would ideally be assumed, then all outputs WIV, W2V, W3V are available. The word counter VIVC thus supplies an output 3 V. The three commands are then detected by an internal clock pulse IC and a cycle check signal CC , which are transferred to the three registers IR via element G30 and elements G27, G28 and C29. The words pass through the majority checking device VR bit by bit in order to generate a command word CW. In the present case, this corresponds to the three commands received. At the same time, the three commands are read into the comparator CMP. Since three words are valid, signal V is transmitted to elements G47 and G48. As a result, the word Wl can reach each of the inputs of the comparator via the element G46, its output signal 2 V / indicating that the two words are identical.

The output signal from G49 is not available because three valid words are transmitted via the word counter VWC V and do not leave 2 vent.

With the 3 V signal, the composed command word ClV can reach the OR element G40 via the GAX element and from here to the // 73 register. At the same time, the parity of the word is checked by the parity check circuit PC . This word is now available as output DA from register // 73.

Due to the absence of the 2 V signal at the G5X element and the presence of the 3 V signal at the G53 element, the element 52 can open if the parity release signal from the PC is present. The output from GS1 pushes the

correct condition of the data and informs the data transmission device that the command can be processed further. On the basis of this signal, member G5A can pass on the output DA from the register IRi to the comparator CAi, where it is compared with the command list to which the data transmission device is to respond. In the event of a consensus, the output of the comparator is open; Link G55, according to which the data from a data source

ίο DS can be passed to the register OR for the progressive Ubertragunf via data line the data is preceded by an assumed command dei tab IRi was stored and the signal by the OP, which is assigned to the member G29, ir

the OR register has been entered. Simultaneously with the transmission of the command and the data on the data lines, a sequence of internal clock pulses / C is output via the clock pulse lines CH via the element G57.

Within the above description it was assumed that the ideal state is reached when all three data lines have the control command evaluated at the same time.
If only two of the words, e.g. B. the words IVl and

Wl, are valid, the word counter delivers the signal 2 V. The three words or the two words and part of the third still pass through the majority checking device to form a compound word, but this is not used because the 3 V signal

GAX is not available on the link.

Under the above conditions, the word IV1 runs through GA2 to one input of the comparator ^x ° ™ ^CMP > while the word W1 runs through G46 and O48 to the other input of the comparator. That

Olied G49 thus supplies a 2VC signal, since both inputs are present. If the words transmitted to the comparator are identical, this fact is indicated by aas oignal 2 V /. The signal 2VC from G49 passes through the gate GAO as in the previous case and

reaches the register IRi.

2 the signal supplied by the comparator activates the Vl members G49 to supply as in the previous case, the signal Db to G53. However, if the two words transferred to the comparator are not identical,

so the word IVl is written into the register IRi , but not used by the data transmission device.
Is it the two valid words?

cn \ u ^m · ^{so the} above-mentioned sequence became in the

start in the same way, except that the word IV2 would be transferred to one input of the comparator and the word Wi to the other input; the word wrote * " ^{this Fa! Ie in the} register // 73. The same is true if aen valid words are IVl and 1 * 3; IVl would be on one input of the comparator and on that Kegister / R3 transmitted, while the word Wl would be transmitted to the other input of the comparator.

"" ε the last possible situation is that only one of the three commands is valid. In this case, the word counter VWC supplies the signal »V. The comparator Τ ™ α 1 ^Off * ^on & since only e, n input is present

₆ , IZ , ^ ^{Ugen Beff} * l depends on the entrance to the

1 ⁸ J ^Ι β * ™ "* ^now through the gate network 7iZ J?" ⁶ P ^members G35 to G40 determine the valid

2 ^ ° "^ fT ** ¹ **« η «* of elements G35 to G37 and the OR element GXL due to the presence of the

Signal 1 V at element G39 , the valid word of this and elements G40 and G34 can pass through on its way to register IR3. As in the previous case, the parity is checked, and if this check is positive, the signal is transmitted from the PC to the gate G53. G51 becomes 2 V due to the absence of the signal

activated at element G52 and C54 by signal 1 V. Element G53 thus supplies a signal D6, after which the data transmission device can accept and further process the commands now contained in register IRi.

In addition 5 sheets of drawings

Claims (4)

Patent claims: 1. Patent transmission system with a large number of data transmission devices, each of which can transmit or receive data to other such devices on the basis of predetermined control commands, each data transmission device being provided with a majority checking device for checking the control commands transmitted in parallel to select the correct control command, and also with a number of control devices which normally issue identical control commands to each data transmission device in parallel via a respective control line, characterized in that the data transmission device (PUi, PL / 2, PIß) addressed by the command sends the selected control command to each of the control devices (HCi, HC2, HC3) returns that each control unit also has a control command generator (CIG) for storing the control command sequence, a register (HR) for temporarily storing the command issued, a register (RISR) for temporarily storing the returned command n command and a comparator (Q is provided to compare these two commands and that if a control device has issued a command recognized as incorrect by majority decision in the addressed data transmission device and stored in the register (HR) , the commands stored in the control command generator (CIG) with the The returned command stored in the register (RiSR) must be compared until they match. 2. Data transmission system according to claim 1, characterized in that the output of the comparator (Q is given to a monostable circuit (R) , the output signal of which is applied to the control command generator (CIG) via members (GB, G9) . 3. Data transmission system according to claim 1 or 2, characterized by a comparator (CM) which compares the selected control command with the commands stored in a command memory (IS) in order to enable the respective data transmission device to respond only when the two commands match. 4. Data transmission system according to one of the preceding claims, characterized in that each control device (WCl, HCl, HC3) has a clock pulse generator (CP) and a clock pulse line (CH) and each data transmission device (PLJi, PL / 2, PLB) is connected to all clock pulse lines (CH) via which clock pulses are transmitted from the clock pulse generators (CP).