DE2158512C3 - Data transmission system with majority checking device - Google Patents

Description

The invention relates to a data transmission system with a plurality of data transmission devices from : nen any data to other such devices on some given control commands or transmitted can receive, with each data transmission device having a majority checking device for checking the irallel transmitted control commands is provided for selecting the correct control command, also with a Number of control units that normally send identical control commands in parallel via a control line to each data transmission device gebea

From DT-PS 1 290 960 there is a method for signal transmission Known in telecommunications systems, after which the signals via two independent signal channels be transmitted, after evaluating the received Signals an approval signal or a repeat signal is transmitted back. Through the ίο Transmission of signals over two channels from one switching center to another should reduce the risk be reduced by failures. In this system, however, no special control devices are provided, give the commands to the switching centers to activate one of a plurality of such centers. The questions of synchronization of such control units therefore arise with the previously known System not

From the DT-AS 1 199 026 is a data processing system known, in which information is passed from one level to another, with a Comparison device is provided, which the characters emitted by the transmission stage with acknowledgment characters compares that are returned by the receiver stage via a feedback channel. 1st this one If the comparison is positive, an equality signal is generated.

This previously known system is also not with a

Equipped with a plurality of control units, which synchronously send the same control command sequence to the transmission stage or Give transmission stages, which is why synchronization of such control command sequences is neither provided nor required is.

From the IBM news. February 1970, p. 7 to 13, is an information transmission over three redundant lines with a subsequent majority decision known. This method makes it possible when one of the signals coming over the three lines the wrong signal is to identify this by means of the majority decision and to switch it off.

From US-PS 3,501,743 a system for the correction of signal errors is known, which in one or more occur from a variety of signal transmission channels. There is a majority circuit for each channel The signals coming through the channels are assigned to a plurality of given to devices that are believed to fail during operation. the Outputs of the devices coupled in this way are then given to a majority circuit, which the correct signal is processed

On the basis of the data transmission system mentioned at the beginning, the object of the invention is now the basis, bsi a redundant control command transmission over more than two lines, the eventual output correcting an incorrect control command and transferring the same information to all redundant To restore lines.

According to the invention, this is achieved in that the data transmission device addressed by the command returns the selected control command to each of the control units via each of the control lines, that furthermore each control device with a control command generator for storing the command issued, a register for the temporary storage of the returned command and a comparator to compare these two commands is provided and that if a control unit has a majority decision in the addressed data transmission device as

ally recognized command is output and stored in the register; it has been saved in the control command generator. : Compensate herten commands with the retransmitted command stored in the register until they match will.

Developments of the invention are in the sub-claims An example embodiment of the invention is given below with reference the drawing explained in the

1 schematically shows a block diagram of an inventive device Systems shows;

2 shows the sequence of the data flow on the data lines;

3 and 4 show the mechanical structure of a control device and, ₅

F i g. 5 and 6 schematically show the structure of a data transmission device.

1 shows three independent control lines Hi, HZ and H3, each of which is monitored via its own control unit HCi, HC2 and HQ . Also shown are three peripheral data transmission devices PU \, PUl and PUi, where 2.u should be noted that a significantly higher number is normally used. Each data transmission device has a separate connection to each control line. Via these and their connections to the data transmission devices, data cannot be transmitted in both directions at the same time, but in each direction. Each control unit generates the same sequence of control commands under the control of its own clock pulse generator. The sequence does not have to be issued symmetrically, but it is often the case that some commands have to be repeated more often than others. The control units work independently of one another.

F i g. 2 shows part of a sequence of control commands, it being assumed that the three control units operate synchronously. Each control unit delivers a control command CIx. The command delivered first, which is shown in the upper part of FIG. 2 activates the individual data transmission devices. Each data transmission device is delayed for a time VV after receiving the first command on one of the control lines before the others can arrive, after which the three commands are checked during the time interval CT. If accepted, the command is executed and the value X is transmitted to the receiving units by the data transmission devices on all three control lines. Immediately before the data is transmitted, the data transmission devices send the control command CIx! back, which synchronizes the three control units. After a short time interval T has elapsed, the three control units transmit the next control command CIy. A clock pulse is assigned to each bit of the control command and can be transmitted on a separate clock pulse line CH

In the F i g. 3 and 4, a schematic diagram of a control device is shown. This has a control command generator CIG, which can, for example, have the form of a permanent memory and contains the full command sequences that the control unit has to issue. In the F i g. 3 and 4, the clock circuits are not shown in detail. The output value supplied by the control command generator CIG is transferred to a register HR and a shift register OSR . Since a parity check is required at a data transfer device, the output of which controls the control command generator CIG beyond a generator PG, which passes the required parity bit to the shift register OSR in the same manner, other by a generator CBG valuation and control bits to the shift register OSR transfera This shift register OSR is connected to a data line DH which is monitored by this special control unit.

The transmission of control commands from the shift register OSR to the data line DH is controlled by clock pulses from a clock pulse generator CP. The output of the generator is connected via a blocking element Gl to both the shift register OSR and to the clock pulse line CH . In addition, a detector EOD, the output of which is connected to an input of an OR element G9 comprising three inputs, receives clock pulses, this element controlling the addressing of the control command generator CIG. The output of the detector EOD is also connected to the setting input of a monostable circuit L. The setting output of the monostable circuit L forms one of the three inputs to an OR gate GX, the output of which forms the blocking input for the gate GX . The output of the element G2 also forms an input of an AND element G3, the other input being connected to the clock pulse line CH . The output Gi forms the clock pulse input for a register RISR, the data input of which is connected to the data line DH . The register RISR is connected to a comparator C and thus to the register HR . The register RtSR is also connected to a detector RID and to a content-addressed memory CAM . The output of the detector RID is connected to the reset input of the monostable circuit L and to the setting input of another monostable circuit T. The output of T forms a second input for the OR gate Gl.

The output of the detector RID is connected to the reset input of a monostable circuit F via an edge detector Ei. The output of F is connected to an AND gate CA comprising three inputs, the other two inputs representing the outputs of the detector RID and the comparator C. The output of the gate CA is an input of an OR gate G5, the other input from one edge detector El is transmitted to the output of the monostable circuit is F applied. The output of G5 is connected to the reset input of a monostable circuit R. The setting input of the monostable circuit R is branched off from an AND element G6 comprising two inputs, one input of this element representing the output of the detector RID . The other input of G6 results from reversing the output of the comparator C via an inversion element Eq. The output of the monostable circuit R forms the remaining input to the OR element G and, in addition, one of the three inputs of an AND element G% provided with three inputs. The other inputs led to G8 are the output of the memory CAM and the inverted comparator output of Eq.

The output of GS is transmitted as an input to each of the two OR gates G9 and G10 and to a delay device D. The output of G9 forms the addressing input for the control command generator CIG and the detector EOD provides the element GS with a second input. The exit dei

Delay device D forms the second input of the OR gate GlO. The output of GlO is connected to the setting input of the monostable circuit F via an edge detector £ 3, the output of which is connected via an inversion element G12 to an AND element GIl comprising three inputs together with the output of GlO and the signal from RID is.

The control unit described above works as follows:

The control command generator CIG issues a command to the register HR and to the shift register OSR. This last-mentioned register also receives every required parity, evaluation or control bit from the generator PG and from the generator CBG. If there is no blocking by the element Gl, the clock pulse generator CP supplies a clock pulse sequence by means of which the command stored in the shift register OSR is transmitted to the data line DH. At the same time, the clock pulse train is transmitted to the clock pulse line CH. The output end on the data line is detected by the detector EOD , which transmits an address signal to the control command generator CIG via the element G9 and brings the monostable circuit L into its unstable position. The output of the circuit L passes through the element Gl and blocks the element Gl, which prevents further clock pulses from being transmitted to the shift register OSR or to the clock pulse line CH , while L remains in the set position. The output from the element Gl is also transmitted to an input of the AND element G3.

The blocking of the clock pulses means that the shift register OSR contains the next instruction together with its parity and control bits, but the register HR still contains the first instruction. The second command is not transferred to the HR register within this switching state.

Provided that the system as a whole is working properly, one of the data transmission devices returns the command to the control device before the time interval determined by the monostable circuit L has expired. This returning command is accompanied by a clock pulse train which triggers the G3 element and enables the command to be read into the register RISR.

The receipt of this return command is received by the detector RID , the output of which resets the monostable circuit L and sets the monostable circuit T. The latter maintains the blocking on the link Gl via the link Gl . The return command in the register RISR and the command given first in the register HR are compared with one another by the comparator C. If these match, the time cycle of the monostable circuit Γ continues without any other influence. After the time interval of F has elapsed, the monostable circuit itself resets itself. The blocking input is thus separated from the element Gl, and the next command can be output via the clock pulse sequence and entered into the register HR for carrying out the next comparison. This sequence of functions is retained as long as the system is working properly. If no test command is issued during the time delay of the monostable circuit /. received, when the delay period has expired, the blocking input is separated from the element Gl and the next control information is output via the data line.

The time intervals of L and T are the same in each control device of the system and are dimensioned to be sufficiently long so that each data transmission device can carry out the necessary switching operations. The time interval of Tist in FIG. 2 shown.

If a command received from register RISR does not match the command previously issued and stored in register HR , the control unit starts a “resynchronization” in order to find a command within the sequence of control commands that matches the one already received. As mentioned earlier, it is very likely that some will occur more than once and others only once within the sequence of instructions. These commands, which only appear once, can be used to re-synchronize the control unit. The content addressable memory G4M is used to identify these. special, occurring only once within the sequence zo the commands used.

If there is a discrepancy between the transmitted and received signals, the comparator C supplies an output value.If the command received is not a one-time command, output values are obtained from the detector RID and from the comparator C, but not from the memory CAM . As a result, only the element G6 works, since the signal from RID and the inverted comparator output are established via Eq . The monostable circuit R is set in this way. The output of R, which is supplied by the element GS , does not cause the element to function, since the output of CAM is not present. The output from the monostable circuit allows only the element G2 to work, whereby a further blocking pulse is transmitted to the element Gl during the duration of the time delay of the monostable circuit R. After this delay has elapsed, the next command is issued.

If, on the other hand, the received command is a one-off command that causes an input from the memory CAM , the full resynchronization process starts. In this case, in addition to the setting of the monostable circuit R described above, the element GR is switched on. The output of GR passes through the element G9 and addresses the control command generator CIG. This runs at the highest possible speed and each new command is read into the shift register OSR as well as into the register HR. The commands in the shift register OSR are not transferred to the data line because the clock pulses are blocked.

The commands from the control command generator CIG are successively compared with the command stored in the RISR register. In the event of a match, the comparator output stops. so that no more output is supplied by element G8. At the same time the setting input to the monostable circuit R is interrupted via the element G6, and the to clock period of R starts. By disconnecting the output from GS , the addressing input from GB to element G9 is also disconnected. In contrast, however, the delay device O delivers a signala) via the elements GlO and G11 to the element G9 in order to address the control command generator CVG again. The possible separation of the output from the element GlO is detected by an edge detector £ 3, after which the monostable circuit F is set. Here-

by an input is separated from the link GIl. The next return command is now expected. If there is a match with the command stored in register HR , the output of RID causes the monostable circuit F to be reset via the edge detector EX and the monostable circuit T to be set, after which the monostable circuit R via the element GA as a result of the non-occurrence of the comparator output is reset, whereby an input is separated from the element Gl . The clock pulses remain blocked, but in this case through the output of the monostable circuit T. After the time interval of Γ has elapsed, the clock pulse block is canceled and normal operation is resumed. If the last comparison is unsatisfactory, the output of comparator C appears again and the entire resynchronization process starts again.

If no other command is received after the clock cycle of the monostable circuit F has started, the monostable circuit R is reset at the end of the output from F via the edge detector El via G5 after the clock cycle of F has expired

The F i g. 5 and 6 show in schematic form the arrangement of a data transmission device for checking and processing incoming control commands. As can be seen from the illustration, the signals are received by each clock pulse and data line via receivers R1 to R6. The signals (data) received from the receivers Rl, RA and R6 are transmitted to an input of three blocking elements G22, GlA and Gib and from here they reach the data inputs of three registers IRi, IR2 and / A3. The signals (clock pulses) of the receivers Rl, R3 and R5 are each to OR elements G27 via blocking elements GIi, G23 and G25. G2 & and G29 placed Their outputs are connected to the clock pulse inputs of the register IRi. IR2 and / R3 connected. The other input to each OR element GZ7, G28 and G29 is branched off from an AND element G30 comprising two inputs, which has internally generated clock pulses IC and a cycle check signal CC , which are sent to these inputs.

The outputs of the three elements GIi, G23 and G15 are also with separate counters CTl. CTl and C73 connected. The outputs of the three counters are applied as inputs to an AND element G31 and an OR element 32. The output of element G31 is connected to one input of an OR element G33, while the output of element G32 is connected to the other input of the element G33 or a delay device DL is connected. The output of element G33 represents the signal / f / used for blocking.

The register IR3 differs from the other two registers in that the output from element G26 is not transferred directly to the register but forms an input for an OR gate GM . The other input of G34 is derived from a gate network described in more detail later

Each of the registers IRU IR2. IR3 is structured in such a way that two corresponding outputs are available. The register / RI supplies an output WIV. who cares. that the word (or instruction) transferred to memory is valid, i. e. the corresponding BiT-ZaM has: in addition an output WI is provided, la in the same way the register IR2 also has two outputs W2V and W1; the register / R3 has the two outputs Wi V and Wi. The outputs Wl V and IVl are connected to the AND element G35, the outputs W2V and Wl are connected to the AND element G36 and the outputs WJV and Wi are connected to the AND element G37. The outputs of the elements G35, G36 and G37 are connected to an OR element G38. The output of this forms an input of an AND gate G39 and the output of G39 forms an input of an OR gate GAO. As already mentioned, the output of GAO is connected on the one hand to the OR gate G34 and on the other hand to a parity check circuit PC .

The schematic in F i g. 6 is shown with free connections for the sake of simplicity. The outputs IVl V, W2 V and IV3 V of the three input registers are connected to a word counter VWC whose output signals 1 V, 2 V, 3 V depend on the number of valid words contained in the registers. The 1 V signal for "one-word validity" is connected to element G39. If necessary, the words themselves can be fed to a majority checking device VR, which selects the corresponding bits by successive bit checking according to the majority principle. The output is a composite command word CW (unless there is only one word in the registers or all words match, as should be the case). The output of the composite word CW is processed with the 3 V signal for "three-word validity" in a member G41, resulting in an output 3 VC which is fed to the member GAO.

The remaining main logic part is a comparator CMP, which checks the equivalence of the words used. The outputs W \ V and IVl of the register / Rl are connected to an AND element G42, the output of which is connected to an input of the comparator via an OR element G43 In the same way, the outputs WJ V and WJ of the register / R3 are fed to an AND element G44, the output of which is connected to the other input of the comparator via an OR element G45. An AND element G46 receives the outputs IV2 V and Wl transmitted from the register / R2, the output of G46 being connected to one input each of two AND elements G47 and GAS . The gate G47 receives the output Wi V on its other input, with its output connected to the OR gate G43. In the same way, the gate GAS receives the output Wl V on its other input, with its output connected to the OR gate G45 The output of element G43 is also connected to an AND element G49, to which the signal 2 V is applied as a further input. The output of G49 is a signal 2 VC which is transmitted to element GAQ .

A command memory / 5 contains all commands to which the respective data transmission device should respond. The instruction memory / Sund the output DA of register IR3 are verbun with a comparator CM . the output DA here via ση AND Gfted G56 to which a signal Db is transmitted. The Aosgani of the comparator CM controls an AND element G55 via which data OD as a data source DS is transmitted to a register OR.

6s A group of control elements shown in FIG. 6 serves to inform the data transmission device about the status of the command checked by the network. An I) N D element GSb are ah inputs

50964OfIi

ge the signal 2 V from the word counter VWC and the signal

2 Vl supplied by the comparator OWf. The output of G30 is applied to an OR element G51 together with the output of an inverter element G52, to which the signal 2VaIs input is applied. The output of G51 forms an input of an AND gate G53, together with the signal from the parity check circuit PC and the output of an OR gate G54, which receives the three signals 1 V, 2 V and 3 V from the word counter VWC .

F i g. 6 also shows devices for returning a command to the control units from a of the data transmission devices.

The content of the register / R3, which is available after the test procedure, is read into the register OR and transmitted from here via the control circuits DRi to DR3 to the three data lines DW1, DH2, DhB . At the same time, the internal clock pulses / C are processed by an AND element G57 together with a signal OP and transmitted to the clock pulse lines CW1, CW2, CW3 via control circuits DRA to £> R6.

The data transmission device works as follows:

A word (or a command) is read into each register IRi, IR2, IR3 under the control of the clock pulses on the clock pulse lines. If each word can be regarded as complete, the associated counter CT supplies an output value. Each counter output starts the delay device DL , which activates the blocking signal TH from the element G33 after a predetermined time interval and prevents further data from being transferred to the register IR . On the other hand, if all three input commands are fully received before the time delay has expired, the same blocking signal is generated via elements G31 and G33. A test cycle is now carried out

If all three commands are complete and if they match, as would ideally be assumed, then all outputs »VI V, W2V, UO V are available. The word counter VWC thus supplies an output 3 V. The three commands are then detected by an internal clock pulse IC and a cycle check signal CC , which are transmitted to the three registers IR via element G30 and elements G27, G28 and G29. The words pass through the majority checking device VR bit by bit. to generate a command word CW. In the present case, this corresponds to the three commands received. At the same time, the three commands are read into the comparator CMP. Since three words are valid, the signal will

3 V transferred to members 647 and G48 . As a result, the word Wl can reach each of the inputs of the comparator via the element U46, its output signal IVl indicating that the words are identical.

The output signal from G49 is not available because three valid words via the word counter VWC result in the 3 V and not 2 V signal.

With the 3 V signal, the composed command word CW can reach the OR element GH) via the element G41 and from there to the register IR3 . At the same time, the parity of the word is checked by the parity check circuit PC. This word is now available as output DA from register IR3.

Due to the absence of signal 2 V at element G5i and the presence of signal 3 V at element G53, element 52 can open if the parity enable signal from PC is present. The output of G52 expresses the correct status of the data and informs the data transmission device that the command can be processed further. On the basis of this signal, the element G54 can forward the output DA from the register / A3 to the comparator CM , where it is compared with the command list to which the data transmission device is to respond. In the event of a match, the output of the comparator opens the element G55, after which the data from a data source

ίο DS can be passed on to the OR register for step-by-step transmission via the data line. The data is preceded by an accepted command which was stored in register IR3 and which was entered in register OR by means of the signal OP transmitted to element G29. Simultaneously with the transmission of the command and the data on the data lines, a sequence of internal clock pulses IC is emitted via the clock pulse lines CW via the element G57.

Within the above description it was assumed that the ideal state is reached when all three data lines have the control command evaluated at the same time.
If only two of the words, e.g. B. the words W \ and W2 are valid, the word counter supplies the signal 2 V. The three words or two words and a part of, although the third pass through even the Majoritätsprüfeinrichtung to form a compound word, it is j " xi not yet "used because the 3 V signal

is not present on link G41

Under the above conditions, the word W1 runs through G42 to one input of the comparator CMP, while the word W2 runs through G46 and through G48 to the other input of the comparator

Element G49 thus supplies a signal 2VC since both inputs are present. If the words transmitted to the comparator are identical, this fact is indicated by the signal 2 V /. The signal 2VC from G49 passes through the element G40 as in the previous fail and

reaches the register / R3.

2 the signal supplied by the comparator Vl aktivien limbs G49 to supply as in the previous case, the signal Db to G53. However, if the two words transmitted by the comparator are not identical, the word Wl is written into the register / R3, but not used by the data transmission device

If the two valid words un W2 and Wi are concerned, the above-mentioned sequence would be in de

start in the same way, except that the word W2 would be transferred to one input of the comparator and the word W. would be transferred to the other input; In this case, Wor W2 would be written into register / R3.

It behaves in the same way if the valid words are W1 and W3; Wl would be transferred to one input of the comparator and to the register IR3 , while the word W2 would be transferred to the other input of the comparator

The final possible situation is that nc one of the three commands is valid in this case fief « the word counter VWC the signal 1V. The comparato does not provide an output as there is only one input di depends on the valid command. The entrance to

Register / A3 is now determined by the gate circuit network with the elements <335 to GW. The valid word runs through one of the elements G35 into G3 and the OR element G3 & by the presence of de

Signal 1 V at element G39, the valid word of this and elements G40 and G34 can pass through on its way to register IR3. As in the previous case, the parity is checked, and if this check is positive, the signal is transmitted from the PC to the gate (753. C51 becomes 2 V due to the absence of the signal

Activated at member G52 and G54 by the signal 'Thus, member G53 supplies a signal D6, after which (data transmission device can accept the commands now contained in register I and process them further.

In addition 5 sheets of drawings

Claims (4)

Patent claims: 1. Data transmission system with a large number of data transmission devices, each of which can transmit or receive data to other such devices on the basis of predetermined control commands, each data transmission device being provided with a majority checking device for checking the control commands transmitted in parallel to select the correct control command, and also with a number of control devices which normally issue identical control commands to each data transmission device in parallel via a respective control line, characterized in that the data transmission device (PUl, PUl, PUi) addressed by the command sends the selected control command to each of the control devices (// Cl, HQ. HC3) returns that each control unit also has a control command generator (CIG) for storing the control command sequence, a register (HR) for temporarily storing the command issued, a register (RISR) for temporarily storing the returned command n command and a comparator (Q is provided to compare these two commands and that if a control device has issued a command recognized as incorrect by majority decision in the addressed data transmission device and stored in the register (HR) , the commands stored in the control command generator (CIG) with the The returned instruction stored in the register (RISR) must be compared until they match. 2. Data transmission system according to claim 1, characterized in that the output of the comparator (Q to a monostable circuit (R) is given, the output signal of which is applied to the control command generator (CIG) via members (G8, G9). 3. Data transmission system according to claim 1 or 2, characterized by a comparator (CM) which compares the selected control command with the commands stored in a command memory (IS) in order to enable the respective data transmission device to respond only when the two commands match. 4. Data transmission system according to one of the preceding claims, characterized in that each control device (// Cl, HCl, HG) has a clock pulse generator (CP) and a clock pulse line (CH) and each data transmission device (PIA, PUl, PUS) with all clock pulse lines ( CH) is connected, via which the clock pulses from the clock pulse generators (CP) are transmitted.