DE2109915A1 - Surface controlled semiconductor device - Google Patents

Description

Boeblingen, February 23, 1971

Official File number: New registration

Applicant's file number: Docket GE 970 025; GE 870 071

Surface controlled semiconductor device

The invention relates to a surface-controlled semiconductor arrangement, in the case of a substrate with first conductivity two areas with opposite second conductivity than Source and drain zones are introduced, in which the channel zone lying between the source and drain zone is covered with an insulating layer and this in turn is covered with a conductive layer as a gate and in the case of at least one electrical connection is provided between the gate and channel zone, according to patent (patent application P 20 01 184.1).

Such until the gate-channel connection similar to a conventional semiconductor field effect transistor structure similar arrangement requires in monolithic technology only one area cost in the order of a single field effect transistor and shows already a bistable behavior. The semiconductor arrangement is therefore eminently suitable for use as a monolithic memory cell.

Is attached to the gate electrode in such a semiconductor arrangement such a high potential is applied that a conductive channel is created between the drain and source zone, the channel potential can be used via said gate-channel connection to maintain the gate potential. This keeps the gate potential

209837/0986

tial also after switching off the introductory voltage pulse the gate electrode upright. Without this gate-channel connection, the gate potential would be due to unavoidable leakage currents sink and switch the field effect transistor into the blocking state after a certain time.

When the said semiconductor arrangement is used as a storage cell, one storage state is due to the conductive and the other Memory state indicated by the non-conductive channel. It is important to ensure that the the potentials corresponding to the two storage states are stable be maintained. For example, in the case of a gate voltage of approximately 0 volts, corresponding to the memory state O, ensure that this does not result from the potential distribution with a drain zone at, for example, +6 V and with a substrate bias of, for example, -3 V without a conductive Channel's resulting potential at the contact point of the gate-channel connection, e.g. +3 V, directly to the gate electrode is coupled. If this were the case, the leakage current stabilizing the gate potential or the leakage current via a second gate-channel connection would have to meet special requirements be asked. Such a mode of operation is possible, but obviously has disadvantages such as a required precise consideration of the leakage currents, their size and the resulting power loss.

For this reason, an improvement of the said semiconductor device has already been proposed that the Gate-channel connection is designed as a diode path. The diode path is preferably in the gate-channel connection connected opposite in series with the diode path formed by the substrate and the drain zone. Lie that way between the gate and drain electrodes two oppositely polarized diode sections, so that with regard to the choice of the gate voltage range at least one compared to the drain voltage

Docket GE 970 025; GE 870 071

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21Ü9915

greater freedom is gained.

On the basis of the proposed semiconductor arrangements mentioned, the object of the invention is to specify a semiconductor arrangement which ensures a further improvement with regard to the stability of the two memory states. In particular, on the one hand, for example, a potential 0 in the memory state 0 and in the memory state 1 a potential at the level that the channel between the drain and source zones is maintained. The measures required for this are while largely using known and well-dominated process technology and without significant additional Halbleiteroberfla- λ be achieved chenaufwand.

This task becomes for a surface controlled semiconductor device according to patent (patent application P 20 01 184.1)

solved in that, in addition to the gate-channel connection, a gate-substrate connection located outside the channel zone is provided. Significant advantages are obtained in that the gate-channel connection and the gate-substrate connection contain diode sections. In particular, one embodiment consists in that regions of second conductivity are provided in the channel or substrate at the contact points between the gate and the channel or substrate. In this connection, it is particularly suitable for the manufacturing process to be advantageous in that the gate electrode \ is made in accordance with the first conductivity doped polycrystalline material.

The surface-controlled semiconductor arrangement according to the invention thus contains a gate-channel connection in the vicinity of the drain zone a diode path, which is polarized in the reverse direction. Forms the gate-substrate connection located outside of the channel also a diode path, but at the contact point between gate and substrate with the selected doping of the polycrystalline Gates is polarized in the forward direction. On the other hand, the one located at the contact point between the gate and the substrate forms

Docket GE 970 025, GE 870 071 ₂₀

Area of second conductivity with the substrate one in the reverse direction Polarized diode, if the potential of the substrate at the border to the oppositely conductive area is suitably selected is. In this way, the desired high-resistance bleeder resistance for stabilizing the gate potential is obtained, which is from is of particular importance for the use of the described semiconductor arrangement according to the invention as a memory cell.

Particularly advantageous exemplary embodiments consist in that the gate-channel connection is located in the cut-off zone of the drain zone and that the gate-substrate connection located outside the channel zone is arranged in the area of the barrier layer of the transition between substrate and drain zone.

In this case, the gate-substrate connection touches a semiconductor region doped opposite to the substrate on one Place a lower potential than the gate-channel connection closer to the drain zone, the one at a higher point Potential touches a semiconductor region doped opposite to the substrate. The pad of the gate-channel connection between the e.g. p-doped gate and the e.g. n-doped region in the substrate in the vicinity of the drain zone is at the forming potentials polarized in reverse direction. In contrast, the lower potential is in the restricted area between substrate and Drain zone chosen so that at the location of the oppositely doped area in the substrate outside of the channel area such a potential exists that, for example, at a potential of O V at the gate corresponding to the storage value O other than the diode from gate and oppositely doped area in the substrate outside of the channel area also the diode from oppositely doped Area and substrate is polarized in the forward direction within the channel region. With this arrangement of connections chosen in this way A memory cell is created between the gate and the channel or substrate outside the channel, which both with respect to no restrictions on the permissible gate voltage range docke t GE 970 025; GE 870 071

209837 / 09P6

demands as well as a high stability of the gate potentials for the two memory states.

An advantageous embodiment is further obtained in that, to increase the channel resistance, the gate in Gate sections is divided.

The invention is explained in more detail below with reference to the exemplary embodiments shown in the drawing. Show it:

Fig. La is a schematic cross-sectional representation of a

semiconductor device according to the invention, (|

Fig. Ib is a schematic plan view of the invention Semiconductor device,

2 shows the equivalent circuit diagram of the semiconductor arrangement according to the invention according to FIGS. la and Ib,

3 shows a schematic illustration of a memory cell

using a semiconductor device according to the invention ,

4a shows a schematic cross-sectional illustration of a λ

Semiconductor arrangement according to the invention, in which the gate-substrate connection in the barrier layer of the substrate-drain junction,

FIG. 4b shows a schematic top view of the semiconductor arrangement according to FIG. 4a,

5 shows the equivalent circuit diagram of the semiconductor arrangement according to the invention according to FIGS. 4a and 4b and

6 shows a semiconductor arrangement according to the invention

divided gate.

Docket GE 970 025; GE 870 071 2098 3 7/0986

The in FIGS. The semiconductor arrangement shown in 1a and 1b consists of a P substrate 1 into which two N ⁺ -doped regions are introduced as a source and drain zone by means of known diffusion or iraplantation processes. As usual, the mutual spacing of the N ⁺ -doped regions 2 and 3 determines the length of the channel zone. This arrangement is covered by a thin oxide layer 4. In the region of the channel zone, the oxide is coated with doped, polycrystalline semiconductor material, for example with doped silicon. This polycrystalline semiconductor layer forms the gate 5. The contacting of the source and drain regions via metallic or doped polycrystalline layers 6 and 7. The connection to the drain region 3 is (using p-doped _f polycrystalline semiconductor material for the contact points by the positive drain voltage Figure 3) polarized in the forward direction. The contact with the source zone is polarized in the reverse direction, which acts as a series resistance of the channel. This sets the drain current to a low value, which is ultimately desirable for a memory cell. With the selected conductivities, there is a voltage of -3 V on the substrate, a voltage of +6 V on the drain electrode D and a voltage of 0V on the source electrode S, for example. The source zone 2 and the drain zone 3 together with the substrate 1 and thus with the channel zone form diode sections 16 and 17 (FIG. 2).

The field effect transistor structure described is correct with one exception the use of polycrystalline semiconductor material for the gate 5 and e.g. also for the contacts 6 and 7 with known designs of such transistors.

In the embodiment according to the invention according to FIGS. La and lb a connection 8 is established between the gate 5 and the region 10 doped opposite to the substrate 1 to the channel zone. In addition, a connection 9 is provided between gate 5 and a region 11 doped opposite to substrate 1.

Docket GE 970 025; GE 870 071

209837/0986

see. The connection 9 is not in the area of the canal zone. The connection 8 thus forms the contact point between the In the example under consideration, the P-doped, polycrystalline semiconductor material of the gate 5 and the N-doped region 10 in FIG Channel zone of the substrate 1. The connection 9 forms the contact point between the P-doped, polycrystalline semiconductor material of the gate 5 and the N-doped region 11 in the substrate 1 outside the channel zone.

If, with this structure according to the invention, a positive pulse is briefly applied to the gate electrode G and thus to the gate 5, then an accumulation of electrons is formed between the source zone 2 and drain zone % 3 as a result of the influence. This means that an N-conducting channel is created.

The potential distribution that occurs along the channel zone is tapped via the gate-channel connection 8 and onto the gate transfer. As a result, the channel is maintained even after the initial gate pulse has been switched off.

To operate the arrangement shown in FIGS. 1 a and 1 b, the voltages which are customary and already specified for operating a normal field effect transistor are applied. In order to achieve a storage effect, a potential of approximately 0 V must be ensured at gate 5 in storage state a 0 and a potential at the level in storage state 1 that the channel between the drain and source zone is maintained. In order to couple as high a potential as possible from the channel zone to the gate 5, the gate-channel connection 8 must be in the area of the barrier layer or cut-off zone, which builds up due to the voltage difference between drain zone and substrate 1, ie as close to the drain zone as possible 3. The substrate doping must be chosen to be low so that a wide barrier layer extension into the substrate results.

14 For example, a substrate doping of 10 atoms / cm

and a doping of the N-regions and thus the drain zone of Docket GE 97O 025; GE 870 071

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17 '3
10 atoms / cm can be provided. With a drain voltage of +6 V and a sub-voltage of -3 V, this results in an expansion of the depletion zone in the substrate in the area adjoining the drain zone of about 10 μm.

The case is now considered in which the potential applied to the gate 5 is greater than the potential of the N-doped region 10. As already mentioned, this would mean a potential greater than +3 V at gate 5. In this case the barrier is poled between gate 5 and region 10 in the forward direction. In contrast, the barrier layer between the area 10 and the Substrate 1 polarized in the reverse direction.

The potential of gate 5 is lower than the potential of the area 10, then the barrier layer between gate 5 and region 10 is polarized in the reverse direction. You have one against the potential of the gate voltage-independent current block between gate and drain zone.

From the equivalent circuit diagram in FIG. 2 of the arrangement according to the invention the always existing blocking can be seen, which is caused by the opposite polarity of the at the connection points between Gate 5 and region 10 and region 10 and substrate 1 formed diode paths 12 and 13 is effected.

According to the invention, there is now a second connection between the 0 for the storage state 0 to stabilize the potential Gate 5 and the substrate 1 with the interposition of an N-doped region 11 provided outside the channel zone. Figs. la and Ib show the contact point between connecting piece 9 and area 11 outside the channel zone. The one from the assumed Example of the P-doped connecting piece 9 and the N-doped region 11 is the existing diode path 14, as shown in the schematic Equivalent circuit diagram 2 can be seen, polarized in the forward direction. The area thus takes on the potential of Gate 5. One

Docket GE 970 025; GE 870 071

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formed between the N-doped region 11 and the substrate 1 Diode path 15 (Fig. 2) is due to the negative potential of, for example -3 V on the substrate and the always positive Potential at gate 5 polarized in reverse direction. This diode path 15 thus provides the leakage resistance for the gate 5 to ensure security of the potential O at the gate for the storage value O.

It is now assumed that the potential at gate 5 is so high that a channel is formed between source zone 2 and drain zone 3. In the example under consideration, a positive potential at the gate electrode G is required for this. That’s the diode 14 in Fig. 2 again polarized in the forward direction. The contact point corresponding to this diode 14 would be between the connecting piece 9 and area 11 are in the channel zone, then the channel then passing through area 11 would be the positive one Reduce the potential of the gate 5 storing the memory value 1 to the potential value in the channel zone at this point; however, the value of the channel potential at this point is almost 0 V. This state is prevented if the contact point exists from connection 9 and area 11 is arranged outside the canal zone. Then the high resistance of the lead remains of the gate 5, which is required for the aforementioned stabilization of the 0 potential, in which for the formation of a Channel obtained according to the storage value 1 required potential at the gate.

Reference is now made to the exemplary embodiment according to the invention according to FIGS. 4a and 4b with the associated equivalent circuit diagram in FIG Referring to Fig. 5. The parts of the structure corresponding to the exemplary embodiment according to FIGS. 1 a, 1 b are given the same reference numerals Mistake. A difference in the structure according to Fig. 4a, 4b is only that the gate-substrate connection, consisting of the connecting piece 19 and the N -doped region 18, in a defined manner with respect to the drain zone 2O Location is arranged. The effect of the diode combination 14, 15, which has already been described in connection with the exemplary embodiment according to

Docket GE 970 025; GE 870 071 209837 ^ 0986

Fig. La, Ib was described is particularly advantageous if the contact point outside the channel zone between gate and substrate, consisting of the connecting piece 19 and the ^ -doped region 18, is also in the depletion region of the drain region and the region 18 is thus approximately is at the potential O. For this purpose, as can be seen from FIG. 4b, the drain zone 20 can be widened laterally beyond the channel zone. At a potential of 0 V at gate 5 corresponding to the storage value 0, in addition to the ^{diode path 14 formed from the connecting piece 19 and the N + region} , the diode path 15 formed between the N region 18 and the P substrate 1 is now polarized in the forward direction. If at potential OV at gate 5 electrons are withdrawn from gate 5 via the reverse-biased diode path 12 and positive charges begin to collect on the gate, then these positive charges are immediately dissipated via diodes 14 and 15 which are continuous at potential 0.

If a positive potential corresponding to the storage value 1 is given to the gate 5, the diode 14 is still permeable, while the diode 15 is polarized in the reverse direction, so that the positive potential of the gate is maintained via the Blocking resistance of the diode path 12, potential losses of the gate, which is at +2.5 V, for example, are continuously compensated. The potential losses can be caused by undesired insulation currents.

The process of writing memory values is discussed in conjunction explained with FIG. 3. In FIG. 3, in addition to the field effect transistor structure according to the invention, referred to below as a memory transistor one connected to the gate electrode G and connected to a bit line BL and a word line WL Field effect transistor is provided, which is referred to below as the control transistor and via which the memory transistor is operated. When the memory value is written into the memory transistor, the value connected to the gate electrode of the

Docket GE 970 025 / GE 870 071 " _ΛΛΑΛΛ

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Drive transistor 22 connected word line WL brought to a higher potential for a short time. The drive transistor 22 becomes conductive as a result, so that a brief voltage pulse applied to the bit line BL reaches the gate electrode 6 of the memory transistor. This means that the gate 5 of the memory transistor is raised to a positive potential of, for example, +2.5 V corresponding to the memory value 1. The gate 5 retains this potential value even after the triggering voltage pulse has decayed, since this potential value is tapped from the N region 10 located in the depletion region of the drain zone 3 when the cone current is present and coupled to the gate 5 via the blocking resistor of the diode 12. M.

When the memory value O is written in, it is done in a similar manner the potential of the word line WL is raised and the 0 potential of the bit line BL via the conductive drive transistor 22 given to the gate electrode G of the memory transistor. As already described, the 0 potential at gate 5 is via the Reverse resistance of the diode 15 (FIG. 2), which is formed between the N region 11 and the P substrate 1, ensures.

In one embodiment of the memory transistor according to the invention according to FIGS. 4 and 5 become the 0 potential of the gate 5 thereby ensures that the two diodes 14 and 15 (FIG. 5) are polarized in the forward direction at 0 potential at gate 5. "

The process of reading out stored information can also be seen in the illustration in FIG. 3. When reading out the control transistor 22 is made conductive via an addressing pulse on the word line WL and the potential of the gate 5 of the memory transistor is filled with as high an impedance as possible via the bit line BL.

Reference will now be made to the exemplary embodiment according to the invention according to FIG. 6, which essentially corresponds to the execution dock t GE 970 025; GE 87O 071

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example according to FIGS. 4 and 5 and also with the the same reference numerals is provided. A significant advantage justifying difference is that the gate 5 in two sections 5a and 5b is split. As already stated, for reasons of stability it is desirable that the Gate of the memory transistor after the write pulse has subsided to store the memory value 1 as high a potential as possible adjusts. The potential at the location of the channel zone is critical for achieving a high potential at the gate, where the N region 10 is located. The potential in the area of area 10 is higher, the higher the channel resistance, which is essentially determined by its geometric dimensions. In the embodiment of the invention according to 6, the channel resistance is advantageously increased in that the gate 5 is divided into the two sections 5a and 5b. Between the two electrically connected gate sections 5a and 5b there is a section in the channel, in the area of which is caused by influence no electrons can be accumulated. In the mentioned channel area there is accordingly a high electrical level Resistance. One consequence of this is that the overall channel resistance is increased and the drain current is correspondingly decreased. The lesser one The drain current causes a higher potential at the point of the N region 10 in the depletion region of the drain zone and thus a higher potential at the gate sections 5a and 5b for the memory value 1.

For the storage value 0, the potential relationships remain the same, as with an undivided gate.

Docket GE 97O 025; GE 870 071 209837/0986

Claims (7)

PAT DISCLAIMER Surface-controlled semiconductor arrangement in which two areas with opposite conductivity are in a substrate second conductivity are introduced as source and drain zones, in which the between source and Channel zone lying on the drain zone with an insulating layer and this in turn covered with a conductive layer as a gate and in which at least one electrical connection is provided between the gate and the channel zone, according to the patent (Patent application P 20 Ol 184.1), characterized in that in addition to the gate-channel connection (8, 10) a gate-substrate connection (9, 11 or 18, 19) located outside the channel zone is provided. 2. Surface-controlled semiconductor device according to claim 1, characterized in that the gate-channel connection (8, 10) and the gate-substrate connection (9, 11 and 18, 19, respectively) contain diode paths (12, 13 and 14, 15). 3. Surface-controlled semiconductor device according to claim 2, characterized in that at the contact points between Gate and channel or substrate regions (10, 11 and 18) of second conductivity are provided in the channel or substrate. 4. Surface-controlled semiconductor device according to claim 3, characterized in that the gate (5) from accordingly the first conductivity doped, polycrystalline material consists. 5. Surface-controlled semiconductor device according to claims 1 to 4, characterized in that the gate channel connection (8, 10) is in the cut-off zone of the drain zone (3 or 20). Docket GE 970 025; GE 870 071 209837/0966 6. Surface-controlled semiconductor device according to the claims 1 to 5, characterized in that the outside of the channel zone lying gate-substrate connection (9, IO or 18, 19) in the area of the barrier layer of the substrate-drain zone transition is arranged. 7. surface-controlled semiconductor device according to claims 1 to 6, characterized in that to increase the Channel resistance, the gate (5) is divided into individual gate sections (5a, 5b). Docket GE 970 025, GE 870 O _{71 209837/0986} Lee on the back