DE2016443C3 - - Google Patents

Description

The invention relates to an associative memory with a mask register, the data content of the Memory containing word registers and search word registers according to the preamble of claim 1.

Associative memories are known (K. Steinbuch, Taschenbuch der Nachrichtenverarbeitung, Springer-Verlag 1962, page 522). In such a memory there is a data memory whose data can be accessed is exercised according to its content and not, as with a non-associative memory, according to its Storage location where the data is located. A typical associative memory consists of an input / output register, a mask register and word registers which contain the data in the memory. There is a in the input / output register Search argument which usually only occupies part of this register. The mask register is masked the part of the input / output register not occupied by the word registers by the search argument. It a search operation is then carried out in which the search argument is matched with the content of the same places in the Word register is compared in which the search argument is also in the input / output register. at The word register is usually equal to the search argument by setting a selection trigger marked, which then represents a predetermined stable state in the register. Then takes place on the an access operation takes place on the marked register. It is then either the content of the input / output register written in the marked registers or the contents of the marked registers are sequentially or read into the input / output register at the same time.

Also known from GB-PS 987666 is an associative memory with two input registers which serve as search word registers. These two registers are used to accommodate search word arguments of variable length and for this purpose are connected to one another and designed as shift registers. These two! Schicberc ^o ister and the dsirin ^ nth ^ ltCiien information or search words are controlled by a control circuit so that one of the two registers always has access to the memory without disturbing the other.

However, this known type of associative memory only has one data path to the outside if it also with the last-mentioned associative memory due to the presence of two input registers is possible to create two entry paths. This one

ίο Register, however, not as input and output register serve, but clearly only as a search word or search argument register, there is still a Narrowing of the data flow from the associative memory to the other units within a data processing system.

The invention is therefore based on the object of creating an associative memory that both on the input side as well as on the output side with the units of a data processing system more quickly.

zo men work than the previously known.

The solution according to the invention consists in the characterizing part of claim 1.

Because there are several input / output registers, there are now too in the interface the other units within a data processing system no longer have bottlenecks because the existing Registers can be loaded separately from one another and read separately from one another which means that the times for the input and output of both search terms as well as the searched data can fully overlap in time. This is particularly of great advantage, when using associative memory with a large storage capacity in which databases are stored. The traditional associative memory is able to do a parallel comparison of old data stored in the search word register to carry out the search argument, if necessary even with two search arguments, however, it is unable to overlap the found data or even output in parallel, but the data found are queried and output one after the other. This problem is solved with the present solution.

The invention is illustrated in detail with the aid of exemplary embodiments and the associated drawings explained. It shows

1 shows a form of the associative memory according to the invention,

2 shows a further form of the associative memory according to the invention,

Fig. 3a is a logic diagram of typical locations in the input mask register shown in Fig. 2,
3b shows a logic diagram of typical locations in an alternative form of the mask register,

3c shows the pictorial representation of a memory cell for the mask register of FIG. 3b,

Figures 4 and 5 are modifications of the mask registers of Figures 3a and 3b and

6 shows an arrangement of associative memories according to the invention.

In the figures, data paths are indicated by thick and

Control signal paths shown by thin arrow lines.

According to FIG. 1, an associative memory 1 consists of a memory arrangement 2 with a plurality of Word registers, which are each extended over the entire arrangement, from an input / output register I / O! one Einübe / Ausoebcrcfistcr T / 02 and one

Mask register 3. Between the register 1/01 and a data collecting line 5 there is a data path 4 for both directions and between the register 1/02 and a data collecting line 7 there is a similar data path 6 for both directions. Two-way data paths 8 and 9 connect the corresponding register 1/01 or 1/02 to the mask register 3, which in turn is connected to the memory arrangement 2 via the two-way data path 10 .

Although the invention can be applied to a passive associative memory to which control signals from external sources are applied, the memory shown in Fig. 1 is a functional memory in which a portion of the memory input is decoded to determine the operation to be performed by the memory. Correspondingly, the associative memory 1 contains a decoder 11 which receives data from register 1/01 via data path 12 and from register 1/02 via data path 13. Control signal lines 14 to 19 extend from the decoder 11 , the purpose of which will be explained later.

For a better understanding of the invention, the mode of operation of the associative memory 1 will first be described only when the register 1/01 is used. A word is transferred from the bus line 5 to the register 1/01 via the data path 4. A part of the word contains data which define the operation to be carried out by the associative memory 1 and is scanned by the decoder 11 , which as a result applies a control signal to the line 14 which defines the mask to be used and further control signals to lines (not shown) inside the memory arrangement that define the operation to be performed. An operation consists of two cycles, in the first of which one or more word registers of the memory arrangement 2 to which access is to be exercised are selected and in the second of which an access operation, reading or writing, is carried out on the selected word registers. The selection of a word register need not take place as a result of a comparison between an input search argument with the contents of the word register - a search operation - but can be carried out with reference to word registers which were selected in previous operations. Thus, following the registers selected in a previous operation, the next registers can be selected. Assume, however, that the operation to be performed is a search operation. It is further assumed that only two mask configurations are feasible and that a single binary signal on line 14 can sufficiently define the mask configuration to be used. With the first mask configuration, for example, the content of the eight left-hand positions of register I / Gl is used as a search argument and access is only exercised to the remaining positions of the word register, and with the second mask configuration, for example, the content of the left-hand 16 positions of register 1/01 used as a search argument and access is only exercised to the remaining positions in the word register. Assume that the Find, Read, Mask 1 operation has been requested. In the first cycle, the content of 1/01 is transferred to mask register 3 via data path 8, but since mask 1 is requested, only the eight positions on the left are used via data path 10 for comparison with the üriker ·. eight control, each word register of the memory arrangement 2 transferred. The selection trigger in each word register in which the comparison resulted in equality is set. In the second cycle, the status of the selection trigger is sensed and the content of those registers that have set their selection trigger is read out via data path 10 to mask register 3, which transfers all digits except the left eight via data path 8 to 1/01 . The content of 1/01 will be

ίο then via data path 4 to collecting line 5 transfer.

In contrast to known associative memories, the associative memory 1 according to the invention has a second input / output register 1/01, and either 1/01 or 1/02 can be used. Specifically with regard to the embodiment shown in FIG. 1, the decoder 11 generates control signals, as a result of which the search argument can be taken from either 1/01 or 1/02 . Furthermore, in the second cycle, an operation can either be written from 1/01 or 1/02 into the memory arrangement 2 or read from the memory arrangement 2 in either 1/01 or 1/02.

This is effected by the control signals on lines 15 to 19 from decoder 11. When energized, the line 15 connects the data path 8 over the marker register 3 to the data path 10. When energized, the line 16 connects the data path 9 via the mask register 3 to the data path 10. When energized, the line 17 enables the register 1/01 to receive data from the memory array 2. When energized, the line 19 enables the register 1/02 to receive data from the memory arrangement 2. When energized, line 18 enables both registers 1/01 and 1/02 to receive data from data lines 5 and 7 to which they are connected via data paths 4 and 6.

The decoder 11 is not described in detail here, since its use is well known. The decoder 11 consists, for example, of a Christmas tree network with four lines including the data path 12 or 13 as input and with 16 lines as output, one of which is designated in accordance with the binary signals on the input lines. The marked output then sets triggers that energize control lines 14 to 19 at the appropriate times.

Using these control signals, it can be seen that the following sequence of operations is possible is:

1. Set 1/01 and 1/02 via data bus 5 and 7 respectively;

2. Search using the search argument from I / Ol or 1/02;

3. Read or write between the selected word registers of the arrangement and 1/01 or 1/02; and

4. Read 1/01 or 1/02 on the data collector. Fig. 2 shows an associative memory according to the invention 20, which was modified from that disclosed in Fig. 1 memory 1 that the memory 20 may change the mask between the search and Zuferiffszyklen an operation. The individual mask register 3 of FIG. 1 is replaced by an input or search argument mask register 23 and two output mask registers 24 and 25. The 1/01 and 1/02 registers have been replaced by registers 21 and 22, which only serve as input registers. the

Output from the memory arrangement 2 occurs via the data path 26 and either via the mask register 24 and the data path 27 to the bus 5 or via the mask register 25 and the data path 28 to collecting line 7.

To simplify the drawing, the control lines from the decoder 11 have not been shown, but it can be seen that the decoder 11 sends out signals which specify the mask configuration for the mask register 23, from which register, 21 or 22, the search argument must be taken and whether the Operation is a read operation in array 2, which register, 24 or 25, is to transfer the data to the bus 5 or 7 connected to it and which mask is to be used. The ability to define which data field is to be transferred on the bus is of course useful when multiple associative memories 20 are connected to a bus. Each memory can operate simultaneously and independently with different characters of multi-character information, and the use of non-overlapping output masks for different memories produces a result that is aligned with the respective mask and at the same time with the bus.

In Fig. 3a typical locations of the mask register 23 are shown for the case in which the memory arrangement 2 consists of binary memory cells. It is assumed that only two masks are used: mask 1, in which the search argument goes beyond digits 0 to 7 of register 23, counting from the left and writing to memory array 2 using the remaining digits, and mask 2 , in which the search argument goes beyond the positions 0 to 15 of the register 23 and the writing into the memory arrangement 2 takes place by means of the remaining positions. In Figure 3a, the line 10 is a typical line of the points 0 through 7 of the data path 10, the line 10b is a typical line of the points 8 to 15, and line c is 10, a typical line from the higher digits. Lines 8a to 8c are corresponding lines of data path 8 from the input register to mask register 23, and lines 9a to 9c are corresponding lines of data path 9 from input register 22 to mask register 23. The meaning of the control lines on the right in Fig. 3 is as follows:

Line 14: mask information; if line 14 is energized, use mask 1, otherwise mask 2;

Line 15: when energized, use data from register 21;

Line 16: when energized, use data from register 22;

Line S: when energized, perform a seek operation;

Line W: when energized, perform a write operation, ie transfer data to the memory array 2;

Line Cl: when energized, it indicates cycle 1 time ;

Line C2: when energized, it indicates cycle 2 time .

If the line is energized 15, the AND circuits 31a to 31c are permeable and the binary data on lines 8a to 8c to 33 c as an input to the AND circuits 34e transmitted via the OR circuits 33a to 34c. , The AND circuits 32a Similarly, when the line 16 is energized, permeable to 32c, and the binary data on the lines 9a to 9c are transmitted via the OR circuits 34a to 34c.

Line 14 has a branch 14a and an inverter 35. When line 14 is not energized, the output line of inverter 35 is energized and gives a signal Ml, which indicates that mask 2 is to be used.

ίο Under the assumed operating conditions, only search argument data are on lines 10a , since both masks 1 and 2 extend beyond positions 0 to 7 of the mask register, and the line is not used for the transmission of data for a write operation. Accordingly, the inputs of the AND circuit 34a are the data output of the OR circuit 33a, the line S, the line Cl - since a search takes place in the first cycle of the two-cycle operation. It is not necessary to specify mask data since both masks 1 and 2 require the line 10a in a search operation.

On the line 10 b are search argument data under mask 2 and write data under the mask 1. The AND circuit 36 has as inputs the control lines Cl, S, and 14a. Its output is connected via the OR circuit 38 to the input of the AND circuit 34 b . Furthermore, the control lines C2, W and 14 are inputs to an AND circuit 37, the output of which is connected to an input of the AND circuit 346 via the OR circuit 38. The AND circuit 36 is energized when the line is to lead 10 b search argument data, and the AND circuit 37 is energized when the line is to lead 10b write data. Line 10c only carries write data and so AND circuit 34c has a data input from OR circuit 33c and control inputs from lines W and C2.

FIG. 3 b shows the modifications of the mask register of FIG. 3 a when the memory arrangement 2 consists of memory cells with three types of states. Each memory cell can assume stable states that represent binary 1, binary 0 and X. The X state is such that the cell does not signal an exception state, whatever interrogation signals have been applied to it during an associative search operation. A cell can, for example, have the configuration according to FIG. 3c. The electronic circuit that makes up the memory cell SC is between a collector line 131 and a word line 132 and between a pair of bit lines L and R. The cells SC of the same word share collector and word lines 131 and 132, respectively, whereas the cells for the same Place of different words have common bit lines L and R. To query the cell SC for the binary 0 state, the potential on the bit line L is lowered relative to an external voltage and the potential on the bit line L is increased. If the cell SC is not in the binary 0 or in the X stable state, the word line 132 carries current, which indicates an exception state. In order to write a binary 0 in the cell, the same potentials are applied to the bit lines as when the cell is interrogated , but the signals of the collector line 131 and the word line 132 are varied, so that the potentials on the bit lines disrupt the status of the cell and cause the cell to be stable

assumes binary O status. By reading out the potentials on the bit lines, the cell can be queried for a binary 1 or a binary 1 can be written into the cell. In order to write an X into the cell, the potentials of the collector line 131 and the word line 132 are matched to those of a write operation and the potentials of the bit lines are raised relative to the reference voltage. In the case of a cell which consists of two bistable circuits, it is not necessary for the raised bit voltage potentials to be applied at the same time. Accordingly, an X is written in two operations. During the first operation, a binary 0 is set in the input register and, if the bit information is masked, /. written. In the second operation, a binary 1 is set in the input register and is written with the bit line R masked. The first operation is called right write and the second is called left write.

In Fig. 3b parts of the same locations of the mask register 23 are shown as in Fig. 3a. The AND circuits 34 'to 34c in FIG. 3a are replaced in FIG. 3c by pairs of AND circuits, each AND circuit controlling a driver, not shown, for a corresponding bit line. In Fig. 3b the output of the OR circuit 33a is inverted and connected as an input to the AND switch 134a and is also connected in its real form as an input to the AND switch 135a. Further inputs to the AND switches 134a and 135a are the signal lines Cl and S from the decoder, which, when energized, indicate that cycle 1 is just now and that a search operation is required. If z. B. is to be searched for binary 0, the output of the AND switch 134iierregt and the output of the AND switch 135 is not energized. The combination of the states of the outputs of the AND switches 134a and 135a is determined by the drivers and corresponding potentials are applied to the bit lines.

An inverted output of the OR circuit 336 is connected as an input to the AND switches 13461 and 13462, and the real output of the OR circuit 33b is connected as an input to the AND switches 13561 and 13562. The lines Ml, Cl and S are connected as inputs to the AND switches 13462 and 13562. The lines Ml and C2 are connected as inputs with both AND switches 13461 and 13561 to the word line WL , which is then energized when a write left operation is required, or are connected to the AND switches 13461 and the line WR connected, which are then energized when a write right operation is required. Both lines WL and WR are energized when a write operation is required. The outputs of AND switches 13461 and 13462 are inputs for an OR circuit 136, the output of which controls the potential on bit line L. OR gate 137 connected to the outputs of AND gates 13561 and 13562 serves a similar purpose for bit line R.

An inverted output of the OR circuit 33 c is connected to the input of the AND switch 134 c, and the real output leads to the input of the AND switch 135 c. The line C2 is connected to the inputs of both AND switches 134c and 135c, the line WL leads to the input of the AND switch 134c and the line WR to the input of the AND switch 135c

The mode of operation of the mask register of FIG. 3b is analogous to that of the register in FIG. 3a and is therefore not explained again.

3a and 3b accordingly show how the data is selected from either register 21 or register 22 and as a search argument in a

ίο Access operation or used as a source of data which are to be written into the memory arrangement 2.

The invention is not limited to having the entire search argument from a single register

ι? must be taken. The search argument can be before. Data in two or more input registers are translated using non-overlapping fields of the Input register are hidden or that in AND, OR or EXCLUSIVE-OR operations overlapping fields of the register are logically combined.

FIG. 4 shows the modification of the circuit of FIG. 3 which is required for this logical combination and further shows a single digit of the left eight digits of the mask register 23. About the circuit 3 in addition, the data lines 8 and 9 with the inputs of an OR circuit 41 and an AND circuit 42 is connected. The output of the OR circuit 41 is connected to the input one AND circuit 43 connected, which has a control line 44 as a further input. The outcome of the AND switch 42 is connected to the input of an AND switch 45, which is also another Input has a control line 46. Lines 15 and 16 remain de-energized and around the OR function of the data on lines 8 and 9 to the OR circuit 33, becomes the control line 44 energized and the AND function of the data on lines 8 and 9 to the OR circuit 33 to transmitted, the control line 46 is energized. The control lines 44 and 46 are optionally through Signals from decoder 11 are energized in the same way as lines 15 and 16. To the OR circuit 41 and the associated control line 44 can be dispensed with, in which case the output the OR circuit 33 represents the OR function of the data in the two input registers. the The EXCLUSIVE OR function can be activated by adding an EXCLUSIVE OR circuit in parallel to the AND circuit 42 and OR circuit 41 can be achieved.

FIG. 5 shows the modification of the circuit of FIG. 3, which is used for masking non-overlapping Fields from both input registers for use

j ₅ is required as a search argument in a search operation. The positions 0 to 15 of the mask register 23 are divided into groups of four, since the size of a character is usually 4 bits, and separate control lines 15a to ISd and 16a to 16a ¹ apply data to the AND switches 34 (see Fig. 3) each job group. The control line 15a is connected as an input to all AND switches 31 (see FIG. 3) of the positions 0 to 3 of the mask register and the control line 156 leads as an input to all AND switches 31 of the positions 4 to 7 of the mask register and the like it for the control lines 15 c and 15 d. The control line 16a is an input with all AND switches 32 of the positions 0 to 3 of the mask reference

gisters connected and it is similar with the control lines 16 / j and I6d with regard to the positions 4 to 7, 8 to 11 and 12 to 15. The control lines 15 and 16 of FIG. 3 are omitted. With the arrangement of FIG. 5, by selectively energizing lines 15a to I5d and 16a to I6d, e.g. B. the lines 15a, 15 /), 16c and \ 6d by the decoder 11 different combinations of the fields from the input register to the mask register are hidden. The arrangement of FIG. 5 can be combined with the arrangement of FIG. 4.

The input registers of an associative memory according to the invention do not need as it is graphically in Figures 1 and 2 to be as wide as the memory array. For the different Different registers can be made available to fields of the arrangement. One embodiment in this technique is shown in FIG. 6, in which the associative memory array 61 via the register 62 with the bus 63 and via the register 64 with the bus 65 is connected. A second associative memory array 66 is connected to the bus via register 67 63 and connected to the bus 65 via the register 68. The memory arrays and Registers are part of the memories as described in connection with FIGS. Insubstantial Elements have been left out. The registers 62 and 64 and the register 67 pass over

ίο digits 0 to 7 of the corresponding memory arrangements 61 and 66. The register 68 extends beyond the positions 8 to 15 of the memory arrangement 66. With the arrangement shown, data that is aligned with the same locations in memory 61 can be aligned with adjacent groups of locations in memory 66. A first group of 8 bits is transferred from memory 61 to memory 66 via registers 64 and 67 and a second group of 8 bits via registers 64 and 68 to the same word register of arrangement 66 as the first group.

In addition 5 sheets of drawings

Claims (3)

Patent claims: 1. Associative memory with mask register, word registers containing the data content of the memory as well as search word registers, the effectiveness of which is controlled by a control circuit, characterized in that the mask register (3,23) is a selected logical combination of search arguments from several input registers (1701,1 / 02), which are used as output registers at the same time serve, and that the data read out from the memory (2) selectively in a of the aforementioned registers are transferrable. 2. Associative memory according to claim 1, characterized in that the mask register (3 or 23) different fields of the search argument from different input registers (1/01, 1/02) fades out. 3. Associative memory according to Claims 1 and 2, characterized in that the output field the data read out from the memory (2) is determined by output mask registers (24, 25).