DE2033709A1 - Associative storage system - Google Patents

Description

The invention relates to an associative memory system with at least a multi-digit associative memory containing an associatively controllable memory group from a plurality of word registers as well as at least one data register and one mask register.

Associative memories are not controlled by calling up a fixed address, rather they are accessed by means of an * associative query with part of the memory content itself. The so-called search argument includes some binary digits that make up part of the word length dee memory form. The content of all word registers is in this selected binary digits with the data content of the search term in

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Input register checked for equality; Word registers, the content of which starts with matches the search argument, set their associated selection trigger. The selected memory words can thus be controlled, with the actual Access, depending on the intended game, is more likely to operate on all the selected ones Words at the same time, or one after the other, or to one assigned to the selected word at a fixed distance in a certain sense of direction Word register takes place.

In an associative memory with a so-called fixed mask, the same set of binary digits of the word registers with the search argument compared. Memories of this type are used, for example, for the Address translation in storage systems with indirect addressing for Output of the true address used. Flexible organized associative memories have a mask register and a corresponding control ' circuit to find the number of binary digits and their To be able to vary the position of the word field.

However, these known associative memories have various disadvantages the most serious of which for many applications is limited microprogram flexibility.

It is now an object of the present invention, by avoiding Disadvantages of the known arrangements allow the range of application of associative memories to be expanded.

The solution to this problem is in the case of an associative memory system initially mentioned, characterized in that a mask memory with a plurality of mask data registers ^ is provided, as well Switching means for transferring the data content of one or more mask data registers into the mask register of the associative memory.

This makes the microprogram flexibility of a Docket UK, 68 015 009887/1827 easy

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such memory improved.

The advantages of a memory constructed in accordance with the invention become clear from the following detailed description, which, together with the accompanying drawings, the essence of the invention explained in more detail.

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On the drawings shows:

Fig. 1 schematically in a block diagram

Embodiment of an electronic digital data storage system;

Fig. 2 in a diagram a binary digit of the

Mask register of Fig. 1;

3 shows an arrangement of mask data in a

Mask memory;

Fig. 4 shows another arrangement of mask data in

a mask memory;

5 shows an embodiment of a storage system

with two memory groups and one mask memory each and

6 shows another arrangement of two memories

groups with one mask memory each.

The associative memory system shown in Fig. 1 comprises a multi-digit Associative memory 1 with a memory group 2, which has a plurality of word registers 2a, a data register 3, a mask register 4 and one

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Function control device 5-contains, - The data register 3 is to a Data bus 6-connected and the data transfer can be in in both directions between the memory group 2 and the data bus 6 via the data register 3, which is thus an input / output register the associative memory is used.

The associative memory 1 runs in a two-phase cycle. While the first or election phase are one or more word registers 2a selected associatively for access. Each word register 2a has a corresponding associated selection trigger (not shown) and is chosen by setting its election trigger to a given stable state. Be during the second or read / write phase of the cycle the selected word registers are controlled at the same time. Either the content of the data register 3 is then transferred as an input register in a write operation to each selected word register, or the content all selected word registers will be in a read operation which is handy is an OR operation on the contents of the selected registers to which Transfer data register 3 as output register. The term "transferred" here does not necessarily mean that the memory location from which Data are transferred here, at the time of the data transfer it is also deleted.

A word register 2a can be accessed as a result of an associative UK 9-68-015- _ 4 -

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Search operation in which a search argument in selected binary digits compared with the content of the word register according to the masking will be selected for addressing. The selection triggers of the word register in which data is stored with the search argument match are set in a given stable state. Word registers can also be accessed by a "next" or "previous" operation, possibly in connection with a search operation. In such a storage operation, the position becomes a each election trigger as a copy on the election trigger of the neighboring word register transferred to the word register during the "next" operation, which is further removed from the data register 3 and in the "earlier" operation on the word register, which is the data register 3 is closer. Either of these two operations, along with a search operation, results in the choice of one originally by the search operation selected registers of neighboring word registers in the specified direction. A "first hit selection" operation can also be used can be defined in such a way that if several word registers are selected at the same time by a search operation, only the selected register is activated which is closest to data register 3.

Each word register can also have more than "one selection trigger, e.g. one Primary trigger and a secondary trigger, and any of the operations described above can be performed with the first or second selection trigger

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will. An operation cycle can e.g. the operations "Search", "Next", "Read", "Primary" comprise and in this cycle the operations run "Search" and "Next" on the primary election triggers and the read operation takes place on the word registers whose primary election trigger in the given stable state. ■

In the circuit shown in Fig. 1 cause control signals from a Function control device 5 the execution of selected operations to be carried out in an operation cycle.

The associative memory 1 contains, as usual, a mask register 4. The mask register consists of a number of interlocking circuits (not shown in Fig. 1), which control the gates in the lines between data register 3 and memory group Z , whereby the positions of the interlocks selected binary digits of the data register are masked from the storage group. Such masking is necessary in order to obtain the necessary flexibility when selecting the field occupied by the search argument in a search operation. If the positions of the interlocks are denoted by one or zero, it has hitherto been common practice for the interlocks which are set to one to mask the data register during the first phase of the memory cycle and the interlocks which are at zero to mask the data register mask the second phase of the cycle. This arrangement has

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however, the disadvantage that the search argument and the addressed locations of a word register occupy exactly the entire word register and time is wasted if only certain ones are not occupied by the search argument Positions are to be addressed, or if, after a "next" operation, e.g. B. Bodies should be addressed that contain the search argument lock in. A more flexible arrangement is to use only the masking interlocks that are set to one and im Change the mask between the first and the second phase of a cycle.

The memory operations of the associative memory 1 are carried out by a Control memory 7 controlled, which outputs a sequence of control words which are decoded into control signals for the associative memory. In the German patent application P 19 31 966. 5 describes a data processing system in which a control memory similar to the Control memory 7 controls a plurality of associative memories by emitting a signal for each memory which indicates the operation to be carried out and when initiating a search operation specifies the mask to be used and at least part of the search argument. the Arithmetic and logic functions are carried out in accordance with the ones specified there Description is carried out in the associative memory by table search and the signal is not only used to activate the function which is to be carried out by entering a search argument through which the corresponding table can be addressed, but

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also to define the memory operation to be carried out yourself. To the So far, it has been possible to limit tax storage to a practicable size just define two masks and associate a given function with a given combination of memory operations. That means however, too great a restriction for the possibilities of the storage system, which is why the system has been improved according to the invention.

A mask memory 8 is now provided which has a number of mask data registers 8a, and the latching circuits of the mask register 4 can simultaneously select one or more of these mask data registers 8a can be loaded. The mask memory 8 is shown as an associative memory, but it does not need to be such. Each Mask data register 8a contains a mask data field 8b and a search field 8c. A mask memory 8 is a fixed mask and operation flow memory which operates to retrieve a search operation the search field 8c and performs a read operation over the data field 8d. A mask identifier placed on the search field 8c selects one of or a plurality of mask data registers for reading out to the interlock circuits of mask register 4. As with associative memory 1, there is a Read operation on more than one of the selected registers is equivalent to an OR operation with respect to the data in the selected ones Registers.

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The memory system also includes a function memory 9 of the same type like the mask memory, which is a series of function data registers 9a, each with a search field 9c and a function data field 9b. The function data fields of selected data registers 9a supply input signals to the function control device 5.

The mask memory 8 can be operated so that it has a mask for supplies each cycle of the associative memory 1, but it should preferably output a mask on the alifang of each cycle phase. Of the Control memory 7 thus gives four control codes for driving the in Fig. 1 shown storage system. Each control word register 7a des Control memory s 7 has license plate fields 7b - 7e. The license plate field 7b is the first mask tag field and contains the search argument which is the one to be used in the first phase of the memory cycle Mask called. It is connected to the search field 8c of the mask memory 8 via AND elements, which are symbolically represented by the AND gate 10 are shown. The identifier field 7c is the second mask identifier field which is used in the second phase of the memory cycle The mask to be used is designated. It is via AND elements, which are symbolically represented by the AND element 11, with the search field 8c of the mask memory 8 connected. The identifier field 7d is the search character field that is associated with a fixed search field 2b of the storage group 2 is connected. The code field 7e is the function code

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character field, which is connected to the function memory 9.

The search identifier defines the arithmetic or logic operation, which is to be executed during a memory cycle in which there is at least specifies part of the identifier which the in the storage group 2 designates the table position suitable for the operation. The search identifier generally does not contain the entire search arguent for storage group 2. It can, for example, specify the table and operands in data register 3 then complete the search argument for designating the special entries in the table. ■. .

The control memory 7 can also be a non-associative memory, in which the control words under the control of an instruction counter can be addressed, or the control store can be an associative store with above-mentioned means for memory operation "choice next memory word ", whereby the control words in sequence can be addressed. The control memory can also have several associative memories 1, and then there must be flag fields 7b-7e for each of the memories.

In operation of the system shown in Fig. 1, the control store 7 is on At the beginning of the first cycle phase of the associative memory 1 a control word which contains the Kennzcichenfeider 7b - 7e. During the first phase

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the line Cl is energized and thus the first mask identifier fcld 7b. switched through to the search field 8c of the mask memory 8, namely in a search and read operation as a search argument, which is the transmission a mask to be used in the first cycle from memory 8 to the Mask register 4 causes. The content of the function identification field 7e is on the search field 9c of the function memory 9 in a search and Read operation directed as a search agent. That leads to transmission • a data word which is the one to be executed during the current cycle

^ Function defined, from the function memory to the decoder of the function control device 5. The content of the search code field 7d is given directly as an input to the code field 2b of the memory group 2, where it can be used as part or as a whole search argument in a search operation on the word registers 2a of the memory group 2 can, if the functions defined by the function identifier field 7e require this. For a simple access operation on a given Word register can be the search identifier field 7d the register

_ fully identify. If the associative memory 1 has a link

or arithmetic operation with the help of data in the storage group. 2 existing function tables is to be carried out, identifies the search indicator field 7d in general the table to be used, and data in register 3 complete the search argument by defining certain ones Entries in the table. The input data can also be used to complete a partial identification of a table

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that was returned by the search code field.

During the second cycle phase, the line Cl is switched off and the Line C2 switched on, whereby the content of the second mask identifier field 7c via the AND element 11 to the search field 8c of the mask memory 8 is transmitted. The mask memory 8 then gives a mask for the second phase. The use of two masks is desirable there where the search argument and the data to be addressed together do not completely occupy a word register Ea of memory group 2. But when the selected word register contains data other than a search argument which should not be addressed or if the to addressing data are in another register that precedes or is behind the register selected by the search argument, and if this data must occupy at least some of the same binary digits in the group as the search argument in the first and second cycle phases different masks are used »The use of two masks it naturally entails that the mask memory 8 is in a search and read operations must work much faster than the associative memory 1. This is generally also the case, since the complexity of an associative memory is a determining factor for determining the Cycle times when designing a system. The mask memory 8 is significantly smaller than the associative memory 1 and can therefore also be significantly designed to work faster.

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A circuit diagram of a binary digit of the mask register 4 is shown in FIG. 2 shown. It is assumed that a binary number is given by the combination of states the potential is shown on two bit lines. the The binary digit of the mask register 4 shown in FIG. 2 is the same Binary digit of the input / output register 3 through the bit lines Zl and 22 and with the same binary digit of each location register 2a Group 2 connected by bit lines 23 and 24. In order to carry out a write or search operation in the binary digit, the potentials on lines 21 and 22, correspondingly to lines 23 and 24 switched through while to perform a read operation in the Binary place the potentials on the lines 23 and 24 to the lines 21 or 22 are switched through. A first AND element 25 has corresponding input lines. A line 26 is energized when a mask lock 27 is at one and a line W / S becomes energized when a write or search operation is commanded by the decoder of the function controller 5 (Fig. 1). Another AND element 28 has corresponding input lines, namely the line W / S, the line 26 and the bit line 22. The outputs of the AND gates 25 and 28 are connected to the bit lines 23 and 24, respectively. Thus, in a write or search operation, the potentials become the bit lines 21 and 22 are switched through to the lines 23 and 24, respectively, and only when the lock 27 is set to one.

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Another AND element 29 has corresponding input lines like line 26, bit line 23 and a line R that is energized, when a read operation is commanded by the decoder of the function controller 5. Another AND element 30 has inputs line 26, bit line 24 and line R on. The outputs of these AND gates 29 and 30 are correspondingly connected to the bit lines 21 and 22 connected. The potentials on the bit lines 23 and 24 are switched through to lines 21 and 22 in the event of a read operation, and only when the locking circuit 27 is at one.

A corresponding locking circuit 27, which is connected to a corresponding line 31 of the mask register 8, belongs to each binary digit of the mask register 4. The line 31 is connected so that when the line is excited, the interlocking circuit assumes the position one. A branch 32 of the line 31 is led via an inverter 33 to the locking circuit 27 that this assumes the position zero when the line 31 is switched off. Each line 31 is connected to a corresponding binary digit of the mask register 8 and is energized when the binary digit of the mask register outputs a binary one as a result of a search and read operation. ^f

So far, an arrangement has been described «in which a mask into the Mask register 4 corresponding to a '<selected from mask memory 8

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Data word is set.

The system described so far works satisfactorily if the data are stored in the mask memory 8 in binary form. The size of the Mask memory can, however, be significantly reduced if the search field 8c contains memory cells, the three states, namely one binary one, a binary zero or the state X can take. In the last-mentioned state X, the cell does not give a signal for disagreement even if any interrogation signal is applied to the cell during an associative search operation. Thus, an im The cell located in state X has no negative influence on whether a Word register is selected for access. Such cells, which can assume three possible states, the size of the Mask memory can be greatly reduced. For example, Fig. 3 shows the contents of four mask data registers 8a of the mask memory 8. The X state is only used in search field 8c. The effect of the pattern of X and 1 states shown as an example is such that every binary digit of the search argument linked to a corresponding mask pattern and that any combination of patterns can be selected, taking into account that the output signal of the mask memory the OR function of the chosen words is if more than one word is chosen '. For example, if the search argument is 1001, the selected Mask thus 1111 0000 0000 1111.

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According to the illustration in FIG. 4, this idea can be expanded in this way that mask groups and from the group further a mask combination can be chosen. The two extreme left binary digits of the search argument determine from which group the desired mask is to be selected. The selection of the mask combination to be used is determined by the other digits of the search argument, • which can also assume the X state.

The planning of a single mask memory 8 for each of several <

Associative memory 1 can be combined with the planning of one ■ common function memory 9 for all associative memories 1. The. Using different masks can lead to different interpretations of the same search argument by different memories and thus to different ones perform functions or logic operations to be carried out. · · ■

Such an arrangement is shown schematically in FIG. Among the associative i save 50, 51 include respective memory groups 52, 53, data registers 54, 55, and mask registers 56 and 57. The mask memory 58 controls the mask register 56 and the mask memory 59, the mask register 57, the data register 54 and 55 are as input register both connected in parallel to a data bus line 60. The same function control digits are sent to the associative memory via the line 61

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50 and 51 are given and the same mask identifiers are given to mask memories 58 and 59 via line 62. The signals on line 61 can come from a function memory 9 or directly from a control memory 7. The same mask identifiers in the mask memories 58 and 59 do not necessarily designate the same mask, and thus the same data word on the data bus 60 can be interpreted differently by the associative memories 50 and 51. The data can contain function bits which supplement the function signals on the line 61 and different memories can then mask out different function bits with the result that different functions are carried out in the memories. Alternatively to. or in conjunction with function bits, the data can contain a multi-character word and each memory is masked to perform an operation on a different character. In certain applications, such as real-time process control, for example, parallel addition in several associatively organized memories, such as 50 and 51, may be desirable instead of serial addition in such a memory.

The arrangement described so far can be modified to the effect that that mask memories contain different mask identifiers and that the non-selection of a mask results in one of the memories 50 or

51 is not performing any operation. Since choosing a mask is putting a

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Election triggers, the election can easily be effected by that at the end of the search phase of a mask memory it is determined whether a selection trigger has been set, and if this is not the case, a Signal for "No operation" generated and sent to the function decoder (Fig. 1) given, which overrides all other function signals.

Another possible application of a mask memory for each associative memory can be found in the serial connection of memories, as shown in FIG. Parts of the same type are provided there with the same reference symbols as in FIG. 5. The associative memories 50, 51 in Fig. 6 are modified from those in Fig. 5 to the effect that that they have two data registers. Data is from the data collector 60 on the corresponding to the signals from the mask memory 58 masked associative memory 51 given and by a Table search in storage group 52 according to the search argument in the data register 54 and the function control signals on the line 61 processed. The result is then via the second data register 54a is passed to the first data register 55 of the associative memory 51 and from there in accordance with the signals from the mask memory 59 masked to the storage group 53, where another table search is carried out before the end result is sent to the data collection line 70 via the data register 55a.

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The connections between the data registers 54a and 55 do not need exist between the same binary digits of the two registers. As indicated schematically by the cross connection of the two register parts any connection pattern can be used. The serial arrangement shown in Fig. Is particularly suitable for additions that can be imagined in two steps: First a partial total is generated with transfers, and then the transfers are converted into the partial total added into it. The associative memory 51 is arranged for this application example in such a way that it only stores the transfers in the Adds data that it receives from the associative memory 50. The associative memory 50 can also be used for other functions be designed as just the first addition step. That's why it's through Double arrows between this memory and the data collector line 60 6 shows a two-way connection. The additional associative memory 51 is only used when performing an addition, which can be achieved, for example, by setting the associative memory 50 in such a way orders that this only output signals during an addition operation to the data register 55, and that an empty register 55 denotes the second associative memory 51 indicates a "no operation" cycle.

In Fig. 6, the two data registers of each memory group drawn on opposite sides to facilitate the flow of data of storage groups to show. Two arrangements of mask registers

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are possible when two or more data registers are used. In In one arrangement, only one mask register is used and the data paths between the data registers and the storage group all run through the mask register. A mask is output to the mask register, either in each. Cycle or any phase of the cycle description above, and the selection of the data register for the data transfer is controlled independently. In the other arrangement, a mask register is associated with each data register, and each time the Registers are to be loaded, as many masks are output from the mask memory as how mask registers are available. Masking makes data registers or parts thereof for data transmission or use selected as search arguments in a search operation. Although those related to the ITig. 1-5 storage systems described only have one data register, several data registers can also be used there be provided and all masking methods described are used.

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Claims (9)

PATENT CLAIMS Associative memory system with at least one multi-digit associative memory which is an associatively controllable memory group contains a plurality of word registers and at least one data register and one mask register, characterized in that that a mask memory (8) with a plurality of mask data · = registers (8a) is provided, as well as switching means for the data content to transfer one or more selected mask data registers (8a) into the mask register (4) of the associative memory (1). 2. Associative storage system according to claim 1, characterized in that that in the word registers (2a) and the data register (3) the same binary digits nail one another according to the mask register (4) are connectable. 3. Associative storage system according to claim 1, characterized in that that the switching means for transmitting the data content is selected Mask data register (8a) of the mask memory (8) into the mask register (4) of the associative memory (1) at the beginning of both the selection phase and the read / write phase of the memory cycle are effective. 4. Associative storage system according to claim 1, characterized in that that the mask spearer (8) is also associatively 009887/1827 Docket UK 968 015 - 22 - 2nd July 1970 «3 and access to the selected mask data register or registers (8a) is carried out by an associative search operation. 5. associative storage system according to claim 4, characterized in that that each mask data register (8a) with a selection trigger is connected, which can be set to one of its two stable states when the associated mask data register has been selected associatively, and that circuitry is provided for sensing the assumed state of the selection triggers are. 6. Associative storage system according to claim 1, characterized in that that in the mask memory (8) memory cells are present which can assume three stable states, which the Binary values zero and one, as well as a neutral X-state correspond, Wherein the neutral state has the effect, regardless of the search argument, that the selected memory cell does not have a signal which means non-compliance. 7. associative memory system according to claim 1, characterized in that that several associative memories (50, 51) cooperating with the same data bus line (60) are present are each with a mask register (56, 57) and with an associated mask memory (58, 59) are equipped. 009887/1827 Docket UK 968 015 - 23 - 2nd July 1970 8. associative memory system according to claim 1, characterized in that that a control memory (7) with a plurality of control word registers (7a) is provided. 9. associative storage system according to claim 1, characterized in that that the control memory (7) is organized associatively. 009887/1827 Docket UK 968 015 Blank page