DE2016443B2 - ASSOCIATIVE MEMORY - Google Patents

Description

The invention relates to an associative memory with a mask register, the data content of the Memory containing word registers and search word registers according to the preamble of claim 1.

Associative memories are known (K. Steinbuch. Taschenbuch der Nachrichtenverarbeitung, Springer-Verlag 1962, page 522). In such a memory there is a data memory whose data can be accessed is exercised according to its content and not. As with a non-associative memory, according to its Storage location where the data is located. A typical associative memory consists of an input / output register, a mask register and word registers which contain the data in the memory. There is a in the input / output register Search argument which usually only occupies part of this register. The mask register is masked the part of the input / output register not occupied by the word registers by the search argument. It a search operation is then carried out in which the search argument is matched with the content of the same places in the Word registers in which the search argument also is in the input / output register. If the search argument is the same, the word register usually by setting a selection trigger marked, which then represents a predetermined stable state in the register. Then takes place on the an access operation takes place on the marked register. It is then either the content of the input / output register written in the marked registers or the contents of the marked registers are sequentially or read into the input / output register at the same time.

In addition, GB-PS 987 666 provides an associative memory with two input registers, which are used as search word registers serve, known. These two registers are used to create keyword arguments of variable length and are interconnected for this purpose and designed as shift registers. These Both shift registers and the information or search words contained therein are controlled by a control circuit controlled in such a way that one of the two registers always has access to the memory without the other disturb.

However, this known type of associative memory only has one data path to the outside if it also with the last-mentioned associative memory due to the presence of two input registers is possible to create two entry paths. However, since these ίο registers are not used as input and output registers serve, but clearly only as a search word or search argument register. still exists Narrowing of the data flow from the associative memory to the other units within a data processing system.

The invention is therefore based on the object of creating an associative memory that both on the input side as well as work faster on the output side with the units of a data processing system can than the previously known.

The solution according to the invention consists in the characterizing part of claim 1.

Because there are several input / output registers, there are now too in the interface the other units within a data processing system no longer have bottlenecks because the existing Registers can be loaded separately from one another and read separately from one another which means that the times for the input and output of both search terms as well as the searched data can fully overlap in time. This is particularly of great advantage, when using associative memory with a large storage capacity in which databases are stored. The traditional associative memory is able to make a parallel comparison of all stored data with that in the search word register to carry out the standing search argument, possibly even with two search arguments, however it is not able to output the data found overlapping or even in parallel, but rather the data found Data are queried and output one after the other. With the present solution, that problem is solved.

The invention is illustrated in detail with the aid of exemplary embodiments and the associated drawings explained. It shows

1 shows a form of the associative memory according to the invention,

2 shows a further form of the associative memory according to the invention,

Fig. 3a is a logic diagram of typical locations in the input mask register shown in Fig. 2,
Fig. 3b is a logic diagram of typical locations in an alternative form of the mask register;

Fig. 3c is a pictorial representation of a memory cell for the mask register of Fig. 3b,

Figures 4 and 5 Modifications of the mask register: Figures 3a and 3b and

Fig. 6 shows an arrangement of associative memories according to the invention.

In the figures, data paths are through thick and <

Control signal paths are shown by thin arrow lines. According to FIG. 1, there is an associative memory 1 au a memory arrangement 2 with a multiplicity of word registers, each covering the entire arrangement are stretched, from an input / output register 1/01, an input / output register 1/02 and a

Mask register 3. Switch between register 1/01. ^{1 of} a data collecting line 5 there is a data path 4 for both directions and between the register 1/02 and a data collecting line 7 there is a similar data path 6 for both directions. Two-way data paths 8 and 9 connect the corresponding register 1/01 or 1/02 to the masking register 3, which in turn is connected to the memory arrangement 2 via the two-way data path 10.

Although the invention is based on a passive associative memory can be applied, which is acted upon by control signals from external sources, is the In Fig. 1 shown memory a functional memory in which a part of the memory input for determination the operation to be performed by the memory is decoded. The associative memory contains accordingly 1 a decoder 11 which is transferred from register 1/01 via data path 12 and from register 1/02 via the data path 13 receives data. From the decoder 11 control signal lines 14 to 19 go out, whose Purpose will be explained later.

For a better understanding of the invention, the mode of operation of the associative memory 1 will first be described only written when using register 1/01. From the collecting line 5 a is via the data path 4 Word transferred to register 1/01. Part of the word contains data that is stored in the associative memory 1 define the operation to be carried out and is scanned by the decoder 11, which as a result a control signal is applied to line 14, which defines the mask to be used, and other control signals to lines (not shown) inside the memory array that carry out the operation define. An operation consists of two cycles, in the first of which one or more word rules ster of the memory array 2 to be accessed to be selected and in their second, an access operation, read or write, is performed on the selected word registers will. The selection of a word register need not be the result of a comparison between an input search argument with the content of the word register - a search operation - can take place, however with reference to word registers selected in previous operations. Thus, following the registers selected in a previous operation, the next tab can be selected. However, it is assumed that the operation to be performed is a search operation. It is further assumed that only two mask configurations can be carried out and that a single binary signal on line 14 is sufficient for the mask configuration to be used can define. With the first mask configuration, for example, the content of the eight left digits of register 1/01 are used as a search argument and access is only available to the remaining digits of the word register, and with the second mask configuration, for example, the content of the left 16 digits of register 1/01 as search argument is used and access is only exercised to the remaining positions in the word register. Assume that the search, read, mask 1 operation has been requested. In the first cycle the content of 1/01 is over the data path 8 is transferred to the mask register 3, but since mask 1 is requested, only the left eight digits via data path 10 for comparison with the left eight digits of each word register the memory arrangement 2 transferred. The selection trigger in each word register in which the comparison Equality is set. In the second cycle, the state of the selection trigger is sensed and the contents of those registers that have set their selection trigger are transmitted via the data path 10 is read out to the mask register 3, which contains all digits except the eight on the left via the data path 8 after 1/01 transmits. The content of 1/01 will be

ίο then via data path 4 to collecting line 5 transfer.

In contrast to known associative memories, the associative memory 1 according to the invention has a second input / output register 1/01, and either 1/01 or 1/02 can be used. Especially in the With regard to the embodiment shown in Fig. 1, the decoder 11 creates control signals, whereby the search argument can be taken from either 1/01 or 1/02. Furthermore, in the second

ao cycle an operation from either 1/01 or 1/02 written to memory array 2 or read from memory array 2 in either 1/01 or 1/02 will.

This is effected by the control signals on lines 15 to 19 from decoder 11. When energized, line 15 connects data path 8 via marker register 3 to data path 10. When energized, line 16 connects data path 9 via mask register 3 to data path 10. When energized, line 17 enables register 1/01 from which Memory arrangement 2 to receive data. When energized, the line 19 enables the register 1/02 to receive data from the memory arrangement 2. When energized, line 18 enables both registers 1/01 and 1/02 to receive data from data lines S and 7, to which they are connected via data paths 4 and 6.

The decoder 11 is not described in detail here, as its use is well known. The decoder 11 consists of, for example, one Christmas tree network with four lines including the data path 12 or 13 as input and with 16 lines as output, one of which in accordance with the binary signals on the input lines is designated. The marked output then sets triggers which, at the appropriate times, the Excite control lines 14 to 19.

Using these control signals, it can be seen that the following sequence of operations is possible is:

1. Put 1/01 and 1/02 on the data bus 5 or 7;

2. Search using the search argument from 1/01 or 1/02;

3. Read or write between the selected word registers of the arrangement and 1/01 or 1/02; and

4, Read 1/01 or 1/02 on the data collector. FIG. 2 shows an associative memory 20 according to the invention which is different from that described in FIG. 1 Memory 1 has been modified so that the memory 20 is the mask between the search and Can change the access cycles of an operation. The individual mask register 3 of FIG. 1 is represented by an input or search argument mask registers 23 and two output mask registers 24 and 25 replaced. the 1/01 and 1/02 registers are divided by registers 21 and 22, which only serve as input registers. the

Output from the memory arrangement 2 occurs via the data path 26 and either via the mask register 24 and the data path 27 to the bus 5 or via the mask register 25 and the data path 28 to collecting line 7.

To simplify the drawing, the control lines from the decoder 11 have not been shown, it however, it can be seen that the decoder 11 sends out signals indicating the mask configuration for the mask register 23 specify from which register, 21 or 22, the search argument must be taken and whether the operation is a read operation in array 2, which register, 24 or 25, the data must be transferred to the associated bus line 5 or 7 and which mask is to be used. The ability to define which data field is to be transmitted on the bus is natural useful when several associative memories 20 are connected to a bus. Everyone Memory can simultaneously and independently with different characters of a multi-character information work, and the use of non-overlapping output masks for different memories causes a result that is aimed at the respective mask and at the same time on the manifold is.

In Fig. 3a typical locations of the mask register 23 are shown for the case in which the memory arrangement 2 consists of binary memory cells. It is assumed that only two masks are used: mask 1, in which the search argument goes beyond digits 0 to 7 of register 23, counting from the left and writing to memory array 2 using the remaining digits, and mask 2 , in which the search argument goes beyond the positions 0 to 15 of the register 23 and the writing into the memory arrangement 2 takes place by means of the remaining positions. In FIG. 3a, line 10o is a typical line from locations 0 to 7 of data path 10, line 106 is a typical line from locations 8 to 15, and line 10c is a typical line from higher positions. The lines 8 «to 8c are corresponding lines of the data path 8 from the input register to the mask register 23, and the lines 9a to 9c are corresponding lines of the data path 9 from the input register 22 to the mask register 23. The meaning of the control lines on the right in Fig. 3 is as follows:

Line 14: mask information; if line 14 is energized, use mask 1, otherwise mask 2;

Line 15: when energized, use data from register 21;

Line 16: when energized, use data from register 22;

Line S: when energized, perform a seek operation;

Line W: when energized, perform a write operation, ie transfer data to the memory array 2;

Line Cl: when energized, it indicates cycle 1 time;

Line C2: when energized, it indicates cycle 2 time.

When the line 15 is energized, the AND circuits 31a to 31c are permeable and the binary data on the lines 8a to 8c are transmitted via the OR circuits 33a to 33c as inputs to the AND circuits 34a to 34c. Be on similarity Liche manner when the line is energized sixteenth the AND circuits 32a to 32c are transparent and the binary data on the lines 9a to 9c are transmitted through the OR circuits 34a to 34c. The line 14 has a branch 14a and an inverter 35. When the line 14 is not energized the output line of inverter 35 is energized and produces a signal A / 2, indicating that mask 2 is to be used.

With the assumed operating conditions, only search argument data are on the lines 10a, there Both masks 1 and 2 go beyond positions 0 through 7 of the mask register and the line will not used for transferring data for a

• 5 write operations. Accordingly, the inputs of the AND circuit 34a are the data output dei OR circuit 33a, line 5, line Cl - since eir in the first cycle of the two-cycle operation Search takes place. It is not necessary to use mask

To specify ao data, since both masks 1 and 2 require the line 10a in a search operation.

On line 10 b there are search argument data under mask 2 and write data under mask 1. The AND circuit 36 has the control

as lines Cl, S, and 14a. Its output is connected via the OR circuit 38 to the input of the AND circuit 34 b . Furthermore, the control lines C2, W and 14 are inputs to an AND circuit 37, the output of which is connected via the OR circuit 38 to an input of the AND circuit 34 £. The AND circuit 36 is energized when the line 10 b should lead search argument data and the AND circuit 37 is energized when the Lei device 10 b should lead write data. The line 10 <

only carries write data and so the AND circuit 34c has a data input from the OR circuit 33c and control inputs from the lines W unc

Fig. 3b shows the modifications of the mask regi stcrs of FIG. 3 a, when the memory arrangement 2 au; Memory cells with three types of states exist. Every Memory cell can assume stable states that represent binary 1, binary 0 and X. The X state is so that the cell does not signal a state of emergency

siert which query signals ever during a an associative search operation has been applied to them. For example, a cell can have the configuratioi have according to Fig. 3c. The electronic circuit of which the memory cell SC consists is between

a processor line 131 and a word line 132 and between a bit line pair L and R. DU cells SC of the same word have common collector and word lines 131 or 132, whereas the cells for the same position are different!

S ₅ keepers have common L and R bit lines. For interrogation of the cell SC for the binary 0 state, the potential on the bit line L is lowered relative to an external voltage and the potential on the bit line L is increased. If the cell SC is not

ίο is in the binary 0 or in the X stable state word line 132 carries current, indicating an exception condition. To get a binary 0 ii to write the cell, the same potential) as when interrogating the cell to the bit lines

(S ₅ sets, but the signals of the collector line 131 and the word line 132 are varied, so that the potentials on the bit lines disturb the status of the cells and cause the cell to become stable

(ο

assumes binary Ü status. By exchanging the potentials on the bit lines, the cell can be queried for a binary 1 or a binary 1 can be written into the cell. In order to write an X into the cell, the potentials of the gate line 131 and the word line 132 are matched to those of a write operation, and the potentials of the bit lines are raised relative to the reference voltage. In the case of a cell which consists of two bistable circuits, it is not necessary for the raised bit line potentials to be applied simultaneously. Accordingly, an X is written in two operations. During the first operation, a binary 0 is set in the input register and is written with the bit line L masked. In the second operation, a binary 1 is set in the input register and is written with the bit line R masked. The first operation is called right write and the second is called left write.

In Fig. 3b parts of the same locations of the mask register 23 are shown as in Fig. 3a. The AND circuits 34 'to 34c in FIG. 3a are replaced in FIG. 3c by pairs of AND circuits, each AND circuit controlling a driver, not shown, for a corresponding bit line. In Fig. 3b the output of the OR circuit 33 "is inverted and connected as an input to the AND switch 134" and is also connected in its real form as an input to the AND switch 135 ". Next "; inputs to the AND switches 134" and 135 "are the signal lines C1 and S from the decoder, which, when energized, indicate that the cycle is 1-digit and a search operation is required 0 is to be searched for, the output of the AND switch 134 "is pressed and the output of the AND switch 135" is not energized corresponding potentials are applied to the bit lines.

An inverted output of the OR circuit 33 /> is connected as an input to the AND switches 13461 and 13462 and the real output of the OR circuit 336 is connected as an input to the AND switches 135M and 13562. The lines / V / 2, Cl and "are connected as inputs to the AND switches 13462 and 13562. The lines Mi and C'2 are connected as inputs to both AND switches 13461 and 13561 with the word line WL , the thin is energized when a write left operation is required or are connected to AND switches 13461 and line WR , which are energized when a write right operation is required, and both lines WL and WR are energized when The outputs of the AND modules 13461 and 13462 are inputs for an OR module 136, the output of which controls the potentiometer on the bit line / .. The OR module 137, which is connected to the outputs of the AND modules 13561 and 13562 serves a similar purpose for bit line R.

An inverted output of OR gate 33r is connected to the input of AND shoulder 134c, and the real output is connected to the input of AND shoulder 135c. The line C'2 is connected to the inputs of both AND shoulders 134c and 135c , the line WL leads to the input of the AND switch 134c and the line WR to the input of the AND switch 135c.

The mode of operation of the mask register in FIG. 3b is analogous to that of the register in FIG. 3 a and will therefore not explained again.

3a and 3b accordingly show how the data is selected from either register 21 or register 22 and as a search argument in a

ίο Access operation or used as a source of data which are to be written into the memory arrangement 2.

The invention is not limited to having the entire search argument from a single register must be taken. The search argument can result from data in two or more input registers be translated that non-overlapping fields of the input register are hidden or that in AND, OR or EXCLUSIVE-OR operations overlap fields of the register logically be combined.

Fig. 4 shows the modification of the circuit of Fig. 3 required for this logical combination and further shows a single digit of the left eight digits of the mask register 23. About the circuit 3 in addition, the data lines 8 and 9 with the inputs of an OR circuit 41 and an AND circuit 42 is connected. The output of the OR circuit 41 is connected to the input cinci AND circuit 43 connected, which has a control line 44 as a further input. The exit de * AND switch 42 is connected to the input of an AND switch 45, which is also another Input has a control line 46. Lines 15 and 16 remain de-energized and around the OR function of the data on lines 8 and 9 to the OR circuit 33, becomes the control line 44 energized and the AND function of the data aul the lines 8 and 9 to the OR circuit 33 to transmitted, the control line 46 is energized. The Stcucrleitungcn 44 and 46 are optionally through Signals from decoder 11 in the same way how the lines 15 and 16 are energized. To the OR circuit 41 and the associated control line 44 can be omitted, in which! 'All the output the OR circuit 33, the OR-l -unktion dei Represents data in the two input registers. The EXKI.USIV-ODHR function can be activated by adding an EXCLUSIVE-OR circuit in parallel with i AND circuit 42 and OR circuit 41 can be achieved.

Fig. 5 shows the modification of the circuit of Fig. 3 which is used for blanking out non-overlapping fields from both input registers

is required as a search argument in a search operation. Positions 0 to 15 of mask register 23 are subdivided into groups of four, since the size of a character usually amounts to 4 bits, and separate control lines 15 "to XSd and 16a to 16a ¹ blender About the AND switches 34 (see Fig. 3) jcdei Job group uus. The control line 15a is input to all AND switches 31 (see FIG. 3) Make O to 3 of the muscular register connected and the Control line 156 leads uls input to zero AND

Shoulders 31 of the positions 4 to 7 of the muscle regulator and similar it is with the control lines 15c and 1 $ d. The control line 16a is an input with all I IND-Schnltcrn 32 of the positions O to 3 of the mask back.

700 628/191

ίο

j; isters connected and it is similar with the control lines 166 and 16d with regard to the positions 4 to 7, 8 to 11 and 12 to 15. The control lines 115 and 16 of FIG. 3 are omitted. With the arrangement of FIG. 5, various combinations of the fields from the input register to the mask register can be masked out by selective excitation of the lines ISa to ISd and 16a to 16a ″, e.g. the lines 15a, 15b, 16c and 16d by the decoder JIl The arrangement of FIG. 5 can be combined with the arrangement of FIG.

The input registers of an associative memory according to the invention do not need as it is graphically in Figures 1 and 2 to be as wide as the memory array. For the different Different registers can be made available to fields of the arrangement. One embodiment in this technique is shown in FIG. 6, in which the associative memory array 61 via the register 62 with the bus 63 and via the register 64 with the bus 65 is connected. A second associative memory array 66 is connected to the bus via register 67 63 and connected to the bus 65 via the register 68. The memory arrays and Registers are part of the memories as described in connection with FIGS. Insubstantial Elements have been left out. The registers 62 and 64 and the register 67 pass over

ίο the digits 0 to 7 of the corresponding memory arrangements 61 and 66 out. The register 68 extends beyond the positions 8 to 15 of the memory arrangement 66. With the arrangement shown, data that are in the same locations of memory 61 can be aligned are aligned with adjacent groups of digits in memory 66. A first group of 8 bits is from memory 61 to memory 66 via registers 64 and 67 and a second group of 8 bits transferred via registers 64 and 68 to the same word register of arrangement 66 as the first group.

In addition 5 sheets of drawings

Claims (3)

Patent claims: 1. Associative memory with mask register, word registers containing the data content of the memory as well as search word registers, the effectiveness of which is controlled by a control circuit, characterized in that the mask register (3, 23) is a selected logical combination of search arguments from several input registers (1/01, 1/02), which are used simultaneously as output registers serve, provides and that the aas the memory (2) read out data selectively in a of the aforementioned registers are transferrable. 2. Associative memory according to claim 1, characterized in that the mask register (3 or 23) different fields of the search argument from different input registers (I / Oi, 1/02) fades out. 3. Associative memory according to Claims 1 and 2, characterized in that the output field the data read out from the memory (2) is determined by output mask registers (24, 25).