DE2016443A1 - Associative memory - Google Patents

Description

IBM Germany Internationale Büro-Matchinen Gesellschaft mbH

Boeblingen, April 6, 1970 ko / you

Applicant: International Business Machines

Corporation, Armonk, N.Y. 10504

Official file number: New registration

Applicant's file number: Docket UK 968 014

As s ο zi ative memory

The invention relates to an associative memory with input / output register, Mask registers and word registers containing the data content of the memory.

Associative memories are known (K. Steinbuch, Taschenbuch der Nachrichtenverarbeitung, Springer-Verlag 1962, page 522). In such a memory there is a data memory, the data of which are accessed according to their content and not, as in the case of a non-associative memory, according to their memory location in which the data are located. A typical associative memory consists of an input / output register, a mask register and word registers which contain the data of the memory. The input / output register contains a search argument which usually only occupies part of this register. The mask register masks the part of the input / output register not occupied by the word registers by the search argument. A search operation is then carried out in which the search argument is compared with the content of the same positions in the word register.

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in which the search argument is also in the input / output register. If the search argument is identical, the word register is usually marked by setting a selection trigger, which is then entered in the register represents a predetermined stable state. An access operation then takes place on the marked registers. Either the content of the input / output register is then written into the marked registers or the content of the marked ones Register is read into the input / output register one after the other or at the same time.

This known type of associative memory has only one Data path to memory. The interface between the memory and the rest of the data processing system is the only input / output register. However, this has the disadvantage of greatly narrowing the original scope of work Associative memory connected, especially if the memory for more extensive and flexible operation possibilities than the only passive information store has been developed.

The invention is now based on the object of an associative memory to create the type mentioned, in which this Kachteil is avoided.

This object is achieved in that the associative memory consists of several input registers which are used in associative memory access operations contain used search arguments, and from a control for the selection of one or more input registers as a source of a search argument.

In this way, the advantage of greater flexibility of the memory is achieved without any loss of functional reliability.

The invention is based on exemplary embodiments and associated Drawings explained in detail. Show it:

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3 Fig. 1 shows a form of the associative memory according to the invention;

2 shows a further form of the associative memory according to the invention;

FIG. 3a shows a logic diagram of typical locations of the in FIG

input mask register shown;

Fig. 3b is a logic diagram of typical locations of an alterna-. tive form of the mask register;

Fig. 3c the pictorial representation of a memory cell for

the mask register of Fig. 3b;

Figs. 4 + 5 modifications of the mask register of FIGS. 3a and

3b and

6 shows an arrangement of associative memories according to the invention.

In the figures, data paths are shown by thick arrow lines and control signal paths are shown by thin arrow lines.

According to FIG. 1, an associative memory 1 consists of a memory arrangement 2 with a plurality of word registers, each of which has the whole arrangement are extended, from an input / output register I / O1, an input / output register I / O2 and a mask register 3. Between the register I / O1 and a data collecting line 5 there is a data path 4 for both directions and between the register 1/02 and a data collecting line 7 there is a similar data path 6 for both directions. Connect two-way data paths 8 and 9 the corresponding register I / O1 or I / O2 with the mask register 3, which in turn is connected to the memory arrangement 2 via the two-way data path 10.

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Although the invention can be applied to a passive associative memory to which control signals from external sources are applied, the memory shown in FIG. 1 is a functional memory in which part of the memory input is decoded to determine the operation to be performed by the memory will. Correspondingly, the associative memory 1 contains a decoder 11, from the register 1/01 via the data path 12 and from Register 1/02 receives data via data path 13. From the decoder 11 run out of control signal lines 14 to 19, the purpose of which will be explained later.

For a better understanding of the invention, the mode of operation of the associative memory 1 will only be described when the register is used 1/01. From the collecting line 5 is via the data path 4 Transfer a word to register 1/01. Part of the word contains data defining the operation to be performed by the associative memory 1 and is sampled by the decoder 11, which as a result, a control signal is applied to line 14 which defines the mask to be used and no further control signals Leads shown inside the memory array that define the operation to be performed. An operation consists of two cycles, in the first of which one or more word registers of the memory arrangement 2 to which access is to be exercised are selected and in the second of which an access operation, reading, is selected or writing is performed on the selected word registers. The selection of a word register does not need to be a result a comparison between an input search argument and the content of the word register - a search operation - can take place however, must be performed with reference to word registers selected in previous operations. Thus, following the registers selected in a previous operation, the next registers can be selected. It is assumed, however, that the operation to be performed is a search operation is. It is further assumed that only two mask configurations are feasible and that a single binary ·· signal on the

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Line 14 can sufficiently define the mask configuration to be used. With the first mask configuration, for example the content of the eight positions on the left of the register I / O1 as Search argument is used and access is only exercised to the remaining positions of the word register, and with the second mask configuration For example, the content of the left 16 digits of the register Ϊ / Ο1 is used as a search argument and access is only to exercised the remaining positions of the word register. Assume that the Find, Read, Mask 1 operation has been requested. In the first cycle, the content of I / O1 is transferred to mask register 3 via data path 8, since mask 1 is requested is, only the left eight digits are transferred to the data path IO to Transferred comparison with the eight positions on the left of each word register of the memory arrangement to the memory arrangement 2. The selection trigger is set in every word register in which the comparison resulted in equality. In the second cycle the State the selection triggers sensed and the content of those Registers that have set their selection trigger are accessed via the Read out data path 10 to mask register 3, which transfers all digits except the eight on the left via data path 8 to I / O1. The content of I / OI is then sent to the bus via data path 4 5 transferred.

In contrast to known associative memories, the associative memory 1 according to the invention has a second input / output register 1/02, and either 1/01 or 1/02 can be used. Especially with regard to the In Flg. 1, the decoder 11 generates control signals, whereby the search argument can be taken either from I / O1 or 1/02. Furthermore, in the second cycle, an operation can either be written from I / O1 or 1/02 into the memory arrangement 2 or read from the memory arrangement 2 into either I / O1 or 1/02.

This is effected by the control signals on lines 15 to 19 from decoder 11. When excited, the line 15 connects the data

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path 8 via mask register 3 with data path 10. When energized The line 16 connects the data path 9 via the mask register 3 to the data path 10. When energized, the enables Line 17 to register 1/01, from memory arrangement 2 data to recieve. When energized, the line 19 enables the register 1/02 to receive data from the memory arrangement 2. When excited enables line 18 to both registers 1/01 and 1/02, from the data lines 5 and 7, to which they are connected via the data paths 4 and 6, to receive data.

The decoder 11 is not described in detail here, since its use is well known. The decoder 11 consists for example from a Christmas tree network with four lines including the data path 12 or 13 as input and with 16 lines as an output, one of which is labeled in accordance with the binary signals on the input lines. Of the The marked output then sets triggers that excite control lines 14 to 19 at the appropriate times.

When using these control signals, it can be seen that the following sequence of operations is possible:

1. Set 1/01 and 1/02 via data bus 5 and 7 respectively;

2. Search using the search argument from 1/01 or 1/02;

3. Read or write between the selected word registers of the arrangement and 1/01 or 1/02; and

4. Read 1/01 or 1/02 on the data line.

Fig. 2 shows an associative memory 20 according to the invention, which has been modified compared to the memory 1 described in FIG. 1 in that the memory 20 is the mask between the search and Can change the access cycles of an operation. The single Maeken

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register 3 of FIG. 1 is replaced by an input or search argument mask register 23 and two output mask registers 24 and 25. The I / Ol and 1/02 registers are separated by registers 21 and 22, which only serve as input registers. The output from the memory arrangement 2 takes place via the data path 26 and either via the mask register 24 and the data path 27 to the bus 5 or via the mask register 25 and the data path 28 to the Manifold 7.

To simplify the drawing, the control lines from the decoder 11 have not been shown, but it can be seen that the Decoder 11 sends out signals specifying the mask configuration for mask register 23, from which register, 21 or 22, the search argument must be taken and whether the operation is a read operation in array 2, which register, 24 or 25, the data must be transferred to the associated bus 5 or 7 and which mask is to be used. The ability to defining which data field must be transferred to the bus is of course useful when several associative memories 20 are connected to a bus. Any memory can work simultaneously and independently with different characters of multi-character information, and the use of non-overlapping output masks for different memories causes a problem Result that applies to the respective mask and at the same time to the Manifold is aligned.

In Fig. 3a are typical locations of the mask register 23 for the Case shown in which the memory arrangement 2 consists of binary memory cells. Assume that only two masks are used are: Mask 1, in which the search argument goes beyond digits 0 to 7 of register 23, counting from the left and the Writing into the memory arrangement 2 takes place by means of the remaining positions, and mask 2 in which the search argument is via the Places O to 15 of register 23 and writing in the memory arrangement 2 takes place by means of the remaining places. In Fig. 3 line 10a is a typical line of the

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Places 0 to 7 of data path 10, line 10b is one typical line from digits 8-15 and line 10c is a typical line from higher digits. The lines 8a to 8c are corresponding lines of the data path 8 from the input register to the mask register 23, and the lines 9a to 9c are corresponding lines of the data path 9 from the input register 22 to the mask register 23. The meaning of the control lines on the right of Fig. 3 is as follows:

Line 14: nose information; if line 14 is energized, use mask 1, otherwise mask 2;

Line 15: when energized, use data from register 21; Line 16: when energized, use data from register 22; Line S: when energized, perform a seek operation;

Line W: when energized, perform a write operation, i.e. transfer data to memory array 2;

Line CIt, when energized, indicates cycle 1 time; Line C2: when energized, it indicates cycle 2 time.

When the line 15 is energized, the AND circuits 31a to 31c permeable and the binary data on lines 8a to 8c are input to the via the OR circuits 33a to 33c AND circuits 34a to 34c are transmitted. In a similar way, when line 16 is energized, dl · AND circuits 32a to 32c are conductive, and dl · binary data on lines 9a to 9c are via the OR circuits 33a to 33c as an input iu dan AND circuits 34a to 34c transmitted. Line 14 has one Junction 14a and an inverter 35 * When the line 14 is not energized, the output line of the inverter 35 is energized and

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yields a signal M2, indicating that mask 2 is using shall be.

Under the assumed operating conditions, lines 10a search argument data only since both masks 1 and 2 go beyond positions 0 through 7 of the mask register and the line will not used to transfer data for a write operation. Accordingly, the inputs of the AND circuit 34a are the data output the OR circuit 33a, the line S, the line Cl - since a search takes place in the first cycle of the two-cycle operation. It is not necessary to specify mask data since both masks 1 and 2 require the line 10a in a search operation.

Search argument data under mask 2 and write data under mask 1 are on line 10b. The AND circuit 36 has control lines C1, S and 14a as inputs. Its output is connected to the Woex OR circuit 38 to the input of the AND circuit 34b. Furthermore, the control lines C2, W and 14 are inputs to an AND circuit 37, the output of which is connected via the OR circuit 38 to an input of the AND circuit 34b. AND circuit 36 is energized when line 10b is to carry search argument data , and AND circuit 37 is energized when line 10b is to carry write data. The line IQc only carries write data and so the AND circuit 34c has a data input from the OR circuit 33c and control inputs from the lines W and C2.

FIG. 3b shows the modifications of the mask register gate of FIG. 3a when the memory arrangement 2 consists of memory cells with three types of states. Each memory cell can assume stable states that represent binary 1, binary 0 and X. The X state is such that the cell does not signal an exceptional state, whichever query signals have been applied to it during an associative search operation. A cell can, for example, have the configuration according to FIG. 3c. The electronic circuit that makes up the dl storage cell SC is located between a collector

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line 131 and a word line 132 and between a bit line pair L and R. The cells SC of the same word have common collector and word lines 131 and 132, respectively, whereas the cells for the same position of different words have common bit lines L and R. To query the cell SC for the binary 0 state, the potential on the bit line L is lowered relative to an external voltage and the potential on the bit line L is increased. If the cell SC is not in the binary 0 or in the X stable state, the word line 132 carries current, which indicates an exception state. To a binary

To write to the cell is 0, the same potentials as applied to the bit lines in retrieving of the cell, the signals of the collector line 131 and word line 132 are however varied, so that the potentials interfere on the bit lines the status of the cell and cause the Cell assumes the stable binary O status. By exchanging the potentials on the bit lines , the cell can be queried for a binary 1 or a binary one

1 can be written into the cell . In order to write an X into the cell , the potentials of the collector line 131 and the word line 132 are made equal to those of a write operation, and the potentials of the bit lines are raised relative to the reference voltage. In the case of a cell which consists of two bistable circuits, it was not necessary for the raised bit line potentials to be applied simultaneously. Accordingly, an X is written in two operations. During the first operation, a binary 0 is roped into the input area and is written when the bit line L is masked. In the second operation, a binary 1 is set in the input register and is written with the bit line R masked. The first operation is called right write and the second is called left write.

In Fig. 3b parts of the same locations of the mask register 23 are shown as in Fig. 3a. The AND circuits 34a to 34c in Fig. 3a are replaced in Fig. 3c by pairs of AND circuits, each AND circuit having a driver, not shown, for a developed

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talking bit line controls. In Fig. 3b the output of the OR circuit 33a is inverted and as an input with the AND switch 134a and is also in its real form as a » connected to the AND switch 135a. Further inputs to the AND switches 134a and 135a are the signal lines Cl and S from Decoders which, when energized, indicate that the cycle 1 time and a seek operation is required. If e.g. after binary O is to be searched for, the output of the AND switch 134a is energized and the output of AND switch 135 is not energized. The combination of the states of the outputs of AND switches 134a and 135a is detected by the drivers and appropriate Potentials applied to the bit lines.

An inverted output of the OR circuit 33b is included as an input connected to AND switches 134bl and 134b2 and the real output the OR circuit 33b is an input to the AND switches 135bl and 135b2 connected. Lines M2, Cl and S are used as inputs connected to AND switches 134b2 and 135b2. The lines Ml and C2 are as inputs with both AND switches 134bl and 135bl connected to the word line WL, which is then excited when a write left operation is required, or * are with connected to AND switches 134bI and line WR which are energized when a right write operation is required. Both lines WL and WR are energized when a write operation is required. The outputs of AND switches 134bl and 134b2 are inputs for an OR circuit 136, the output of which controls the potential on the L bit line. The OR circuit 137 that starts with the outputs of the AND circuits 135bl and 135b2 are connected, serves a similar purpose for bit line R.

An inverted output of the OR circuit 33c is connected to the input of AND switch 134c, and the real output goes to the input of AND switch 135c. The line C2 is with the inputs both AND switches 134c and 135c connected, the line WL leads to the input of the AND switch 134c and the line WR to the

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Input of AND switch 135c.

The mode of operation of the mask register in FIG. 3b is analogous to that of the register in FIG. 3a and is therefore not explained again.

The FIGS. 3a and 3b thus show how the data can be selected from either register 21 or register 22 and as Search argument can be used in an access operation or as a source for data which are written into the memory arrangement 2 should.

The invention is not limited to the entire search argument must be taken from a single register. The search argument can result from data in two or more input registers be translated that non-overlapping fields of the input register hidden or that in AND, OR or EXCLUSIVE OR operations overlapping fields of the register are logically combined.

FIG. 4 shows the modification of the circuit of FIG. 3 which is required for this logical combination and also shows a single digit of the left eight digits of the mask register 23. Beyond the circuit of FIG. 3, the data lines 8 and 9 with the Inputs of an OR circuit 41 and an AND circuit 42 connected. The output of the OR circuit 41 is connected to the input of an AND circuit 43 which has a control line 44 as a further input. The output of the AND switch 42 is connected to the input of an AND switch 45, which also has a control line 46 as a further input. Lines 16 and 16 remain de-energized and in order to transfer the OR function of the data on lines 8 and 9 to OR switch 33, control line 44 is energized and the AND function of the data on lines 8 and 9 to OR To transmit switch 33 , the control line 46 is energized. The control lines 44 and 46 are selectively activated by signals from the decoder 11 in the same manner

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how the lines 15 and 16 are energized. On the OR switch 41 and the associated control line 44 can be omitted if the lines 15 and 16 are excited at the same time, in which case the output of the OR circuit 3 3 represents the OR function of the data in the two input registers. The EXCLUSIVE OR function can be added in parallel to the AND circuit 42 and OR circuit 41 can be achieved.

Fig. 5 shows the modification of the circuit of Fig. 3, which for hiding non-overlapping fields from ^ both input registers is required for use as a search argument in a search operation. The positions 0 to 15 of the mask register 23 are divided into groups of four, since the size of a character is usually 4 bits, and separate control lines 15a to 15d and 16a through 16d hide data to AND switches 34 (see FIG. 3) of each digit group. The control line 15a is used as an input all AND switches 31 (see Fig. 3) of the positions O to 3 of the Mask register connected and the control line 15b leads as an input to all ÜND switches 31 of positions 4 to 7 of the mask register and it is similar with the control lines 15c and 15d. The control line 16a is an input with all AND switches 32 of positions 0 to 3 of the mask register and it is similar with the control lines 16b and 16d with regard to the positions 4 to 7, 8 to 11 and 12 to 15. The control lines 15 and 16 of the Fig. 3 are omitted. With the arrangement of FIG. 5 can by selectively energizing leads 15a to 15d and 16a to 16d, e.g. the lines 15a, 15b, 16c and I6d through the decoder 11 different Combinations of the fields from the input register to the mask register can be hidden. The arrangement of FIG. 5 can with the Arrangement of Fig. 4 can be combined.

The input registers of an associative memory according to the invention do not need, as it drawersLach in Figures 1 and is shown to be as wide as 3ein as rlLe storage array, for the different fields of the arrangement can have different positions

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registers are made available. An embodiment in this technique is illustrated in FIG. 6, in which the associative memory array 61 is connected to the bus via register 62 63 and is connected to the bus 65 via the register 64. A second associative memory array 66 is above the register 67 is connected to the bus 63 and via the register 68 to the bus 65. The memory arrays and Registers are part of the memories as described in connection with FIGS. Inessential elements are omitted been. The registers 62 and 64 and the register 67 go through the positions 0 to 7 of the corresponding memory arrangements 61 and 66 out. The register 68 extends beyond the positions 8 to 15 of the memory arrangement 66.

With the arrangement shown, data that is aligned with the same locations in memory 61 can be placed in adjacent groups of locations aligned in memory 66. A first group of 8 bits is transferred from memory 61 to memory 66 via registers 62 and 67 and a second group of 8 bits via registers 64 and 68 to the same word register of array 66 as the first Transfer group.

Claims (6)

PATENT CLAIMS ί. Associative memory with input / output register, mask register and the data content of the word registers containing the memory, characterized in that the associative memory (1, 20) from a plurality of input registers (I / O1, 1/02, Fig. 1; 21, 22, Fig. 2) which are used in associative memory access operation contain used search arguments, and from a control (11) for the selection of one or multiple input registers as the source of a search argument. 2. Associative memory according to claim 1, characterized in that the field of the search argument from a mask register (23) it is determined in which selecting control devices the content of one or more input registers Hide (21, 22) towards the mask register. 3. Associative memory according to claim 2, characterized in that the mask register (3, 23) is a selected one provides a logical combination of search argument data from more than one input register (I / Ol, 1/02; 21, 22). 4. Associative memory according to claim 2 to 3, characterized in that that the mask register (3, 23) different fields of the search argument from different input registers (I / Ol, 1/02; 21, 22) fades out. 5. Associative memory according to claim 1 to 4, characterized in that that the input registers are input / output registers (I / Ol, 1/02) and are controlled so that the the data read out from the memory (2) are selectively transferred to one of the input / output registers. 6. Associative memory according to claim 1 to 5, characterized in that that the output field of the memory (2) 009841/1718 Docket UK 968 014 read out data is determined by output mask registers (24, 25). Associative memory according to Claims 1 to 6, characterized in that that the memory (2) consists of several word registers with the same number of digits and the input register have fewer digits than a word register. 00 98A 1/1718 Docket UK 968 014